| /freebsd-src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterBankEmitter.cpp | 113 const std::vector<RegisterBank> &Banks);
115 const std::vector<RegisterBank> &Banks);
117 std::vector<RegisterBank> &Banks);
131 const std::vector<RegisterBank> &Banks) { in emitHeader()
139 for (const auto &Bank : Banks) in emitHeader()
150 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
217 raw_ostream &OS, StringRef TargetName, std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
223 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
246 for (const auto &Bank : Banks) { in emitBaseClassImplementation()
260 for (const auto &Bank : Banks) in emitBaseClassImplementation()
129 emitHeader(raw_ostream & OS,const StringRef TargetName,const std::vector<RegisterBank> & Banks) emitHeader() argument
148 emitBaseClassDefinition(raw_ostream & OS,const StringRef TargetName,const std::vector<RegisterBank> & Banks) emitBaseClassDefinition() argument
216 emitBaseClassImplementation(raw_ostream & OS,StringRef TargetName,std::vector<RegisterBank> & Banks) emitBaseClassImplementation() argument
298 std::vector<RegisterBank> Banks; run() local
[all...] |
| /freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | img,meta-intc.txt | 11 - num-banks: Specifies the number of interrupt banks (each of which can
58 // Number of interrupt banks
59 num-banks = <2>;
|
| /freebsd-src/sys/dev/qat/qat_hw/qat_c4xxx/ |
| H A D | adf_c4xxx_res_part.c | 64 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_sym_threads()
82 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_asym_threads()
102 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_dc_threads()
125 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb_c4xxx()
176 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb_c4xxx()
|
| /freebsd-src/sys/dev/ice/ |
| H A D | ice_nvm.c | 462 struct ice_bank_info *banks = &hw->flash.banks; in ice_get_flash_bank_offset()
469 offset = banks->nvm_ptr; in ice_get_flash_bank_offset()
470 size = banks->nvm_size; in ice_get_flash_bank_offset()
471 active_bank = banks->nvm_bank; in ice_get_flash_bank_offset()
474 offset = banks->orom_ptr; in ice_get_flash_bank_offset()
475 size = banks->orom_size; in ice_get_flash_bank_offset()
476 active_bank = banks->orom_bank; in ice_get_flash_bank_offset()
479 offset = banks->netlist_ptr; in ice_get_flash_bank_offset()
480 size = banks in ice_get_flash_bank_offset()
464 struct ice_bank_info *banks = &hw->flash.banks; ice_get_flash_bank_offset() local
1329 struct ice_bank_info *banks = &hw->flash.banks; ice_determine_active_flash_banks() local
[all...] |
| /freebsd-src/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-atlas7.txt | 7 - gpio-banks : How many gpio banks on this controller
28 gpio-banks = <2>;
|
| H A D | brcm,kona-gpio.txt | 8 support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
18 number of GPIO banks on the SoC. The interrupts must be ordered by bank,
19 starting with bank 0. There is always a 1:1 mapping between banks and
|
| H A D | brcm,kona-gpio.yaml | 11 support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
35 GPIO banks on the SoC. The interrupts must be ordered by bank, starting
36 with bank 0. There is always a 1:1 mapping between banks and IRQs.
|
| H A D | mediatek,mt7621-gpio.txt | 3 The IP core used inside these SoCs has 3 banks of 32 GPIOs each.
4 The registers of all the banks are interwoven inside one single IO range.
|
| H A D | mediatek,mt7621-gpio.yaml | 13 The IP core used inside these SoCs has 3 banks of 32 GPIOs each.
14 The registers of all the banks are interwoven inside one single IO range.
|
| H A D | brcm,brcmstb-gpio.txt | 5 interrupt is shared for all of the banks handled by the controller.
26 correspond to number of banks suggested by the 'reg' property.
|
| /freebsd-src/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | samsung,pinctrl-gpio-bank.yaml | 31 For GPIO banks supporting external GPIO interrupts or external wake-up
37 For GPIO banks supporting external GPIO interrupts or external wake-up
42 For GPIO banks supporting direct external wake-up interrupts (without
|
| H A D | pinctrl-st.txt | 16 First type is via irqmux, single interrupt is used by multiple gpio banks. This
17 reduces number of overall interrupts numbers required. All these banks belong to
44 with other gpio banks via irqmux.
45 a irqline and gpio banks.
|
| /freebsd-src/sys/contrib/device-tree/Bindings/misc/ |
| H A D | qcom,fastrpc.txt | 40 = COMPUTE BANKS
41 Each subnode of the Fastrpc represents compute context banks available
43 - All Compute context banks MUST contain the following properties:
|
| /freebsd-src/sys/arm/allwinner/ |
| H A D | aw_gpio.c | 94 const char *banks;
105 .banks = "abcdefghi",
117 .banks = "bcdefg",
129 .banks = "abcdefghi",
141 .banks = "abcdefgh",
153 .banks = "abcdefgh",
164 .banks = "lm",
176 .banks = "bcdefgh",
189 .banks = "acdefg",
196 .banks
87 const char *banks; global() member
[all...] |
| /freebsd-src/sys/dev/qat/qat_common/ |
| H A D | adf_hw_arbiter.c | 53 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb()
73 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_gen2_arb()
187 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb()
220 csr = accel_dev->transport->banks[0].csr_addr; in adf_disable_arb()
|
| H A D | adf_transport.c | 189 bank = &trans_data->banks[bank_num]; in adf_poll_bank()
256 /* Loop over banks and call adf_poll_bank */ in adf_poll_all_banks()
259 bank = &trans_data->banks[bank_num]; in adf_poll_all_banks()
419 bank = &transport_data->banks[bank_num]; in adf_create_ring()
677 etr_data->banks = kzalloc_node(size, in adf_init_etr_data()
703 adf_init_bank(accel_dev, &etr_data->banks[i], i, csr_addr); in adf_init_etr_data()
711 kfree(etr_data->banks); in adf_init_etr_data()
751 cleanup_bank(&etr_data->banks[i]); in adf_cleanup_etr_handles()
771 kfree(etr_data->banks); in adf_cleanup_etr_data()
|
| H A D | adf_vf_isr.c | 178 TASK_INIT(&priv_data->banks[i].resp_handler, in adf_setup_bh()
181 &priv_data->banks[i]); in adf_setup_bh()
199 &transport->banks[i].resp_handler, in adf_cleanup_bh()
202 &transport->banks[i].resp_handler); in adf_cleanup_bh()
230 struct adf_etr_bank_data *bank = &etr_data->banks[i]; in adf_isr()
|
| /freebsd-src/sys/contrib/device-tree/Bindings/ata/ |
| H A D | cavium-compact-flash.txt | 12 - reg: The base address of the CF chip select banks. Depending on
13 the device configuration, there may be one or two banks.
|
| /freebsd-src/sys/contrib/device-tree/Bindings/net/ |
| H A D | cavium-mix.txt | 9 - reg: The base addresses of four separate register banks. The first
16 register banks corresponds to this MIX device.
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/BPF/GISel/ |
| H A D | BPFRegisterBanks.td | 1 //===-- BPFRegisterBanks.td - Describe the BPF Banks -------*- tablegen -*-===//
10 /// Define the BPF register banks used for GlobalISel.
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kRegisterBanks.td | 1 //===-- M68kRegisterBanks.td - Describe the M68k Banks -----*- tablegen -*-===//
10 /// Define the M68k register banks used for GlobalISel.
|
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 10 /// This API is responsible for handling the register banks.
39 /// Holds all the information related to register banks.
91 /// different register banks.
147 /// How the value is broken down between the different register banks.
388 /// Hold the set of supported register banks.
391 /// Total number of register banks.
394 /// Hold the sizes of the register banks for all HwModes.
566 /// not change, only the register banks.
602 /// Get the total number of register banks.
616 /// coverage for the register banks
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCRegisterBanks.td | 1 //===-- PPCRegisterBanks.td - Describe the PPC Banks -------*- tablegen -*-===//
10 /// Define the PPC register banks used for GlobalISel.
|
| /freebsd-src/sys/x86/x86/ |
| H A D | mca.c | 100 static int mca_banks; /* Number of per-CPU register banks. */
806 * When the banks are polled, check to see if the threshold in update_threshold()
886 * This scans all the machine check banks of the current CPU to see if
904 * For a CMCI, only check banks this CPU is in mca_scan()
994 * Scan the machine check banks on all CPUs by binding to each CPU in
1178 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid))); in cmci_monitor()
1227 * For resume, reset the threshold for any banks we monitor back to
1236 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid))); in cmci_resume()
1242 /* Ignore banks not monitored by this CPU. */ in cmci_resume()
1289 * Kludge: On 10h, banks after 4 are not thresholding but also may have in amd_thresholding_monitor()
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/ |
| H A D | gpio.txt | 17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
25 Example of four SOC GPIO banks defined as gpio-controller nodes:
|