Searched +full:ast2600 +full:- +full:lpc +full:- +full:ctrl (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Aspeed Low Pin Count (LPC) Bus Controller11 - Andrew Jeffery <andrew@aj.id.au>12 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth17 primary use case of the Aspeed LPC controller is as a slave on the bus21 The LPC controller is represented as a multi-function device to account for the[all …]
2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth7 primary use case of the Aspeed LPC controller is as a slave on the bus11 The LPC controller is represented as a multi-function device to account for the16 * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the17 physical properties of some LPC pins, configuration of serial IRQs, and18 APB-to-LPC bridging amonst other functions.20 * An LPC Host Interface Controller: Manages functions exposed to the host such21 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART28 Additionally the state of the LPC controller influences the pinmux[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/interrupt-controlle593 lpc: lpc@1e789000 { global() label [all...]