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/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dloop-prefetch.ll1 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs -asm-verbose=0 < %s | FileCheck --ch…
2 …-mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s -filetype=obj | llvm-objdump -d --arch-na…
3 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
5 ; GFX8-NOT: s_inst_prefetch
6 ; GFX8-NOT: .palign 6
8 ; GCN-LABEL: test_loop_64
9 ; GFX10: s_movk_i32 s{{[0-9]+}}, 0x400
10 ; GFX10-DIS-NEXT: {{^$}}
11 ; GFX10-ASM-NEXT: [[L1:.LBB[0-9_]+]]:
12 ; GFX10-DIS-NEXT: <[[L1:L[0-9]+]]>:
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H A Ddirective-amdgcn-target.ll1 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 < %s | FileCheck --check-prefixes=GFX600 %s
2 ; RUN: llc -mtriple=amdgcn
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H A Dhsa-note-no-func.ll1 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx600 | FileCheck --check-prefixes=NONHSA-SI600 %s
2 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx601 | FileCheck --check-prefixes=NONHSA-SI601 %s
3 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx602 | FileCheck --check-prefixes=NONHSA-SI602 %s
4 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx700 | FileCheck --check-prefix=HSA-CI700 %s
5 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA-CI700 %s
6 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx701 | FileCheck --check-prefix=HSA-CI701 %s
7 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=hawaii | FileCheck --check-prefix=HSA-CI701 %s
8 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx702 | FileCheck --check-prefix=HSA-CI702 %s
9 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx703 | FileCheck --check-prefix=HSA-CI703 %s
10 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kabini | FileCheck --check-prefix=HSA-CI703 %s
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H A Dllvm.amdgcn.kill.ll1 ; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixe
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H A Delf-header-flags-mach.ll1 ; RUN: llc -filetype=obj -mtriple=r600 -mcpu=r600 < %s | llvm-readobj --file-header - | FileCheck --chec
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H A Dlower-kernel-and-module-lds.ll1 ; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module …
2 ; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=…
10 ; CHECK: %llvm.amdgcn.module.lds.t = type { [8 x i8], [1 x i8] }
11 ; CHECK: %llvm.amdgcn.kernel.k0.lds.t = type { [16 x i8], [4 x i8], [2 x i8], [1 x i8] }
12 ; CHECK: %llvm.amdgcn.kernel.k1.lds.t = type { [16 x i8], [4 x i8], [2 x i8] }
13 ; CHECK: %llvm.amdgcn.kernel.k2.lds.t = type { [2 x i8] }
14 ; CHECK: %llvm.amdgcn.kernel.k3.lds.t = type { [4 x i8] }
17 ; CHECK: @llvm.amdgcn.module.lds = internal addrspace(3) global %llvm.amdgcn.module.lds.t poison, a…
18 …addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(3) @llvm.amdgcn.module.lds to ptr)…
19 ; CHECK: @llvm.amdgcn.kernel.k0.lds = internal addrspace(3) global %llvm.amdgcn.kernel.k0.lds.t poi…
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/llvm-project/llvm/test/Object/AMDGPU/
H A Delf-header-flags-mach.yaml1 # RUN: sed -e 's/<BITS>/32/' -e 's/<MACH>/R600_R600/' %s | yaml2obj -o %t.o.R600_R600
2 # RUN: llvm-readobj -S --file-headers %t.o.R600_R600 | FileCheck --chec
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/llvm-project/clang/test/CodeGenOpenCL/
H A Damdgpu-abi-struct-arg-byref.cl1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
2 // RUN: %clang_cc1 %s -emit-llvm -o - -cl-std=CL2.0 -O0 -tripl
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H A Daddr-space-struct-arg.cl1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
2 // RUN: %clang_cc1 %s -emit-llvm -o - -O0 -ffake-address-spac
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/llvm-project/clang/test/Driver/
H A Dcl-denorms-are-zero.cl2 // RUN: %clang -### -target amdgcn--amdhsa -nogpulib -c -mcpu=pitcairn %s 2>&1 | FileCheck -check-p…
3 …N: %clang -### -cl-denorms-are-zero -o - --target=amdgcn--amdhsa -nogpulib -c -mcpu=pitcairn %s 2>…
6 // RUN: %clang -### -target amdgcn--amdhsa -nogpulib -c -mcpu=tahiti %s 2>&1 | FileCheck -check-pre…
7 …UN: %clang -### -cl-denorms-are-zero -o - --target=amdgcn--amdhsa -nogpulib -c -mcpu=tahiti %s 2>&…
10 // RUN: %clang -### -target amdgcn--amdhsa -nogpulib -c -mcpu=fiji %s 2>&1 | FileCheck -check-prefi…
11 …RUN: %clang -### -cl-denorms-are-zero -o - --target=amdgcn--amdhsa -nogpulib -c -mcpu=fiji %s 2>&1…
14 // RUN: %clang -### -target amdgcn--amdhsa -nogpulib -c -mcpu=gfx900 %s 2>&1 | FileCheck -check-pre…
15 …UN: %clang -### -cl-denorms-are-zero -o - -target amdgcn--amdhsa -nogpulib -c -mcpu=gfx900 %s 2>&1…
18 // RUN: %clang -### -target amdgcn--amdhsa -nogpulib -c %s 2>&1 | FileCheck -check-prefixes=AMDGCN,…
19 // RUN: %clang -### -cl-denorms-are-zero -o - -target amdgcn--amdhsa -nogpulib -c %s 2>&1 | FileChe…
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H A Damdgpu-mcpu.cl1 // Check that -mcpu works for all supported GPUs.
4 // R600-based processors.
7 // RUN: %clang -### -target r600 -mcpu=r600 %s 2>&1 | FileCheck --check-prefix=R600 %s
8 // RUN: %clang -### -targe
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H A Drocm-device-libs.cl1 // REQUIRES: !system-windows
3 // Test flush-denormals-to-zero enabled uses oclc_daz_opt_on
5 // RUN: %clang -### -target amdgcn-amd-amdhsa \
6 // RUN: -x cl -mcpu=gfx900 \
7 // RUN: --rocm-path=%S/Inputs/rocm \
9 // RUN: 2>&1 | FileCheck --check-prefixes=COMMON,COMMON-DEFAULT,GFX900-DEFAULT,GFX900,WAVE64 %s
14 // RUN: %clang -### -target amdgcn-amd-amdhsa \
15 // RUN: -x cl -mcpu=gfx803 \
16 // RUN: --rocm-path=%S/Inputs/rocm \
18 // RUN: 2>&1 | FileCheck --check-prefixes=COMMON,COMMON-DEFAULT,GFX803-DEFAULT,GFX803,WAVE64 %s
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H A Damdgpu-macros.cl2 // "-target" and "-mcpu" options.
5 // R600-based processors.
8 // RUN: %clang -E -dM -target r600 -mcpu=r600 %s 2>&1 | FileCheck --check-prefixe
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/llvm-project/llvm/test/Verifier/AMDGPU/
H A Dintrinsic-immarg.ll1 ; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s
3 declare float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32>, i32, i32, i32)
5 ; CHECK: immarg operand has non-immediate parameter
6 ; CHECK-NEXT: i32 %arg
7 ; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 %arg)
8 %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 %arg)
12 declare float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32>, i32, i32, i32)
14 ; CHECK: immarg operand has non-immediat
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/llvm-project/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/
H A Dcos.ll2 ; RUN: opt < %s -passes=instsimplify -S | FileCheck %s
4 declare half @llvm.amdgcn.cos.f16(half) #0
5 declare float @llvm.amdgcn.cos.f32(float) #0
6 declare double @llvm.amdgcn.cos.f64(double) #0
9 ; CHECK-LABEL: @test_f16(
10 ; CHECK-NEXT: store volatile half 0xH3C00, ptr [[P:%.*]], align 2
11 ; CHECK-NEXT: store volatile half 0xH3C00, ptr [[P]], align 2
12 ; CHECK-NEXT: store volatile half 0xH39A8, ptr [[P]], align 2
13 ; CHECK-NEXT: store volatile half 0xH39A8, ptr [[P]], align 2
14 ; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]], align 2
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H A Dsin.ll2 ; RUN: opt < %s -passes=instsimplify -S | FileCheck %s
4 declare half @llvm.amdgcn.sin.f16(half) #0
5 declare float @llvm.amdgcn.sin.f32(float) #0
6 declare double @llvm.amdgcn.sin.f64(double) #0
9 ; CHECK-LABEL: @test_f16(
10 ; CHECK-NEXT: store volatile half 0xH0000, ptr [[P:%.*]], align 2
11 ; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]], align 2
12 ; CHECK-NEXT: store volatile half 0xH39A8, ptr [[P]], align 2
13 ; CHECK-NEXT: store volatile half 0xHB9A8, ptr [[P]], align 2
14 ; CHECK-NEXT: store volatile half 0xH3C00, ptr [[P]], align 2
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H A Dcubeid.ll2 ; RUN: opt < %s -passes=instsimplify -S | FileCheck %s
4 declare float @llvm.amdgcn.cubeid(float, float, float)
7 ; CHECK-LABEL: @test(
8 ; CHECK-NEXT: store volatile float 4.000000e+00, ptr [[P:%.*]]
9 ; CHECK-NEXT: store volatile float 2.000000e+00, ptr [[P]]
10 ; CHECK-NEXT: store volatile float 4.000000e+00, ptr [[P]]
11 ; CHECK-NEXT: store volatile float 2.000000e+00, ptr [[P]]
12 ; CHECK-NEXT: store volatile float 0.000000e+00, ptr [[P]]
13 ; CHECK-NEXT: store volatile float 0.000000e+00, ptr [[P]]
14 ; CHECK-NEXT: store volatile float 5.000000e+00, ptr [[P]]
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H A Dcubema.ll2 ; RUN: opt < %s -passes=instsimplify -S | FileCheck %s
4 declare float @llvm.amdgcn.cubema(float, float, float)
7 ; CHECK-LABEL: @test(
8 ; CHECK-NEXT: store volatile float 1.000000e+01, ptr [[P:%.*]]
9 ; CHECK-NEXT: store volatile float 1.000000e+01, ptr [[P]]
10 ; CHECK-NEXT: store volatile float 1.000000e+01, ptr [[P]]
11 ; CHECK-NEXT: store volatile float 1.000000e+01, ptr [[P]]
12 ; CHECK-NEXT: store volatile float 1.000000e+01, ptr [[P]]
13 ; CHECK-NEXT: store volatile float 1.000000e+01, ptr [[P]]
14 ; CHECK-NEXT: store volatile float -1.000000e+01, ptr [[P]]
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H A Dcubesc.ll2 ; RUN: opt < %s -passes=instsimplify -S | FileCheck %s
4 declare float @llvm.amdgcn.cubesc(float, float, float)
7 ; CHECK-LABEL: @test(
8 ; CHECK-NEXT: store volatile float 3.000000e+00, ptr [[P:%.*]]
9 ; CHECK-NEXT: store volatile float 3.000000e+00, ptr [[P]]
10 ; CHECK-NEXT: store volatile float 4.000000e+00, ptr [[P]]
11 ; CHECK-NEXT: store volatile float 4.000000e+00, ptr [[P]]
12 ; CHECK-NEXT: store volatile float -4.000000e+00, ptr [[P]]
13 ; CHECK-NEXT: store volatile float -3.000000e+00, ptr [[P]]
14 ; CHECK-NEXT: store volatile float -3.000000e+00, ptr [[P]]
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H A Dcubetc.ll2 ; RUN: opt < %s -passes=instsimplify -S | FileCheck %s
4 declare float @llvm.amdgcn.cubetc(float, float, float)
7 ; CHECK-LABEL: @test(
8 ; CHECK-NEXT: store volatile float -4.000000e+00, ptr [[P:%.*]]
9 ; CHECK-NEXT: store volatile float 4.000000e+00, ptr [[P]]
10 ; CHECK-NEXT: store volatile float -3.000000e+00, ptr [[P]]
11 ; CHECK-NEXT: store volatile float 3.000000e+00, ptr [[P]]
12 ; CHECK-NEXT: store volatile float -3.000000e+00, ptr [[P]]
13 ; CHECK-NEXT: store volatile float -4.000000e+00, ptr [[P]]
14 ; CHECK-NEXT: store volatile float -4.000000e+00, ptr [[P]]
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H A Dfract.ll2 ; RUN: opt < %s -passes=instsimplify -S | FileCheck %s
4 declare half @llvm.amdgcn.fract.f16(half)
5 declare float @llvm.amdgcn.fract.f32(float)
6 declare double @llvm.amdgcn.fract.f64(double)
9 ; CHECK-LABEL: @test_f16(
10 ; CHECK-NEXT: store volatile half 0xH0000, ptr [[P:%.*]]
11 ; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]]
12 ; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]]
13 ; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]]
14 ; CHECK-NEXT: store volatile half 0xH3400, ptr [[P]]
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/llvm-project/llvm/test/Transforms/InferAddressSpaces/AMDGPU/
H A Dflat-fadd-fmin-fmax-intrinsics.ll
/llvm-project/llvm/test/tools/llvm-objdump/ELF/AMDGPU/
H A Dsubtarget.ll7 ; ----------
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/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/
H A Drcp-contract-rsq.ll1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
2 ; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -passes=instcombine -S < %s | FileCheck %s
4 declare half @llvm.amdgcn.sqrt.f16(half)
5 declare float @llvm.amdgcn.sqrt.f32(float)
6 declare double @llvm.amdgcn.sqrt.f64(double)
8 declare half @llvm.amdgcn.rcp.f16(half)
9 declare float @llvm.amdgcn.rcp.f32(float)
10 declare double @llvm.amdgcn.rcp.f64(double)
12 declare half @llvm.amdgcn.rsq.f16(half)
13 declare float @llvm.amdgcn.rsq.f32(float)
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/llvm-project/clang/test/CodeGenHIP/
H A Dprintf.cpp1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
2 // REQUIRES: amdgpu-registered-target
3 // RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -emit-llvm -fcuda-is-device \
4 // RUN: -o - %s | FileCheck --check-prefix=AMDGCN --enable-var-scope %s
5 // RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip -emit-llvm -fcuda-is-device \
6 // RUN: -o - %s | FileCheck --check-prefix=AMDGCNSPIRV --enable-var-scope %s
12 // AMDGCN-LABEL: define dso_local noundef i32 @_Z4foo1v(
13 // AMDGCN-SAME: ) #[[ATTR0:[0-9]+]] {
14 // AMDGCN-NEXT: [[ENTRY:.*]]:
15 // AMDGCN-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5)
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