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2 # ALTERA -- Intel Altera kernel configuration file for FreeBSD/arm6423 ident ALTERA27 include "std.altera"
2 # Altera SoC support16 device dwc_socfpga # Altera SOCFPGA Ethernet MAC
1 * Altera SOCFPGA specific extensions to the Synopsys Designware Mobile7 by synopsys-dw-mshc.txt and the properties used by the Altera SOCFPGA specific13 - "altr,socfpga-dw-mshc": for Altera's SOCFPGA platform
1 Altera Passive Serial SPI FPGA Manager3 Altera FPGAs support a method of loading the bitstream over what is8 See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
1 Altera Freeze Bridge Controller Driver3 The Altera Freeze Bridge Controller manages one or more freeze bridges.
7 title: Altera Freeze Bridge Controller10 The Altera Freeze Bridge Controller manages one or more freeze bridges.
1 * Altera I2C Controller2 * This is Altera's synthesizable logic block I2C Controller for use3 * in Altera's FPGAs.
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>10 model = "Altera SOCFPGA VT";
3 * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>9 model = "Altera SOCFPGA Arria V SoC Development Kit";
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>9 model = "Altera SOCFPGA Cyclone V SoC Development Kit";
1 Altera SOCFPGA SDRAM Controller5 syscon is required by the Altera SOCFPGA SDRAM EDAC.
4 $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#7 title: Altera SOCFPGA Clock Manager
7 title: Altera mSGDMA IP core13 Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)