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/llvm-project/polly/lib/External/isl/imath/tests/
H A Dadd.tc3 add:0,0,0:0
4 add:0,0,=1:0
5 add:1,=1,=1:2
6 add:1,-1,0:0
7 add:-1,1,0:0
8 add:-1,1,=1:0
10 add:103427990038,909510006269847,0:909613434259885
11 add:128593002,-9007199254740992,0:-9007199126147990
12 add:-65537,70000,0:4463
13 add:-1000000,-6543210,0:-7543210
[all …]
/llvm-project/mlir/test/Target/LLVMIR/Import/
H A Dincorrect-instmap-assignment.ll14 %3 = add i32 %0, %1
15 %4 = add i32 %1, %3
16 %5 = add i32 %3, %4
17 %6 = add i32 %4, %5
18 %7 = add i32 %5, %6
19 %8 = add i32 %6, %7
20 %9 = add i32 %7, %8
21 %10 = add i32 %8, %9
22 %11 = add i32 %9, %10
23 %12 = add i32 %10, %11
[all …]
/llvm-project/llvm/test/Transforms/Reassociate/
H A D2012-05-08-UndefLeak.ll10 ; CHECK-NEXT: add i64 %{{.*}}, 1617
12 %t0 = add i64 %x0, 1
13 %t1 = add i64 %x0, 2
14 %t2 = add i64 %x0, 3
15 %t3 = add i64 %x0, 4
16 %t4 = add i64 %x0, 5
17 %t5 = add i64 %x0, 6
18 %t6 = add i64 %x0, 7
19 %t7 = add i64 %x0, 8
20 %t8 = add i64 %x0, 9
[all …]
/llvm-project/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dreduce-add-i64.ll4 ; This test checks whether load-zext-add and load-add reduction patterns
15 ; CHECK-NEXT: [[ADD_1:%.*]] = add nuw nsw i64 [[ZEXT]], [[ZEXT_1]]
24 %add.1 = add nuw nsw i64 %zext, %zext.1
25 ret i64 %add.1
33 ; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> [[TMP1]])
43 %add.1 = add nuw nsw i64 %zext, %zext.1
47 %add.2 = add nuw nsw i64 %add.1, %zext.2
51 %add.3 = add nuw nsw i64 %add.2, %zext.3
52 ret i64 %add.3
60 ; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> [[TMP1]])
[all …]
H A Dmultiple_reduction.ll43 ; CHECK-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[TMP17]], [[TMP18]]
46 ; CHECK-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[ADD_1]], [[TMP20]]
48 ; CHECK-NEXT: [[ADD_3:%.*]] = add nuw nsw i32 [[ADD_2]], [[TMP21]]
50 ; CHECK-NEXT: [[ADD_4:%.*]] = add nuw nsw i32 [[ADD_3]], [[TMP22]]
52 ; CHECK-NEXT: [[ADD_5:%.*]] = add nuw nsw i32 [[ADD_4]], [[TMP23]]
54 ; CHECK-NEXT: [[ADD_6:%.*]] = add nuw nsw i32 [[ADD_5]], [[TMP24]]
56 ; CHECK-NEXT: [[ADD_7:%.*]] = add nuw nsw i32 [[ADD_6]], [[TMP25]]
58 ; CHECK-NEXT: [[ADD_141:%.*]] = add nuw nsw i32 [[ADD_7]], [[TMP26]]
60 ; CHECK-NEXT: [[ADD_1_1:%.*]] = add nuw nsw i32 [[ADD_141]], [[TMP27]]
62 ; CHECK-NEXT: [[ADD_2_1:%.*]] = add nu
[all...]
/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
H A Dreassociated-loads.ll8 ; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> [[TMP0]])
15 %add.i.1.i = add i8 %vecext.i.i.1.i, %vecext.i.i.i
17 %add.i.2.i = add i8 %vecext.i.i.2.i, %add.i.1.i
19 %add.i.3.i = add i8 %vecext.i.i.3.i, %add.i.2.i
21 %add.i.4.i = add i8 %vecext.i.i.4.i, %add.i.3.i
23 %add.i.5.i = add i8 %vecext.i.i.5.i, %add.i.4.i
25 %add.i.6.i = add i8 %vecext.i.i.6.i, %add.i.5.i
27 %add.i.7.i = add i8 %vecext.i.i.7.i, %add.i.6.i
29 %add.i.8.i = add i8 %vecext.i.i.8.i, %add.i.7.i
31 %add.i.9.i = add i8 %vecext.i.i.9.i, %add.i.8.i
[all …]
H A Darith-add-load.ll19 ; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i8> [[TMP1]], [[TMP0]]
26 %add = add i8 %1, %0
27 store i8 %add, ptr %r, align 1
32 %add.1 = add i8 %3, %2
33 store i8 %add.1, ptr %arrayidx2.1, align 1
38 %add.2 = add i8 %5, %4
39 store i8 %add.2, ptr %arrayidx2.2, align 1
44 %add.3 = add i8 %7, %6
45 store i8 %add.3, ptr %arrayidx2.3, align 1
54 ; CHECK-NEXT: [[TMP2:%.*]] = add <8 x i8> [[TMP1]], [[TMP0]]
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dsoft-clause-exceeds-register-budget.ll32 %i6 = add i32 %i4, %i5
34 %conv = add i32 %i6, %i7
37 %add.ptr22 = getelementptr inbounds float, ptr addrspace(4) %wei_ptr, i64 undef
74 %i_ptr.0288 = phi ptr addrspace(1) [ %in.ptr1, %entry ], [ %add.ptr47.3, %for.cond28.preheader ]
75 %w_ptr.0287 = phi ptr addrspace(4) [ %add.ptr22, %entry ], [ %add.ptr74, %for.cond28.preheader ]
78 %add.ptr47 = getelementptr inbounds float, ptr addrspace(1) %i_ptr.0288, i64 49
79 %i9 = load float, ptr addrspace(1) %add.ptr47, align 4
80 %add.ptr47.1 = getelementptr inbounds float, ptr addrspace(1) %i_ptr.0288, i64 98
81 %i10 = load float, ptr addrspace(1) %add.ptr47.1, align 4
82 %add.ptr47.2 = getelementptr inbounds float, ptr addrspace(1) %i_ptr.0288, i64 147
[all …]
/llvm-project/llvm/test/Transforms/SCCP/
H A Dadd-nuw-nsw-flags.ll8 ; CHECK-NEXT: [[ADD_1:%.*]] = add nuw i8 [[A_SHR]], 1
9 ; CHECK-NEXT: [[ADD_2:%.*]] = add nuw nsw i8 [[A_SHR]], -128
10 ; CHECK-NEXT: [[ADD_3:%.*]] = add nsw i8 [[A_SHR]], -127
11 ; CHECK-NEXT: [[ADD_4:%.*]] = add nsw i8 [[A_SHR]], -1
19 %add.1 = add i8 %a.shr, 1
20 %add.2 = add i8 %a.shr, 128
21 %add.3 = add i
[all...]
/llvm-project/llvm/test/CodeGen/SystemZ/
H A Dint-add-11.ll12 %add = add i32 %val, 127
13 store i32 %add, ptr %ptr
23 %add = add i32 %val, 127
24 store i32 %add, ptr %ptr
36 %add = add i32 %val, 128
37 store i32 %add, ptr %ptr
47 %add = add i32 %val, -128
48 store i32 %add, ptr %ptr
59 %add = add i32 %val, -129
60 store i32 %add, ptr %ptr
[all …]
H A Dint-add-12.ll11 %add = add i64 %val, 127
12 store i64 %add, ptr %ptr
22 %add = add i64 %val, 127
23 store i64 %add, ptr %ptr
35 %add = add i64 %val, 128
36 store i64 %add, ptr %ptr
46 %add = add i64 %val, -128
47 store i64 %add, ptr %ptr
58 %add = add i64 %val, -129
59 store i64 %add, ptr %ptr
[all …]
/llvm-project/llvm/test/MC/X86/apx/
H A Dadd-intel.s3 # CHECK: {evex} add bl, 123
5 {evex} add bl, 123
6 # CHECK: {nf} add bl, 123
8 {nf} add bl, 123
9 # CHECK: add cl, bl, 123
11 add cl, bl, 123
12 # CHECK: {nf} add cl, bl, 123
14 {nf} add cl, bl, 123
15 # CHECK: {evex} add dx, 123
17 {evex} add dx, 123
[all …]
/llvm-project/llvm/test/CodeGen/LoongArch/ir-instruction/
H A Dadd.ll5 ;; Exercise the 'add' LLVM IR: https://llvm.org/docs/LangRef.html#add-instruction
10 ; LA32-NEXT: add.w $a0, $a0, $a1
15 ; LA64-NEXT: add.d $a0, $a0, $a1
17 %add = add i1 %x, %y
18 ret i1 %add
24 ; LA32-NEXT: add.w $a0, $a0, $a1
29 ; LA64-NEXT: add.d $a0, $a0, $a1
31 %add = add i8 %x, %y
32 ret i8 %add
38 ; LA32-NEXT: add.w $a0, $a0, $a1
[all …]
/llvm-project/llvm/test/Analysis/CostModel/RISCV/
H A Dreduce-add.ll9 ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> undef)
10 ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.add.v2i1(<2 x i1> undef)
11 ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.vector.reduce.add.v4i1(<4 x i1> undef)
12 ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.vector.reduce.add.v8i1(<8 x i1> undef)
13 ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.vector.reduce.add.v16i1(<16 x i1> undef)
14 ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32 = call i1 @llvm.vector.reduce.add.v32i1(<32 x i1> undef)
15 ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V64 = call i1 @llvm.vector.reduce.add.v64i1(<64 x i1> undef)
16 ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V128 = call i1 @llvm.vector.reduce.add.v128i1(<128 x i1> undef)
20 ; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> undef)
21 ; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.add
[all...]
/llvm-project/llvm/test/Analysis/ScalarEvolution/
H A Dptrtoint-global.ll12 ; CHECK-NEXT: %add = add i64 ptrtoint (ptr @glob.i32.align2 to i64), 5
17 %add = add i64 ptrtoint (ptr @glob.i32.align2 to i64), 5
18 ret i64 %add
24 ; CHECK-NEXT: %add = add i64 ptrtoint (ptr @glob.i32.align2 to i64), 6
29 %add = add i64 ptrtoint (ptr @glob.i32.align2 to i64), 6
30 ret i64 %add
36 ; CHECK-NEXT: %add = add i64 ptrtoint (ptr @glob.i32.align8 to i64), 7
41 %add = add i64 ptrtoint (ptr @glob.i32.align8 to i64), 7
42 ret i64 %add
48 ; CHECK-NEXT: %add = add i64 ptrtoint (ptr @glob.i32.align8 to i64), 8
[all …]
/llvm-project/llvm/test/Transforms/InstCombine/
H A Dadd2.ll11 %tmp5 = add i64 %tmp3, %A
23 %F = add i32 %B, %C
36 %F = add i32 %B, %C
45 %B = add nuw i32 %A, %A
51 ; CHECK-NEXT: [[ADD:%.*]] = xor <2 x i1> [[A:%.*]], [[B:%.*]]
52 ; CHECK-NEXT: ret <2 x i1> [[ADD]]
54 %add = add <2 x i1> %A, %B
55 ret <2 x i1> %add
60 ; CHECK-NEXT: [[ADD
[all...]
H A Dadd_or_sub.ll14 %add = add nuw i32 %or, %x
15 ret i32 %add
21 ; CHECK-NEXT: [[TMP1:%.*]] = add nsw i8 [[X]], -1
22 ; CHECK-NEXT: [[ADD:%.*]] = and i8 [[TMP1]], [[X]]
23 ; CHECK-NEXT: ret i8 [[ADD]]
28 %add = add nsw i8 %x, %or
29 ret i8 %add
40 %add
[all...]
/llvm-project/llvm/test/CodeGen/Hexagon/
H A Dmemops.ll10 %add = add nsw i32 %conv, 5
11 %conv1 = trunc i32 %add to i8
23 %add = add nsw i32 %conv1, %conv
24 %conv2 = trunc i32 %add to i8
90 %add.ptr = getelementptr inbounds i8, ptr %p, i32 %i
91 %0 = load i8, ptr %add.ptr, align 1
93 %add = add ns
[all...]
/llvm-project/llvm/test/tools/llvm-ar/
H A Dadd-library.test1 RUN: yaml2obj %S/Inputs/add-lib1.yaml -o %t-add-lib1.o
2 RUN: yaml2obj %S/Inputs/add-lib2.yaml -o %t-add-lib2.o
3 RUN: yaml2obj %S/Inputs/add-lib2.yaml -o %t-add-lib3.o
6 RUN: llvm-ar crs %t.ar %t-add-lib1.o
7 RUN: llvm-ar cqs %t.ar %t-add-lib2.o
10 CHECK-NAMES-NO-ADDLIB: add-library.test.tmp-add-lib1.o
11 CHECK-NAMES-NO-ADDLIB: add-library.test.tmp-add-lib2.o
14 CHECK-SYMBOLS-NO-ADDLIB: add-lib1
15 CHECK-SYMBOLS-NO-ADDLIB: add-lib2
18 RUN: llvm-ar crs %t1.ar %t-add-lib3.o
[all …]
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dcommon-chain.ll43 ; CHECK-NEXT: add r8, r4, r7
44 ; CHECK-NEXT: add r7, r5, r4
45 ; CHECK-NEXT: add r5, r5, r8
46 ; CHECK-NEXT: add r7, r3, r7
47 ; CHECK-NEXT: add r5, r3, r5
81 %add = add i64 %i.047, %base1
82 %add.ptr9.idx = add i64 %add,
[all...]
/llvm-project/llvm/test/tools/llvm-reduce/
H A Dreduce-operands-int.ll12 ; CHECK-INTERESTINGNESS: = add i32 %
13 ; CHECK-INTERESTINGNESS: = add i32
14 ; CHECK-INTERESTINGNESS: = add i32
15 ; CHECK-INTERESTINGNESS: = add i32
16 ; CHECK-INTERESTINGNESS: = add i32
18 ; CHECK-INTERESTINGNESS: = add <2 x i32> %
19 ; CHECK-INTERESTINGNESS: = add <2 x i32>
20 ; CHECK-INTERESTINGNESS: = add <2 x i32>
21 ; CHECK-INTERESTINGNESS: = add <2 x i32>
22 ; CHECK-INTERESTINGNESS: = add <
[all...]
/llvm-project/llvm/test/CodeGen/X86/
H A D2009-03-23-MultiUseSched.ll253 %tmp25 = add i64 %tmp6, %tmp5 ; <i64> [#uses=1]
254 %tmp26 = add i64 %tmp25, %tmp4 ; <i64> [#uses=1]
255 %tmp27 = add i64 %tmp7, %tmp4 ; <i64> [#uses=1]
256 %tmp28 = add i64 %tmp27, %tmp26 ; <i64> [#uses=1]
257 %tmp29 = add i64 %tmp28, %tmp24 ; <i64> [#uses=2]
258 %tmp30 = add i64 %tmp2, %tmp1 ; <i64> [#uses=1]
259 %tmp31 = add i64 %tmp30, %tmp ; <i64> [#uses=1]
260 %tmp32 = add i64 %tmp2, %tmp1 ; <i64> [#uses=1]
261 %tmp33 = add i64 %tmp31, %tmp32 ; <i64> [#uses=1]
262 %tmp34 = add i64 %tmp29, %tmp3 ; <i64> [#uses=5]
[all …]
/llvm-project/llvm/test/Transforms/ConstraintElimination/
H A Dshl.ll49 ; CHECK-NEXT: [[START_ADD_1:%.*]] = add nuw i8 [[START]], [[START]]
58 %start.add.1 = add nuw i8 %start, %start
59 %t = icmp ule i8 %start.add.1, %start.shl.2
70 ; CHECK-NEXT: [[START_ADD_1:%.*]] = add nuw i8 [[START]], [[START]]
80 %start.add.1 = add nuw i8 %start, %start
81 %f = icmp ult i8 %start.add.1, %start.shl.2
92 ; CHECK-NEXT: [[START_ADD_1:%.*]] = add nuw i8 [[START]], [[START]]
93 ; CHECK-NEXT: [[START_ADD_2:%.*]] = add nuw i8 [[START_ADD_1]], [[START_ADD_1]]
101 %start.add.1 = add nuw i8 %start, %start
102 %start.add.2 = add nuw i8 %start.add.1, %start.add.1
[all …]
H A Dmul.ll49 ; CHECK-NEXT: [[START_ADD_1:%.*]] = add nuw i8 [[START]], [[START]]
58 %start.add.1 = add nuw i8 %start, %start
59 %t = icmp ule i8 %start.add.1, %start.mul.2
71 ; CHECK-NEXT: [[START_ADD_1:%.*]] = add nuw i8 [[START]], [[START]]
80 %start.add.1 = add nuw i8 %start, %start
81 %f = icmp ult i8 %start.add.1, %start.mul.2
92 ; CHECK-NEXT: [[START_ADD_1:%.*]] = add nuw i8 [[START]], [[START]]
93 ; CHECK-NEXT: [[START_ADD_2:%.*]] = add nuw i8 [[START_ADD_1]], [[START_ADD_1]]
101 %start.add.1 = add nuw i8 %start, %start
102 %start.add.2 = add nuw i8 %start.add.1, %start.add.1
[all …]
/llvm-project/llvm/test/Analysis/CostModel/AArch64/
H A Dvec3-ops.ll7 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %add = add <3 x i32> %l, %b
8 …NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp = icmp uge <3 x i32> %add, %a
9 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sub = sub <3 x i32> %add,…
10 …an estimated cost of 1 for instruction: %sel = select <3 x i1> %cmp, <3 x i32> %add, <3 x i32> %sub
15 %add = add <3 x i32> %l, %b
16 %cmp = icmp uge <3 x i32> %add, %a
17 %sub = sub <3 x i32> %add, %a
18 %sel = select <3 x i1> %cmp, <3 x i32> %add, <3 x i32> %sub
26 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %add = add <3 x i32> %l, %b
27 …NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cmp = icmp uge <3 x i32> %add, %a
[all …]

12345678910>>...522