adc\-use\-res (full) in projects: freebsd-src

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Searched +full:adc +full:- +full:use +full:- +full:res (Results 1 – 25 of 34) sorted by relevance

/freebsd-src/sys/contrib/device-tree/Bindings/iio/adc/
H A D	at91_adc.txt	1 * AT91's Analog to Digital Converter (ADC) 4 - compatible: Should be "atmel,<chip>-adc" 6 - reg: Should contain ADC registers location and length 7 - interrupts: Should contain the IRQ line for the ADC 8 - clock-names: tuple listing input clock names. 10 - clocks: phandles to input clocks. 11 - atmel,adc-channels-used: Bitmask of the channels muxed and enabled for this 13 - atmel,adc-startup-time: Startup Time of the ADC in microseconds as 15 - atmel,adc-vref: Reference voltage in millivolts for the conversions 16 - atmel,adc-res: List of resolutions in bits supported by the ADC. List size [all …]
H A D	atmel,sama9260-adc.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/iio/adc/atmel,sama9260-adc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: AT91 sama9260 and similar Analog to Digital Converter (ADC) 10 - Alexandre Belloni <alexandre.belloni@bootlin.com> 15 - atmel,at91sam9260-adc 16 - atmel,at91sam9rl-adc 17 - atmel,at91sam9g45-adc 18 - atmel,at91sam9x5-adc [all …]`
/freebsd-src/sys/arm/freescale/vybrid/
H A D	vf_adc.c	1 /- 5 Redistribution and use in source and binary forms, with or without 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * Vybrid Family 12-bit Analog to Digital Converter (ADC) 73 #define CFG_ADLPC (1 << 7) /* Low-Power Configuration / 79 #define CFG_MODE_12 0x2 / 12-bit mode / 110 struct resource res[2]; member 121 { -1, 0 } 131 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-adc")) in adc_probe() [all …]
/freebsd-src/sys/arm/allwinner/
H A D	a10_codec.c	`1 /- 2 Copyright (c) 2014-2016 Jared D. McNeill <jmcneill@invisible.ca> 5 * Redistribution and use in source and binary forms, with or without 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 /* toggle DAC/ADC mute / 84 #define AC_DAC_DPC(_sc) ((_sc)->cfg->DPC) 86 #define AC_DAC_FIFOC(_sc) ((_sc)->cfg->DAC_FIFO 161 struct resource res[2]; global() member [all...]`
H A D	a33_codec.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 7 * Redistribution and use in source and binary forms, with or without 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 133 { "allwinner,sun8i-a33-codec", 1}, 140 { -1, 0 } 145 struct resource *res[2]; member 152 #define CODEC_LOCK(sc) mtx_lock(&(sc)->mtx) 153 #define CODEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) [all …]`
H A D	aw_thermal.c	1 /- 4 Redistribution and use in source and binary forms, with or without 19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 175 return ((A83T_TEMP_BASE - (val * A83T_TEMP_MUL)) / A83T_TEMP_DIV); in a83t_to_temp() 207 return ((A64_TEMP_BASE - (val * A64_TEMP_MUL)) / A64_TEMP_DIV); in a64_to_temp() 239 return (H3_TEMP_BASE - ((val * H3_TEMP_MUL) / H3_TEMP_DIV)); in h3_to_temp() 245 return ((H3_TEMP_MINUS - (val * H3_TEMP_DIV)) / H3_TEMP_MUL); in h3_to_reg() 275 tmp = H5_TEMP_BASE - (val * H5_TEMP_MUL); in h5_to_temp() 281 tmp = H5_TEMP_BASE_CPU - (val * H5_TEMP_MUL_CPU); in h5_to_temp() [all …]
H A D	axp209.c	1 /- 2 Copyright (c) 2015-2016 Emmanuel Vadot <manu@freebsd.org> 5 * Redistribution and use in source and binary forms, with or without 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * X-Power AXP209/AXP211 PMU for Allwinner SoCs 525 .value_convert = -(AXP209_TEMPMON_MIN - AXP209_0C_TO_K), 589 .value_convert = -(AXP221_TEMPMON_MIN - AXP209_0C_TO_K), 600 struct resource * res[1]; member 622 { "x-powers,axp209", AXP209 }, [all …]
/freebsd-src/sys/dev/sound/pci/
H A D	csapcm.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 9 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 11 * Redistribution and use in source and binary forms, with or without 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 csa_res res; /* resourc member [all...]`
H A D	csa.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 9 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 11 * Redistribution and use in source and binary forms, with or without 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 csa_res res; /* resource member 401 struct resource *res; csa_alloc_resource() local [all...]`
/freebsd-src/sys/arm/allwinner/a64/
H A D	sun50i_a64_acodec.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 7 * Redistribution and use in source and binary forms, with or without 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 120 { "allwinner,sun50i-a64-codec-analog", 1}, 126 struct resource *res; member 131 #define A64CODEC_LOCK(sc) mtx_lock(&(sc)->mtx) 132 #define A64CODEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 133 #define A64CODEC_READ(sc, reg) bus_read_4((sc)->res, (reg)) [all …]
/freebsd-src/crypto/openssl/crypto/bn/asm/
H A D	rsaz-avx512.pl	1 # Copyright 2020-2022 The OpenSSL Project Authors. All Rights Reserved. 4 # Licensed under the Apache License 2.0 (the "License"). You may not use 17 # Implementation utilizes 256-bit (ymm) registers to avoid frequency scaling issues. 19 # IceLake-Client @ 1.3GHz 20 # \|---------+----------------------+--------------+-------------\| 21 # \| \| OpenSSL 3.0.0-alpha9 \| this \| Unit \| 22 # \|---------+----------------------+--------------+-------------\| 25 # \|---------+----------------------+--------------+-------------\| 37 ( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or 38 ( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or [all …]
/freebsd-src/crypto/openssl/crypto/ec/asm/
H A D	ecp_nistz256-x86_64.pl	`2 # Copyright 2014-2020 The OpenSSL Project Authors. All Rights Reserved. 6 # Licensed under the Apache License 2.0 (the "License"). You may not use 22 # this/original with/without -DECP_NISTZ256_ASM(*) 23 # Opteron +15-49% +150-195% 24 # Bulldozer +18-45% +175-240% 25 # P4 +24-46% +100-150% 26 # Westmere +18-34% +87-160% 27 # Sandy Bridge +14-35% +120-185% 28 # Ivy Bridge +11-35% +125-180% 29 # Haswell +10-37% +160-200% [all …]`
H A D	ecp_nistz256-armv8.pl	`2 # Copyright 2015-2020 The OpenSSL Project Authors. All Rights Reserved. 4 # Licensed under the Apache License 2.0 (the "License"). You may not use 24 # with/without -DECP_NISTZ256_ASM 25 # Apple A7 +190-360% 26 # Cortex-A53 +190-400% 27 # Cortex-A57 +190-350% 28 # Denver +230-400% 31 # on benchmark. Lower coefficients are for ECDSA sign, server-side 40 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or 41 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or [all …]`
/freebsd-src/sys/dev/adlink/
H A D	adlink.c	1 /- 2 SPDX-License-Identifier: BSD-3-Clause 4 * Copyright (c) 2003-2004 Poul-Henning Kamp 7 * Redistribution and use in source and binary forms, with or without 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * This is a device driver or the Adlink 9812 and 9810 ADC cards, mainly 33 * in the VLF band. See http://phk.freebsd.dk/loran-c 79 # define STATE_RESET -1 105 struct resource *res[3]; member [all …]
/freebsd-src/sys/dev/sound/pci/hda/
H A D	hdaa.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 6 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 9 * Redistribution and use in source and binary forms, with or without 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 #define hdaa_lock(devinfo) snd_mtxlock((devinfo)->loc 536 uint32_t res; hdaa_presence_handler() local 685 uint32_t res; hdaa_eld_handler() local 943 const char res = NULL; hdaa_local_patch_pin() local 1325 const char res = NULL; hdaa_local_patch() local 1383 uint32_t res; hdaa_widget_connection_parse() local 2687 uint32_t res = 0; hdaa_audio_ctl_recsel_comm() local 2925 uint32_t res; hdaa_audio_parse() local 3557 nid_t min, res; hdaa_audio_trace_as_out() local 3836 nid_t min, res; hdaa_audio_trace_as_in_mch() local 3895 nid_t res = 0; hdaa_audio_trace_to_out() local 4720 int type = -1, use, used = 0; hdaa_audio_assign_names() local 4865 int j, res; hdaa_audio_build_tree() local 6050 uint32_t res, pincap, delay; hdaa_pindump() local 6595 uint32_t res; hdaa_attach() local [all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A D	X86ScheduleZnver2.td	1 //=- X86ScheduleZnver2.td - X86 Znver2 Scheduling -------------- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 33 // Zen can issue micro-ops to 10 different units in one cycle. 67 // Micro-ops to be issued to multiple units are tackled this way. 70 // Zn2ALU03 - 0,3 grouping 90 // 4 Cycles load-to use Latency is captured 93 // 7 Cycles vector load-to use Latency is captured 101 // speculative version of the 64-bit integer registers. [all …]
H A D	X86ScheduleZnver1.td	1 //=- X86ScheduleZnver1.td - X86 Znver1 Scheduling -------------- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 33 // Zen can issue micro-ops to 10 different units in one cycle. 66 // Micro-ops to be issued to multiple units are tackled this way. 69 // ZnALU03 - 0,3 grouping 89 // 4 Cycles integer load-to use Latency is captured 92 // 8 Cycles vector load-to use Latency is captured 100 // speculative version of the 64-bit integer registers. [all …]
H A D	X86ISelLowering.cpp	1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation ------- 3880 SDValue Res = ZeroNewElements ? getZeroVector(VT, Subtarget, DAG, dl) widenSubVector() local 4178 SDValue Res = DAG.getNode(Opcode, DL, DstVT, SrcOps); getAVX512Node() local 7485 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(), IVT, NewOps); LowerBUILD_VECTORvXbf16() local 8279 SDValue Res = DAG.getNode(Opcode, DL, VT, LHS, RHS); lowerBuildVectorToBitOp() local 8493 SDValue Res = DAG.getSelectCC( createVariablePermute() local 8510 SDValue Res = createVariablePermute(WidenSrcVT, SrcVec, IndicesVec, DL, createVariablePermute() local 8529 SDValue Res = DAG.getSelectCC( createVariablePermute() local 8568 SDValue Res = Opcode == X86ISD::VPERMV createVariablePermute() local 10318 SDValue Res; lowerShuffleWithPACK() local 11446 SDValue Res = Mask[ZeroLo] < (int)NumElts ? V1 : V2; lowerShuffleAsByteShiftMask() local 17174 SDValue Res = widenMaskVector(V1, false, Subtarget, DAG, DL); lower1BitShuffleAsKSHIFTR() local 17273 SDValue Res = widenMaskVector(V, false, Subtarget, DAG, DL); lower1BitShuffle() local 17961 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG)) LowerEXTRACT_VECTOR_ELT() local 17974 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, LowerEXTRACT_VECTOR_ELT() local 17986 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, LowerEXTRACT_VECTOR_ELT() local 18073 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, IVT, LowerINSERT_VECTOR_ELT() local 18780 SDValue res; LowerGlobalTLSAddress() local 19044 SDValue Res, Chain; lowerINT_TO_FP_vXi64() local 19434 SDValue Res = DAG.getNode(Op->getOpcode(), DL, {MVT::v4f64, MVT::Other}, lowerUINT_TO_FP_v2i32() local 19496 SDValue Res, Chain; lowerUINT_TO_FP_vXi32() local 19951 SDValue Res = DAG.getLoad(Op.getValueType(), SDLoc(Op), FIST, StackSlot, MPI); FP_TO_INTHelper() local 20033 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v16i16, Lo, Hi); SplitAndExtendv16i1() local 20159 SDValue Res = DAG.getNode(Opcode, DL, OutVT, LHS, RHS); truncateVectorWithPACK() local 20172 if (SDValue Res = truncateVectorWithPACK() local 20185 SDValue Res = DAG.getNode(Opcode, DL, OutVT, Lo, Hi); truncateVectorWithPACK() local 20194 SDValue Res = DAG.getNode(Opcode, DL, OutVT, Lo, Hi); truncateVectorWithPACK() local 20218 SDValue Res = truncateVectorWithPACK() local 20226 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, PackedVT, Lo, Hi); truncateVectorWithPACK() local 20361 if (SDValue Res = LowerTruncateVecPackWithSignBits(DstHalfVT, Lo, DL, LowerTruncateVecPackWithSignBits() local 20404 if (SDValue Res = LowerTruncateVecPack(DstHalfVT, Lo, DL, Subtarget, DAG)) LowerTruncateVecPack() local 20680 SDValue Res; LowerFP_TO_INT() local 21300 SDValue Res; LowerFP_EXTEND() local 21312 SDValue Res; LowerFP_EXTEND() local 21354 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8f16, In, LowerFP_EXTEND() local 21366 SDValue Res = LowerFP_EXTEND() local 21411 SDValue Res; LowerFP_ROUND() local 21437 SDValue Res; LowerFP_ROUND() local 21473 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, LowerFP16_TO_FP() local 21502 SDValue Res, Chain; LowerFP_TO_FP16() local 21534 SDValue Res; LowerFP_TO_BF16() local 21544 SDValue Res = LowerFP_TO_BF16() local 21796 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, N0); LowerFGETSIGN() local 23694 SDValue Res = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, X86CC, EFLAGS); LowerSETCC() local 23715 SDValue Res = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, X86CC, EFLAGS); LowerSETCC() local 24095 SDValue Res = LowerSELECT() local 25875 SDValue Res; LowerINTRINSIC_WO_CHAIN() local 26313 SDValue Res = getAVX2GatherNode() local 26351 SDValue Res = getGatherNode() local 26382 SDValue Res = getScatterNode() local 26406 SDNode Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops); getPrefetchNode() local 26790 SDValue Res = LowerINTRINSIC_W_CHAIN() local 26810 SDValue Res = LowerINTRINSIC_W_CHAIN() local 27771 SDValue Res = DAG.getNode(ISD::ADD, DL, CurrVT, Lo, Hi); LowerVectorCTLZInRegLUT() local 28529 SDValue Res = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, ShufMask); LowerMULH() local 28607 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi); LowerMULO() local 29029 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); LowerShiftByScalarImmediate() local 29080 SDValue Res = getTargetVShiftNode(LogicalX86Op, dl, ExtVT, LowerShiftByScalarVariable() local 29295 SDValue Res = DAG.getNode(ISD::MULHU, dl, VT, R, Scale); LowerShift() local 29318 SDValue Res = DAG.getNode(ISD::MULHS, dl, VT, R, Scale); LowerShift() local 29759 SDValue Res = DAG.getNode(ISD::OR, DL, WideVT, Op0, Op1); LowerFunnelShift() local 29800 SDValue Res = DAG.getNode(ISD::SHL, DL, MVT::i32, Op0, HiShift); LowerFunnelShift() local 30688 SDNode Res = DAG.getMachineNode(X86::OR32mi8Locked, DL, MVT::i32, emitLockedStackOp() local 30703 SDNode Res = DAG.getMachineNode(X86::OR32mi8Locked, DL, MVT::i32, emitLockedStackOp() local 31037 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, In); LowerBITREVERSE_XOP() local 31067 SDValue Res = DAG.getBitcast(MVT::v16i8, In); LowerBITREVERSE_XOP() local 32029 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi); ReplaceNodeResults() local 32045 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi); ReplaceNodeResults() local 32082 SDValue Res = DAG.getNode(ISD::MUL, dl, MulVT, Op0, Op1); ReplaceNodeResults() local 32100 SDValue Res = DAG.getNode(ISD::MUL, dl, MVT::v2i64, Op0, Op1); ReplaceNodeResults() local 32153 SDValue Res = DAG.getNode(N->getOpcode(), dl, WideVT, InVec0, InVec1); ReplaceNodeResults() local 32191 SDValue Res = DAG.getNode(N->getOpcode(), dl, ResVT, N0, N1); ReplaceNodeResults() local 32222 if (SDValue Res = truncateVectorWithPACK(PackOpcode, VT, Src, ReplaceNodeResults() local 32273 SDValue Res = DAG.getVectorShuffle(MVT::v16i8, dl, Lo, Hi, ReplaceNodeResults() local 32330 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi); ReplaceNodeResults() local 32368 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi); ReplaceNodeResults() local 32385 SDValue Res; ReplaceNodeResults() local 32457 SDValue Res; ReplaceNodeResults() local 32505 SDValue Res = ReplaceNodeResults() local 32530 SDValue Res; ReplaceNodeResults() local 32550 SDValue Res = DAG.getNode(N->getOpcode(), dl, {MVT::v4i32, MVT::Other}, ReplaceNodeResults() local 32583 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecInVT, ReplaceNodeResults() local 32644 SDValue Res = DAG.getNode(Opc, dl, {MVT::v8f16, MVT::Other}, ReplaceNodeResults() local 32661 SDValue Res = DAG.getNode(Opc, dl, {MVT::v4f32, MVT::Other}, ReplaceNodeResults() local 32723 SDValue Res = DAG.getNode(N->getOpcode(), dl, {MVT::v4f32, MVT::Other}, ReplaceNodeResults() local 32740 SDValue Res = DAG.getNode(X86ISD::STRICT_VFPROUND, dl, ReplaceNodeResults() local 32925 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Ld, ReplaceNodeResults() local 32934 SDValue Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2f32, Ld, ReplaceNodeResults() local 33006 SDValue Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); ReplaceNodeResults() local 33017 SDValue Res = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, ReplaceNodeResults() local 33051 SDValue Res = DAG.getMemIntrinsicNode( ReplaceNodeResults() local 33073 SDValue Res = DAG.getLoad(LdVT, dl, Ld->getChain(), Ld->getBasePtr(), ReplaceNodeResults() local 33088 SDValue Res = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, ReplaceNodeResults() local 36682 std::optional<bool> Res = Opc == X86ISD::PCMPEQ computeKnownBitsForTargetNode() local 37785 SDValue Res; combineX86ShuffleChain() local 38714 SDValue Res = DAG.getNode(Opcode0, DL, VT0, LHS, RHS); canonicalizeShuffleMaskWithHorizOp() local 38814 SDValue Res = DAG.getNode(Opcode0, DL, HalfVT, V0, V1); canonicalizeShuffleMaskWithHorizOp() local 39249 if (SDValue Res = combineX86ShufflesRecursively( combineX86ShufflesRecursively() local 39769 SDValue Res; canonicalizeShuffleWithOp() local 39810 SDValue Res = canonicalizeLaneShuffleWithRepeatedOps() local 39830 SDValue Res = DAG.getNode(X86ISD::VPERM2X128, DL, SrcVT0, LHS, RHS, canonicalizeLaneShuffleWithRepeatedOps() local 39887 if (SDValue Res = combineX86ShufflesRecursively( combineTargetShuffle() local 40254 SDValue Res = DAG.getNode(X86ISD::VPERMI, DL, SrcVT, Src, N1); combineTargetShuffle() local 40303 if (SDValue Res = canonicalizeLaneShuffleWithRepeatedOps(N, DAG, DL)) combineTargetShuffle() local 40352 SDValue Res = DAG.getNode(Opcode, DL, VT, combineTargetShuffle() local 40882 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineShuffle() local 41058 __anon973982078c02(SDNode Use) SimplifyDemandedVectorEltsForTargetNode() argument 43039 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0, combineBitcast() local 44262 __anon973982079902(SDNode Use) combineExtractVectorElt() argument 44284 SDValue Res = DAG.getNode(ISD::AND, dl, BCVT, BC, Mask); combineExtractVectorElt() local 44300 __anon973982079a02(SDNode Use) combineExtractVectorElt() argument 44787 SDValue Res = DAG.getNode(ISD::SUB, DL, MaskVT, SubOp1, SubOp2); combineLogicBlendIntoConditionalNegate() local 45117 SDValue Res = DAG.getSelect(DL, SrcVT, Cond, LHS, RHS); combineSelect() local 45798 if (SDValue Res = combinePTESTCC() local 47183 SDValue Res = DAG.getNode(Opcode, DL, VT, Lo, Hi); combineHorizOpWithShuffle() local 47241 SDValue Res = DAG.getNode(Opcode, DL, VT, LHS, RHS); combineHorizOpWithShuffle() local 47277 SDValue Res = DAG.getNode(Opcode, DL, VT, DAG.getBitcast(SrcVT, Op00), combineHorizOpWithShuffle() local 47434 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineVectorPack() local 47464 SDValue Res = DAG.getNode(LHS.getOpcode(), DL, LHS.getValueType(), combineVectorHADDSUB() local 47589 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineVectorShiftImm() local 47699 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineVectorInsert() local 48711 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineAnd() local 48858 SDValue Res = getAVX512Node(X86ISD::VPTERNLOG, DL, OpVT, {A, B, C, Imm}, canonicalizeBitSelect() local 48938 if (SDValue Res = combineLogicBlendIntoConditionalNegate(VT, Mask, X, Y, DL, combineLogicBlendIntoPBLENDV() local 49469 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineOr() local 49792 SDValue Res = DAG.getNode(TruncOpc, DL, TruncVT, SatVal); combineTruncateWithSat() local 49887 SDValue Res = SplitOpsAndApply(DAG, Subtarget, DL, Pow2VT, Ops, AVGBuilder); detectAVGPattern() local 50980 SDValue Res; combineFMulcFCMulc() local 51226 SDValue Res = DAG.getNode(ISD::MULHU, DL, BCVT, DAG.getBitcast(BCVT, LHS), combinePMULH() local 52248 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineAndnp() local 52571 SDValue Res = DAG.getNode(X86ISD::CMOV, DL, ExtendVT, CMovOp0, CMovOp1, combineToExtendCMOV() local 52619 SDValue Res = DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); combineExtSetcc() local 52690 __anon97398207cf02(SDNode Use) getInvertedVectorForFMA() argument 53230 SDValue Res = DAG.getNode(ISD::XOR, DL, SrcVT, ShiftLHS, ShiftRHS); combineMOVMSK() local 53514 SDValue Res = DAG.getBitcast(VT, NewAnd); combineVectorCompareAndMaskUnaryOp() local 53627 if (SDValue Res = combineVectorCompareAndMaskUnaryOp(N, DAG)) combineSIntToFP() local 53958 SDValue Res = DAG.getNode(GenericOpc, DL, VT, LHS, RHS); combineX86AddSub() local 54397 __anon97398207d702(SDNode Use) pushAddIntoCmovOfConsts() argument 54595 SDValue ADC = DAG.getNode(X86ISD::ADC, SDLoc(Op1), Op1->getVTList(), Op0, combineSub() local 54822 SDValue Res = DAG.getBitcast(FloatVT, ConcatSubOperand(VT, Ops, 0)); combineConcatVectorOps() local 54921 SDValue Res = DAG.getNode(X86ISD::SHUF128, DL, ShuffleVT, combineConcatVectorOps() local 54967 SDValue Res = DAG.getBitcast(MVT::v8i32, ConcatSubOperand(VT, Ops, 0)); combineConcatVectorOps() local 55215 SDValue Res = widenSubVector(Op0, false, Subtarget, DAG, DL, 512); combineConcatVectorOps() local 55375 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineINSERT_SUBVECTOR() local 55880 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineEXTEND_VECTOR_INREG() local 55918 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, combineFP16_TO_FP() local 57413 std::pair<Register, const TargetRegisterClass*> Res; getRegForInlineAsmConstraint() local [all...]
H A D	X86ISelDAGToDAG.cpp	1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===--- 933 SDValue Res = CurDAG->getNode(ISD::AND, SDLoc(N), N->getValueType(0), PreprocessISelDAG() local 979 SDValue Res = PreprocessISelDAG() local 998 SDValue Res = PreprocessISelDAG() local 1026 SDValue Res = PreprocessISelDAG() local 1076 SDValue Res = CurDAG->getBitcast(VT, Extract); PreprocessISelDAG() local 1134 SDValue Res; PreprocessISelDAG() local 1164 SDValue Res = CurDAG->getNode(NewOpc, SDLoc(N), N->getValueType(0), PreprocessISelDAG() local 1190 SDValue Res = CurDAG->getNode(NewOpc, SDLoc(N), N->getValueType(0), PreprocessISelDAG() local 1230 SDValue Res; PreprocessISelDAG() local 1266 SDValue Res; PreprocessISelDAG() local 2361 SDValue Res; matchIndexRecursively() local 2722 SDValue Res = ShlSrc; matchAddressRecursively() local 5048 MachineSDNode Res = CurDAG->getMachineNode( Select() local 6433 MachineSDNode Res = CurDAG->getMachineNode( Select() local [all...]
H A D	X86SchedAlderlakeP.td	`1 //===- X86SchedAlderlakeP.td - X86 Alderlake-P Scheduling ----- tablegen -- [all...]`
H A D	X86ISelLowering.h	`1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ------- 397 ADC, global() enumerator [all...]`
/freebsd-src/sys/contrib/x86emu/
H A D	x86emu.c	8 * Copyright (C) 1996-1999 SciTech Software, Inc. 9 * Copyright (C) David Mosberger-Tang 15 * Permission to use, copy, modify, distribute, and sell this software and 29 * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 30 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 179 if (emu->_x86emu_intrTab[intno]) { in x86emu_intr_dispatch() 180 (emu->_x86emu_intrTab[intno]) (emu, intno); in x86emu_intr_dispatch() 182 push_word(emu, (uint16_t) emu->x86.R_FLG); in x86emu_intr_dispatch() 185 push_word(emu, emu->x86.R_CS); in x86emu_intr_dispatch() 186 emu->x86.R_CS = fetch_word(emu, 0, intno 4 + 2); in x86emu_intr_dispatch() [all …]
/freebsd-src/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A D	EmulateInstructionARM.cpp	1 //===-- EmulateInstructionARM.cpp -------- 1906 AddWithCarryResult res = AddWithCarry(sp, imm32, 0); EmulateADDSPImm() local 2435 AddWithCarryResult res = AddWithCarry(sp, ~imm32, 1); EmulateSUBSPImm() local 3107 AddWithCarryResult res = AddWithCarry(Rn, imm32, 0); EmulateADDImmThumb() local 3172 AddWithCarryResult res = AddWithCarry(val1, imm32, 0); EmulateADDImmARM() local 3266 AddWithCarryResult res = AddWithCarry(val1, shifted, 0); EmulateADDReg() local 3321 AddWithCarryResult res = AddWithCarry(reg_val, imm32, 0); EmulateCMNImm() local 3388 AddWithCarryResult res = AddWithCarry(val1, shifted, 0); EmulateCMNReg() local 3438 AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); EmulateCMPImm() local 3514 AddWithCarryResult res = AddWithCarry(val1, ~shifted, 1); EmulateCMPReg() local 5832 AddWithCarryResult res = AddWithCarry(val1, imm32, APSR_C); EmulateADCImm() local 5919 AddWithCarryResult res = AddWithCarry(val1, shifted, APSR_C); EmulateADCReg() local 9194 AddWithCarryResult res = AddWithCarry(~reg_val, imm32, 1); EmulateRSBImm() local 9273 AddWithCarryResult res = AddWithCarry(~val1, shifted, 1); EmulateRSBReg() local 9331 AddWithCarryResult res = AddWithCarry(~reg_val, imm32, APSR_C); EmulateRSCImm() local 9401 AddWithCarryResult res = AddWithCarry(~val1, shifted, APSR_C); EmulateRSCReg() local 9468 AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, APSR_C); EmulateSBCImm() local 9555 AddWithCarryResult res = AddWithCarry(val1, ~shifted, APSR_C); EmulateSBCReg() local 9644 AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); EmulateSUBImmThumb() local 9711 AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); EmulateSUBImmARM() local 10068 AddWithCarryResult res = AddWithCarry(sp_val, ~shifted, 1); EmulateSUBSPReg() local 10154 AddWithCarryResult res = AddWithCarry(Rn, shifted, 0); EmulateADDRegShift() local 10286 AddWithCarryResult res = AddWithCarry(Rn, ~shifted, 1); EmulateSUBReg() local 14149 AddWithCarryResult res = {result, carry_out, overflow}; AddWithCarry() local [all...]
/freebsd-src/sys/cam/scsi/
H A D	scsi_all.c	`1 /- 4 SPDX-License-Identifier: BSD-2-Clause 10 * Redistribution and use in source and binary forms, with or without 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 78 #define ERESTART -1 /* restart syscall / 79 #define EJUSTRETURN - 4727 struct scsi_sense_ata_ret_desc res; scsi_sense_ata_sbuf() local [all...]`
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A D	ARMISelLowering.cpp	1 //===- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------- 3463 SDValue Res; LowerConstantPool() local 5805 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); LowerBR_CC() local 6062 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, LowerFCOPYSIGN() local 6569 SDValue Res = DAG.getBitcast(VT8Bit, N->getOperand(0)); LowerCTPOP() local 8924 SDValue Res = DAG.getNode(ShuffleOpc, dl, DAG.getVTList(SubVT, SubVT), LowerVECTOR_SHUFFLE() local 10311 SDValue Res; LowerVecReduce() local 10397 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, LowerVecReduceMinMax() local 10711 SDValue Res; ReplaceNodeResults() local 14006 SDValue Res = DAG.getNode(ISD::SHL, dl, MVT::i32, BinOp, SHL.getOperand(1)); PerformSHLSimplify() local 14240 SDValue Res; PerformMULCombine() local 14504 SDValue Res = DAG.getNode(Opcode, dl, MVT::i32, OpS32, OpS16); PerformORCombineToSMULWBT() local 14546 SDValue Res; PerformORCombineToBFI() local 14782 if (SDValue Res = PerformORCombineToBFI(N, DCI, Subtarget)) PerformORCombine() local 15314 SDNode Use = N->use_begin(); PerformARMBUILD_VECTORCombine() local 18279 SDValue Res; PerformHWLoopCombine() local 18397 SDValue Res; PerformCMOVCombine() local [all...]