adc\-res\-names (full) in projects: freebsd-src

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Searched +full:adc +full:- +full:res +full:- +full:names (Results 1 – 9 of 9) sorted by relevance

/freebsd-src/sys/contrib/device-tree/Bindings/iio/adc/
H A D	at91_adc.txt	1 * AT91's Analog to Digital Converter (ADC) 4 - compatible: Should be "atmel,<chip>-adc" 6 - reg: Should contain ADC registers location and length 7 - interrupts: Should contain the IRQ line for the ADC 8 - clock-names: tuple listing input clock names. 10 - clocks: phandles to input clocks. 11 - atmel,adc-channels-used: Bitmask of the channels muxed and enabled for this 13 - atmel,adc-startup-time: Startup Time of the ADC in microseconds as 15 - atmel,adc-vref: Reference voltage in millivolts for the conversions 16 - atmel,adc-res: List of resolutions in bits supported by the ADC. List size [all …]
H A D	atmel,sama9260-adc.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/iio/adc/atmel,sama9260-adc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: AT91 sama9260 and similar Analog to Digital Converter (ADC) 10 - Alexandre Belloni <alexandre.belloni@bootlin.com> 15 - atmel,at91sam9260-adc 16 - atmel,at91sam9rl-adc 17 - atmel,at91sam9g45-adc 18 - atmel,at91sam9x5-adc [all …]`
/freebsd-src/sys/dev/adlink/
H A D	adlink.c	`1 /- 2 SPDX-License-Identifier: BSD-3-Clause 4 * Copyright (c) 2003-2004 Poul-Henning Kamp 15 * 3. The names of the authors may not be used to endorse or promote 31 * This is a device driver or the Adlink 9812 and 9810 ADC cards, mainly 33 * in the VLF band. See http://phk.freebsd.dk/loran-c 79 # define STATE_RESET -1 105 struct resource *res[3]; member 136 u = bus_read_4(sc->res[0], 0x38); in adlink_intr() 139 bus_write_4(sc->res[0], 0x38, u \| 0x003f4000); in adlink_intr() [all …]`
/freebsd-src/sys/dev/sound/pci/hda/
H A D	hdaa.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 6 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 50 #define hdaa_lock(devinfo) snd_mtxlock((devinfo)->lock) 51 #define hdaa_unlock(devinfo) snd_mtxunlock((devinfo)->lock) 52 #define hdaa_lockassert(devinfo) snd_mtxassert((devinfo)->lock) 79 "Green", "Red", "Orange", "Yellow", "Purple", "Pink", "Res 536 uint32_t res; hdaa_presence_handler() local 685 uint32_t res; hdaa_eld_handler() local 943 const char res = NULL; hdaa_local_patch_pin() local 1325 const char res = NULL; hdaa_local_patch() local 1383 uint32_t res; hdaa_widget_connection_parse() local 2687 uint32_t res = 0; hdaa_audio_ctl_recsel_comm() local 2925 uint32_t res; hdaa_audio_parse() local 3557 nid_t min, res; hdaa_audio_trace_as_out() local 3836 nid_t min, res; hdaa_audio_trace_as_in_mch() local 3895 nid_t res = 0; hdaa_audio_trace_to_out() local 4865 int j, res; hdaa_audio_build_tree() local 6050 uint32_t res, pincap, delay; hdaa_pindump() local 6595 uint32_t res; hdaa_attach() local [all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A D	X86ISelLowering.cpp	1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation ------- 3880 SDValue Res = ZeroNewElements ? getZeroVector(VT, Subtarget, DAG, dl) widenSubVector() local 4178 SDValue Res = DAG.getNode(Opcode, DL, DstVT, SrcOps); getAVX512Node() local 7485 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(), IVT, NewOps); LowerBUILD_VECTORvXbf16() local 8279 SDValue Res = DAG.getNode(Opcode, DL, VT, LHS, RHS); lowerBuildVectorToBitOp() local 8493 SDValue Res = DAG.getSelectCC( createVariablePermute() local 8510 SDValue Res = createVariablePermute(WidenSrcVT, SrcVec, IndicesVec, DL, createVariablePermute() local 8529 SDValue Res = DAG.getSelectCC( createVariablePermute() local 8568 SDValue Res = Opcode == X86ISD::VPERMV createVariablePermute() local 10318 SDValue Res; lowerShuffleWithPACK() local 11446 SDValue Res = Mask[ZeroLo] < (int)NumElts ? V1 : V2; lowerShuffleAsByteShiftMask() local 17174 SDValue Res = widenMaskVector(V1, false, Subtarget, DAG, DL); lower1BitShuffleAsKSHIFTR() local 17273 SDValue Res = widenMaskVector(V, false, Subtarget, DAG, DL); lower1BitShuffle() local 17961 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG)) LowerEXTRACT_VECTOR_ELT() local 17974 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, LowerEXTRACT_VECTOR_ELT() local 17986 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, LowerEXTRACT_VECTOR_ELT() local 18073 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, IVT, LowerINSERT_VECTOR_ELT() local 18780 SDValue res; LowerGlobalTLSAddress() local 19044 SDValue Res, Chain; lowerINT_TO_FP_vXi64() local 19434 SDValue Res = DAG.getNode(Op->getOpcode(), DL, {MVT::v4f64, MVT::Other}, lowerUINT_TO_FP_v2i32() local 19496 SDValue Res, Chain; lowerUINT_TO_FP_vXi32() local 19951 SDValue Res = DAG.getLoad(Op.getValueType(), SDLoc(Op), FIST, StackSlot, MPI); FP_TO_INTHelper() local 20033 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v16i16, Lo, Hi); SplitAndExtendv16i1() local 20159 SDValue Res = DAG.getNode(Opcode, DL, OutVT, LHS, RHS); truncateVectorWithPACK() local 20172 if (SDValue Res = truncateVectorWithPACK() local 20185 SDValue Res = DAG.getNode(Opcode, DL, OutVT, Lo, Hi); truncateVectorWithPACK() local 20194 SDValue Res = DAG.getNode(Opcode, DL, OutVT, Lo, Hi); truncateVectorWithPACK() local 20218 SDValue Res = truncateVectorWithPACK() local 20226 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, PackedVT, Lo, Hi); truncateVectorWithPACK() local 20361 if (SDValue Res = LowerTruncateVecPackWithSignBits(DstHalfVT, Lo, DL, LowerTruncateVecPackWithSignBits() local 20404 if (SDValue Res = LowerTruncateVecPack(DstHalfVT, Lo, DL, Subtarget, DAG)) LowerTruncateVecPack() local 20680 SDValue Res; LowerFP_TO_INT() local 21300 SDValue Res; LowerFP_EXTEND() local 21312 SDValue Res; LowerFP_EXTEND() local 21354 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8f16, In, LowerFP_EXTEND() local 21366 SDValue Res = LowerFP_EXTEND() local 21411 SDValue Res; LowerFP_ROUND() local 21437 SDValue Res; LowerFP_ROUND() local 21473 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, LowerFP16_TO_FP() local 21502 SDValue Res, Chain; LowerFP_TO_FP16() local 21534 SDValue Res; LowerFP_TO_BF16() local 21544 SDValue Res = LowerFP_TO_BF16() local 21796 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, N0); LowerFGETSIGN() local 23694 SDValue Res = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, X86CC, EFLAGS); LowerSETCC() local 23715 SDValue Res = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, X86CC, EFLAGS); LowerSETCC() local 24095 SDValue Res = LowerSELECT() local 25875 SDValue Res; LowerINTRINSIC_WO_CHAIN() local 26313 SDValue Res = getAVX2GatherNode() local 26351 SDValue Res = getGatherNode() local 26382 SDValue Res = getScatterNode() local 26406 SDNode Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops); getPrefetchNode() local 26790 SDValue Res = LowerINTRINSIC_W_CHAIN() local 26810 SDValue Res = LowerINTRINSIC_W_CHAIN() local 27771 SDValue Res = DAG.getNode(ISD::ADD, DL, CurrVT, Lo, Hi); LowerVectorCTLZInRegLUT() local 28529 SDValue Res = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, ShufMask); LowerMULH() local 28607 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi); LowerMULO() local 29029 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); LowerShiftByScalarImmediate() local 29080 SDValue Res = getTargetVShiftNode(LogicalX86Op, dl, ExtVT, LowerShiftByScalarVariable() local 29295 SDValue Res = DAG.getNode(ISD::MULHU, dl, VT, R, Scale); LowerShift() local 29318 SDValue Res = DAG.getNode(ISD::MULHS, dl, VT, R, Scale); LowerShift() local 29759 SDValue Res = DAG.getNode(ISD::OR, DL, WideVT, Op0, Op1); LowerFunnelShift() local 29800 SDValue Res = DAG.getNode(ISD::SHL, DL, MVT::i32, Op0, HiShift); LowerFunnelShift() local 30688 SDNode Res = DAG.getMachineNode(X86::OR32mi8Locked, DL, MVT::i32, emitLockedStackOp() local 30703 SDNode Res = DAG.getMachineNode(X86::OR32mi8Locked, DL, MVT::i32, emitLockedStackOp() local 31037 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, In); LowerBITREVERSE_XOP() local 31067 SDValue Res = DAG.getBitcast(MVT::v16i8, In); LowerBITREVERSE_XOP() local 32029 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi); ReplaceNodeResults() local 32045 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi); ReplaceNodeResults() local 32082 SDValue Res = DAG.getNode(ISD::MUL, dl, MulVT, Op0, Op1); ReplaceNodeResults() local 32100 SDValue Res = DAG.getNode(ISD::MUL, dl, MVT::v2i64, Op0, Op1); ReplaceNodeResults() local 32153 SDValue Res = DAG.getNode(N->getOpcode(), dl, WideVT, InVec0, InVec1); ReplaceNodeResults() local 32191 SDValue Res = DAG.getNode(N->getOpcode(), dl, ResVT, N0, N1); ReplaceNodeResults() local 32222 if (SDValue Res = truncateVectorWithPACK(PackOpcode, VT, Src, ReplaceNodeResults() local 32273 SDValue Res = DAG.getVectorShuffle(MVT::v16i8, dl, Lo, Hi, ReplaceNodeResults() local 32330 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi); ReplaceNodeResults() local 32368 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi); ReplaceNodeResults() local 32385 SDValue Res; ReplaceNodeResults() local 32457 SDValue Res; ReplaceNodeResults() local 32505 SDValue Res = ReplaceNodeResults() local 32530 SDValue Res; ReplaceNodeResults() local 32550 SDValue Res = DAG.getNode(N->getOpcode(), dl, {MVT::v4i32, MVT::Other}, ReplaceNodeResults() local 32583 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecInVT, ReplaceNodeResults() local 32644 SDValue Res = DAG.getNode(Opc, dl, {MVT::v8f16, MVT::Other}, ReplaceNodeResults() local 32661 SDValue Res = DAG.getNode(Opc, dl, {MVT::v4f32, MVT::Other}, ReplaceNodeResults() local 32723 SDValue Res = DAG.getNode(N->getOpcode(), dl, {MVT::v4f32, MVT::Other}, ReplaceNodeResults() local 32740 SDValue Res = DAG.getNode(X86ISD::STRICT_VFPROUND, dl, ReplaceNodeResults() local 32925 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Ld, ReplaceNodeResults() local 32934 SDValue Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2f32, Ld, ReplaceNodeResults() local 33006 SDValue Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); ReplaceNodeResults() local 33017 SDValue Res = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, ReplaceNodeResults() local 33051 SDValue Res = DAG.getMemIntrinsicNode( ReplaceNodeResults() local 33073 SDValue Res = DAG.getLoad(LdVT, dl, Ld->getChain(), Ld->getBasePtr(), ReplaceNodeResults() local 33088 SDValue Res = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, ReplaceNodeResults() local 36682 std::optional<bool> Res = Opc == X86ISD::PCMPEQ computeKnownBitsForTargetNode() local 37785 SDValue Res; combineX86ShuffleChain() local 38714 SDValue Res = DAG.getNode(Opcode0, DL, VT0, LHS, RHS); canonicalizeShuffleMaskWithHorizOp() local 38814 SDValue Res = DAG.getNode(Opcode0, DL, HalfVT, V0, V1); canonicalizeShuffleMaskWithHorizOp() local 39249 if (SDValue Res = combineX86ShufflesRecursively( combineX86ShufflesRecursively() local 39769 SDValue Res; canonicalizeShuffleWithOp() local 39810 SDValue Res = canonicalizeLaneShuffleWithRepeatedOps() local 39830 SDValue Res = DAG.getNode(X86ISD::VPERM2X128, DL, SrcVT0, LHS, RHS, canonicalizeLaneShuffleWithRepeatedOps() local 39887 if (SDValue Res = combineX86ShufflesRecursively( combineTargetShuffle() local 40254 SDValue Res = DAG.getNode(X86ISD::VPERMI, DL, SrcVT, Src, N1); combineTargetShuffle() local 40303 if (SDValue Res = canonicalizeLaneShuffleWithRepeatedOps(N, DAG, DL)) combineTargetShuffle() local 40352 SDValue Res = DAG.getNode(Opcode, DL, VT, combineTargetShuffle() local 40882 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineShuffle() local 43039 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0, combineBitcast() local 44284 SDValue Res = DAG.getNode(ISD::AND, dl, BCVT, BC, Mask); combineExtractVectorElt() local 44787 SDValue Res = DAG.getNode(ISD::SUB, DL, MaskVT, SubOp1, SubOp2); combineLogicBlendIntoConditionalNegate() local 45117 SDValue Res = DAG.getSelect(DL, SrcVT, Cond, LHS, RHS); combineSelect() local 45798 if (SDValue Res = combinePTESTCC() local 47183 SDValue Res = DAG.getNode(Opcode, DL, VT, Lo, Hi); combineHorizOpWithShuffle() local 47241 SDValue Res = DAG.getNode(Opcode, DL, VT, LHS, RHS); combineHorizOpWithShuffle() local 47277 SDValue Res = DAG.getNode(Opcode, DL, VT, DAG.getBitcast(SrcVT, Op00), combineHorizOpWithShuffle() local 47434 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineVectorPack() local 47464 SDValue Res = DAG.getNode(LHS.getOpcode(), DL, LHS.getValueType(), combineVectorHADDSUB() local 47589 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineVectorShiftImm() local 47699 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineVectorInsert() local 48711 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineAnd() local 48858 SDValue Res = getAVX512Node(X86ISD::VPTERNLOG, DL, OpVT, {A, B, C, Imm}, canonicalizeBitSelect() local 48938 if (SDValue Res = combineLogicBlendIntoConditionalNegate(VT, Mask, X, Y, DL, combineLogicBlendIntoPBLENDV() local 49469 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineOr() local 49792 SDValue Res = DAG.getNode(TruncOpc, DL, TruncVT, SatVal); combineTruncateWithSat() local 49887 SDValue Res = SplitOpsAndApply(DAG, Subtarget, DL, Pow2VT, Ops, AVGBuilder); detectAVGPattern() local 50980 SDValue Res; combineFMulcFCMulc() local 51226 SDValue Res = DAG.getNode(ISD::MULHU, DL, BCVT, DAG.getBitcast(BCVT, LHS), combinePMULH() local 52248 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineAndnp() local 52571 SDValue Res = DAG.getNode(X86ISD::CMOV, DL, ExtendVT, CMovOp0, CMovOp1, combineToExtendCMOV() local 52619 SDValue Res = DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); combineExtSetcc() local 53230 SDValue Res = DAG.getNode(ISD::XOR, DL, SrcVT, ShiftLHS, ShiftRHS); combineMOVMSK() local 53514 SDValue Res = DAG.getBitcast(VT, NewAnd); combineVectorCompareAndMaskUnaryOp() local 53627 if (SDValue Res = combineVectorCompareAndMaskUnaryOp(N, DAG)) combineSIntToFP() local 53958 SDValue Res = DAG.getNode(GenericOpc, DL, VT, LHS, RHS); combineX86AddSub() local 54595 SDValue ADC = DAG.getNode(X86ISD::ADC, SDLoc(Op1), Op1->getVTList(), Op0, combineSub() local 54822 SDValue Res = DAG.getBitcast(FloatVT, ConcatSubOperand(VT, Ops, 0)); combineConcatVectorOps() local 54921 SDValue Res = DAG.getNode(X86ISD::SHUF128, DL, ShuffleVT, combineConcatVectorOps() local 54967 SDValue Res = DAG.getBitcast(MVT::v8i32, ConcatSubOperand(VT, Ops, 0)); combineConcatVectorOps() local 55215 SDValue Res = widenSubVector(Op0, false, Subtarget, DAG, DL, 512); combineConcatVectorOps() local 55375 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineINSERT_SUBVECTOR() local 55880 if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) combineEXTEND_VECTOR_INREG() local 55918 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, combineFP16_TO_FP() local 57413 std::pair<Register, const TargetRegisterClass> Res; getRegForInlineAsmConstraint() local [all...]
/freebsd-src/sys/cam/scsi/
H A D	scsi_all.c	`1 /- 4 SPDX-License-Identifier: BSD-2-Clause 78 #define ERESTART -1 /* restart syscall / 79 #define EJUSTRETURN -2 / don't modify regs, just return / 91 a minimum value of 100ms. Note that this is pertinent only for SPI- 142 { 0xD8, R, "CD-DA READ" } 149 * to read CD-D 4727 struct scsi_sense_ata_ret_desc *res; scsi_sense_ata_sbuf() local [all...]`
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A D	ARMAsmParser.cpp	`1 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===// 5 // SPDX-Licens 4683 ParseStatus Res = parseVectorLane(LaneKind, LaneIndex, E); parseVectorList() local 4704 ParseStatus Res = parseVectorLane(LaneKind, LaneIndex, E); parseVectorList() local 6050 int Res = tryParseShiftRegister(Operands); parseOperand() local [all...]`
/freebsd-src/sys/contrib/zstd/lib/common/
H A D	xxhash.h	2 * xxHash - Fast Hash algorithm 6 * - xxHash homepage: http://www.xxhash.com 7 * - xxHash source repository : https://github.com/Cyan4973/xxHash 9 * This source code is licensed under both the BSD-style license (found in the 12 * You may select, at your option, one of the above-listed licenses. 49 MD5-32 0.33 GB/s 10 Ronald L. Rivest 50 SHA1-32 0.28 GB/s 10 57 Other speed-oriented implementations can be faster, 59 https://fastcompression.blogspot.com/2019/03/presenting-xxh3.html?showComment=1552696407071#c349009… 61 A 64-bit version, named XXH64, is available since r35. [all …]
/freebsd-src/sys/contrib/dev/ath/ath_hal/ar9300/
H A D	ar9300_reset.c	121 ahp->ah_hwp = HAL_TRUE_CHIP; in ar9300_attach_hw_platform() 196 * Mask used to construct AAD for CCMP-AES in ar9300_init_mfp() 197 * Cisco spec defined bits 0-3 as mask in ar9300_init_mfp() 226 centers->ctl_center = centers->ext_center = in ar9300_get_channel_centers() 227 centers->synth_center = ichan->channel; in ar9300_get_channel_centers() 238 centers->synth_center = ichan->channel + HT40_CHANNEL_CENTER_SHIFT; in ar9300_get_channel_centers() 241 centers->synth_center = ichan->channel - HT40_CHANNEL_CENTER_SHIFT; in ar9300_get_channel_centers() 242 extoff = -1; in ar9300_get_channel_centers() 245 centers->ctl_center = in ar9300_get_channel_centers() 246 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); in ar9300_get_channel_centers() [all …]