Searched +full:t1 +full:- +full:framing +full:- +full:tx (Results 1 – 1 of 1) sorted by relevance
2 * Copyright (c) 2017-2018 Cavium, Inc. 73 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX76 … 0x003824UL //Access:R DataWidth:0x20 // tx number of tlp sent78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…116 … (0x1<<9) // Fast back-to-back transaction ena…[all …]