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/freebsd-src/sys/contrib/device-tree/Bindings/sound/
H A Dti,j721e-cpb-ivi-audio.yaml24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
28 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
38 PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
H A Dti,j721e-cpb-audio.yaml20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
29 PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
/freebsd-src/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dqcom,mmcc-msm8960.h135 #define PLL15 126 macro