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/llvm-project/llvm/tools/llvm-readobj/
H A DARMWinEHPrinter.h38 bool opcode_0xxxxxxx(const uint8_t *Opcodes, unsigned &Offset,
40 bool opcode_10Lxxxxx(const uint8_t *Opcodes, unsigned &Offset,
42 bool opcode_1100xxxx(const uint8_t *Opcodes, unsigned &Offset,
44 bool opcode_11010Lxx(const uint8_t *Opcodes, unsigned &Offset,
46 bool opcode_11011Lxx(const uint8_t *Opcodes, unsigned &Offset,
48 bool opcode_11100xxx(const uint8_t *Opcodes, unsigned &Offset,
50 bool opcode_111010xx(const uint8_t *Opcodes, unsigned &Offset,
52 bool opcode_1110110L(const uint8_t *Opcodes, unsigned &Offset,
54 bool opcode_11101110(const uint8_t *Opcodes, unsigned &Offset,
56 bool opcode_11101111(const uint8_t *Opcodes, unsigned &Offset,
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H A DARMEHABIPrinter.h34 void (OpcodeDecoder::*Routine)(const uint8_t *Opcodes, unsigned &OI);
38 void Decode_00xxxxxx(const uint8_t *Opcodes, unsigned &OI);
39 void Decode_01xxxxxx(const uint8_t *Opcodes, unsigned &OI);
40 void Decode_1000iiii_iiiiiiii(const uint8_t *Opcodes, unsigned &OI);
41 void Decode_10011101(const uint8_t *Opcodes, unsigned &OI);
42 void Decode_10011111(const uint8_t *Opcodes, unsigned &OI);
43 void Decode_1001nnnn(const uint8_t *Opcodes, unsigned &OI);
44 void Decode_10100nnn(const uint8_t *Opcodes, unsigned &OI);
45 void Decode_10101nnn(const uint8_t *Opcodes, unsigned &OI);
46 void Decode_10110000(const uint8_t *Opcodes, unsigned &OI);
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/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFMA3Info.h10 // about existing X86 FMA3 opcodes, classifying and grouping them.
21 /// This class is used to group {132, 213, 231} forms of FMA opcodes together.
22 /// Each of the groups has either 3 opcodes, Also, each group has an attributes
25 /// An array holding 3 forms of FMA opcodes.
26 uint16_t Opcodes[3]; member
29 /// FMA groups of opcodes.
40 /// group of FMA opcodes consists of FMA intrinsic opcodes.
44 /// group of FMA opcodes consists of AVX512 opcodes accepting a k-mask and
50 /// group of FMA opcodes consists of AVX512 opcodes accepting a k-zeromask.
56 return Opcodes[Form132]; in get132Opcode()
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/llvm-project/llvm/include/llvm/DebugInfo/GSYM/
H A DLineTable.h36 /// SLEB MinDelta The min line delta for special opcodes that advance
38 /// SLEB MaxDelta The max line delta for single byte opcodes that
52 /// form. Some opcodes cause "Row" to be modified and some opcodes may also
57 /// NORMAL OPCODES
59 /// The opcodes 0 through 3 are normal in opcodes. Their encoding and
69 /// OPCODES below).
71 /// SPECIAL OPCODES
73 /// Opcodes LTOC_FirstSpecial through 255 are special opcodes that always
82 /// these special opcodes, we calculate the number of values reserved for the
88 /// Then we can adjust the opcode to not include any of the normal opcodes:
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/llvm-project/llvm/test/CodeGen/ARM/
H A Dtail-dup.ll12 define i32 @fn(ptr nocapture %opcodes) nounwind readonly ssp {
14 %0 = load i32, ptr %opcodes, align 4
20 %1 = load i32, ptr %opcodes.addr.0, align 4
26 %2 = load i32, ptr %opcodes.addr.0, align 4
32 …%opcodes.pn = phi ptr [ %opcodes, %entry ], [ %opcodes.addr.0, %DECREMENT ], [ %opcodes.addr.0, %I…
34 %opcodes.addr.0 = getelementptr inbounds i32, ptr %opcodes.pn, i32 1
/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMUnwindOpAsm.h1 //===-- ARMUnwindOpAsm.h - ARM Unwind Opcodes Assembler ---------*- C++ -*-===//
49 /// Emit unwind opcodes for .save directives
52 /// Emit unwind opcodes for .vsave directives
55 /// Emit unwind opcodes to copy address from source register to $sp.
58 /// Emit unwind opcodes to add $sp with an offset.
61 /// Emit unwind raw opcodes
62 void EmitRaw(const SmallVectorImpl<uint8_t> &Opcodes) { in EmitRaw() argument
63 Ops.insert(Ops.end(), Opcodes.begin(), Opcodes.end()); in EmitRaw()
64 OpBegins.push_back(OpBegins.back() + Opcodes.size()); in EmitRaw()
H A DARMUnwindOpAsm.cpp1 //===-- ARMUnwindOpAsm.cpp - ARM Unwind Opcodes Assembler -------*- C++ -*-===//
46 "Only 256 additional words are allowed for unwind opcodes"); in EmitSize()
106 /// Emit unwind opcodes for .vsave directives
129 /// Emit unwind opcodes to copy address from source register to $sp.
134 /// Emit unwind opcodes to add $sp with an offset.
176 assert(Ops.size() <= 3 && "too many opcodes for __aeabi_unwind_cpp_pr0"); in Finalize()
189 // Copy the unwind opcodes in Finalize()
194 // Emit the padding finish opcodes if the size is not multiple of 4. in Finalize()
H A DARMELFStreamer.cpp88 const SmallVectorImpl<uint8_t> &Opcodes) override;
281 const SmallVectorImpl<uint8_t> &Opcodes) { in emitUnwindRaw() argument
283 for (uint8_t Opcode : Opcodes) in emitUnwindRaw()
410 const SmallVectorImpl<uint8_t> &Opcodes) override;
476 void emitUnwindRaw(int64_t Offset, const SmallVectorImpl<uint8_t> &Opcodes); in emitFill()
730 SmallVector<uint8_t, 64> Opcodes;
775 const SmallVectorImpl<uint8_t> &Opcodes) {
776 getStreamer().emitUnwindRaw(Offset, Opcodes); in emitUnwindRaw()
1216 Opcodes.clear(); in emitFnEnd()
1229 // Emit unwind opcodes i in emitFnEnd()
732 SmallVector<uint8_t, 64> Opcodes; global() member in __anonb22a74070111::ARMELFStreamer
777 emitUnwindRaw(int64_t Offset,const SmallVectorImpl<uint8_t> & Opcodes) emitUnwindRaw() argument
1455 emitUnwindRaw(int64_t Offset,const SmallVectorImpl<uint8_t> & Opcodes) emitUnwindRaw() argument
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/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsSizeReduction.cpp74 // Information about opcodes
75 struct OpCodes { struct
76 OpCodes(unsigned WideOpc, unsigned NarrowOpc) in OpCodes() argument
86 /// opcodes to narrow
92 struct OpCodes Ops; ///< All relevant OpCodes
96 ReduceEntry(enum ReduceType RType, struct OpCodes Op, in ReduceEntry()
208 // ReduceType as a sub-criterion (when wide opcodes are the same).
211 // ReduceType, OpCodes, ReduceFunction,
214 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
216 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
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/llvm-project/llvm/test/tools/llvm-readobj/ELF/ARM/
H A Dunwind.s55 .section .opcodes
57 .type opcodes,%function
58 opcodes: label
159 @ CHECK: Opcodes [
175 @ CHECK: Opcodes [
193 @ SYM: Opcodes [
217 @ CHECK: SectionName: .ARM.exidx.opcodes
221 @ SYM: FunctionName: opcodes
224 @ CHECK: Opcodes [
239 @ CHECK: Opcodes [
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H A Dunwind-non-relocatable.test20 # UNWIND-NEXT: Opcodes [
31 # UNWIND-NEXT: Opcodes [
41 # UNWIND-NEXT: Opcodes [
56 # UNWIND-NEXT: Opcodes [
99 Value: 0x80B0B0B0 ## arbitrary opcodes.
102 Value: 0x809B8480 ## arbitrary opcodes.
105 Value: 0x80B0B0B0 ## arbitrary opcodes.
111 Value: 0x80B0B0B0 ## arbitrary opcodes.
/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp84 // Store the opcodes that we might need, so we don't have to check what kind
128 } const Opcodes; member in __anon4a65c32b0111::ARMInstructionSelector
177 STI(STI), Opcodes(STI), in ARMInstructionSelector()
349 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16; in selectSimpleExtOpc()
352 return Size == 8 ? Opcodes.ZEXT8 : Opcodes.ZEXT16; in selectSimpleExtOpc()
366 return isStore ? Opcodes.STORE8 : Opcodes.LOAD8; in selectLoadStoreOpCode()
368 return isStore ? Opcodes in selectLoadStoreOpCode()
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/llvm-project/llvm/include/llvm/Target/
H A DTargetInstrPredicate.td84 // set of opcodes.
199 // Check that the instruction opcode is one of the opcodes in set `Opcodes`.
203 class CheckOpcode<list<Instruction> Opcodes> : MCInstPredicate {
204 list<Instruction> ValidOpcodes = Opcodes;
208 // `Opcodes`. This check is always expanded to "false" if we are generating
210 class CheckPseudo<list<Instruction> Opcodes> : CheckOpcode<Opcodes>;
253 // `opcodes` list, and each case is associated with MCStatement `caseStmt`.
254 class MCOpcodeSwitchCase<list<Instruction> opcodes, MCStatement caseStmt> {
255 list<Instruction> Opcodes = opcodes;
322 // a) MI's opcode is in the `opcodes` set, and
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/llvm-project/lldb/include/lldb/Symbol/
H A DUnwindPlan.h164 void GetDWARFExpr(const uint8_t **opcodes, uint16_t &len) const {
166 *opcodes = m_location.expr.opcodes;
169 *opcodes = nullptr; in GetDWARFExpressionBytes()
174 void SetAtDWARFExpression(const uint8_t *opcodes, uint32_t len); in GetDWARFExpressionLength()
176 void SetIsDWARFExpression(const uint8_t *opcodes, uint32_t len); in GetDWARFExpressionLength()
180 return m_location.expr.opcodes;
202 const uint8_t *opcodes;
257 void SetIsDWARFExpression(const uint8_t *opcodes, uint32_t len) {
259 m_value.expr.opcodes in GetOffset()
154 GetDWARFExpr(const uint8_t ** opcodes,uint16_t & len) GetDWARFExpr() argument
192 const uint8_t *opcodes; global() member
244 SetIsDWARFExpression(const uint8_t * opcodes,uint32_t len) SetIsDWARFExpression() argument
279 GetDWARFExpr(const uint8_t ** opcodes,uint16_t & len) GetDWARFExpr() argument
315 const uint8_t *opcodes; global() member
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/llvm-project/llvm/lib/ObjCopy/MachO/
H A DMachOWriter.cpp58 assert((DyLdInfoCommand.rebase_size == O.Rebases.Opcodes.size()) && in totalSize()
59 "Incorrect rebase opcodes size"); in totalSize()
63 assert((DyLdInfoCommand.bind_size == O.Binds.Opcodes.size()) && in totalSize()
64 "Incorrect bind opcodes size"); in totalSize()
68 assert((DyLdInfoCommand.weak_bind_size == O.WeakBinds.Opcodes.size()) && in totalSize()
69 "Incorrect weak bind opcodes size"); in totalSize()
74 assert((DyLdInfoCommand.lazy_bind_size == O.LazyBinds.Opcodes.size()) && in totalSize()
75 "Incorrect lazy bind opcodes size"); in totalSize()
323 assert((DyLdInfoCommand.rebase_size == O.Rebases.Opcodes.size()) && in writeRebaseInfo()
324 "Incorrect rebase opcodes siz in writeRebaseInfo()
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H A DMachOLayoutBuilder.cpp278 uint64_t StartOfRebaseInfo = updateOffset(O.Rebases.Opcodes.size()); in layoutTail()
279 uint64_t StartOfBindingInfo = updateOffset(O.Binds.Opcodes.size()); in layoutTail()
280 uint64_t StartOfWeakBindingInfo = updateOffset(O.WeakBinds.Opcodes.size()); in layoutTail()
281 uint64_t StartOfLazyBindingInfo = updateOffset(O.LazyBinds.Opcodes.size()); in layoutTail()
399 O.Rebases.Opcodes.empty() ? 0 : StartOfRebaseInfo; in layoutTail()
400 MLC.dyld_info_command_data.rebase_size = O.Rebases.Opcodes.size(); in layoutTail()
402 O.Binds.Opcodes.empty() ? 0 : StartOfBindingInfo; in layoutTail()
403 MLC.dyld_info_command_data.bind_size = O.Binds.Opcodes.size(); in layoutTail()
405 O.WeakBinds.Opcodes.empty() ? 0 : StartOfWeakBindingInfo; in layoutTail()
406 MLC.dyld_info_command_data.weak_bind_size = O.WeakBinds.Opcodes in layoutTail()
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/llvm-project/lldb/source/Expression/
H A DDWARFExpression.cpp168 // Opcodes with no arguments in GetOpcodeDataSize()
268 // Opcodes with a single 1 byte arguments in GetOpcodeDataSize()
277 // Opcodes with a single 2 byte arguments in GetOpcodeDataSize()
285 // Opcodes with a single 4 byte arguments in GetOpcodeDataSize()
291 // Opcodes with a single 8 byte arguments in GetOpcodeDataSize()
296 // All opcodes that have a single ULEB (signed or unsigned) argument in GetOpcodeDataSize()
345 // All opcodes that have a 2 ULEB (signed or unsigned) arguments in GetLocation_DW_OP_addr()
587 const DataExtractor &opcodes, in Evaluate_DW_OP_entry_value()
723 const uint32_t subexpr_len = opcodes.GetULEB128(&opcode_offset);
724 const void *subexpr_data = opcodes
534 Evaluate_DW_OP_entry_value(std::vector<Value> & stack,ExecutionContext * exe_ctx,RegisterContext * reg_ctx,const DataExtractor & opcodes,lldb::offset_t & opcode_offset,Log * log) Evaluate_DW_OP_entry_value() argument
824 Evaluate(ExecutionContext * exe_ctx,RegisterContext * reg_ctx,lldb::ModuleSP module_sp,const DataExtractor & opcodes,const DWARFUnit * dwarf_cu,const lldb::RegisterKind reg_kind,const Value * initial_value_ptr,const Value * object_address_ptr) Evaluate() argument
2335 DataExtractor opcodes(m_data); MatchesOperand() local
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/llvm-project/llvm/test/MC/ARM/
H A Dseh-epilog-sharing.s1 // This test checks various cases around sharing opcodes between epilogue and prologue with more th…
26 // CHECK-NEXT: Opcodes [
35 // CHECK-NEXT: Opcodes [
44 // CHECK-NEXT: Opcodes [
74 // CHECK-NEXT: Opcodes [
84 // CHECK-NEXT: Opcodes [
93 // CHECK-NEXT: Opcodes [
136 // Epilogue matches the first one; will reuse that epilogue's opcodes,
H A Deh-directive-unwind_raw.s64 @ CHECK: Opcodes [
72 @ CHECK: Opcodes [
82 @ CHECK: Opcodes [
93 @ CHECK: Opcodes [
101 @ CHECK: Opcodes [
/llvm-project/clang/lib/AST/
H A DCMakeLists.txt12 clang_tablegen(Opcodes.inc
13 -gen-clang-opcodes
14 SOURCE ByteCode/Opcodes.td
15 TARGET Opcodes)
142 Opcodes
/llvm-project/llvm/tools/llvm-exegesis/lib/
H A DSerialSnippetGenerator.cpp44 std::vector<unsigned> Opcodes; in computeAliasingInstructions() local
45 Opcodes.resize(State.getInstrInfo().getNumOpcodes()); in computeAliasingInstructions()
46 std::iota(Opcodes.begin(), Opcodes.end(), 0U); in computeAliasingInstructions()
47 llvm::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator()); in computeAliasingInstructions()
50 for (const unsigned OtherOpcode : Opcodes) { in computeAliasingInstructions()
/llvm-project/llvm/include/llvm/MCA/Stages/
H A DMicroOpQueueStage.h10 /// This file defines a stage that implements a queue of micro opcodes.
11 /// It can be used to simulate a hardware micro-op queue that serves opcodes to
25 /// A stage that simulates a queue of instruction opcodes.
49 // number of micro opcodes (see field `InstrDesc::NumMicroOpcodes`). The
53 // opcodes than doesn't fit in the buffer.
/llvm-project/lld/MachO/
H A DSyntheticSections.cpp214 // Rebases are communicated to dyld using a bytecode, whose opcodes cause the
425 // Encode a sequence of opcodes that tell dyld to write the address of symbol +
433 std::vector<BindIR> &opcodes) { in encodeBinding()
437 opcodes.push_back( in encodeBinding()
444 opcodes.push_back({BIND_OPCODE_ADD_ADDR_ULEB, offset - lastBinding.offset}); in encodeBinding()
449 opcodes.push_back( in encodeBinding()
454 opcodes.push_back({BIND_OPCODE_DO_BIND, 0}); in encodeBinding()
459 static void optimizeOpcodes(std::vector<BindIR> &opcodes) { in optimizeOpcodes()
463 for (i = 1; i < opcodes.size(); ++i, ++pWrite) { in optimizeOpcodes()
464 if ((opcodes[ in optimizeOpcodes()
432 encodeBinding(const OutputSection * osec,uint64_t outSecOff,int64_t addend,Binding & lastBinding,std::vector<BindIR> & opcodes) encodeBinding() argument
458 optimizeOpcodes(std::vector<BindIR> & opcodes) optimizeOpcodes() argument
643 std::vector<BindIR> opcodes; finalizeContents() local
677 std::vector<BindIR> opcodes; finalizeContents() local
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/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetOpcodes.h1 //===-- llvm/CodeGen/TargetOpcodes.h - Target Indep Opcodes -----*- C++ -*-===//
9 // This file defines the target independent instruction opcodes.
18 /// Invariant opcodes: All instruction sets have these as their low opcodes.
/llvm-project/lldb/source/Symbol/
H A DUnwindPlan.cpp46 return !memcmp(m_location.expr.opcodes, rhs.m_location.expr.opcodes, in operator ==()
59 const uint8_t *opcodes, uint32_t len) { in SetAtDWARFExpression()
61 m_location.expr.opcodes = opcodes; in SetAtDWARFExpression()
68 const uint8_t *opcodes, uint32_t len) { in SetIsDWARFExpression()
70 m_location.expr.opcodes = opcodes; in SetIsDWARFExpression()
151 s, llvm::ArrayRef(m_location.expr.opcodes, m_location.expr.length), in Dump()
187 return !memcmp(m_value.expr.opcodes, rh in operator ==()
57 SetAtDWARFExpression(const uint8_t * opcodes,uint32_t len) SetAtDWARFExpression() argument
66 SetIsDWARFExpression(const uint8_t * opcodes,uint32_t len) SetIsDWARFExpression() argument
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