| /freebsd-src/sys/contrib/device-tree/Bindings/iommu/ |
| H A D | samsung,sysmmu.yaml | 7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
17 System MMU is an IOMMU and supports identical translation table format to
19 permissions, shareability and security protection. In addition, System MMU has
25 master), but one System MMU can handle transactions from only one peripheral
26 device. The relation between a System MMU and the peripheral device needs to be
31 * MFC has one System MMU on its left and right bus.
32 * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
34 * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
35 the other System MMU on the write channel.
37 For information on assigning System MMU controller to its peripheral devices,
[all …]
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| H A D | arm,smmu.yaml | 7 title: ARM System MMU Architecture Implementation
35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
64 - const: arm,mmu-500
66 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
84 - const: arm,mmu-500
85 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
105 - const: arm,mmu-500
106 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
115 - const: arm,mmu-500
131 - description: Marvell SoCs implementing "arm,mmu
[all...] |
| H A D | rockchip,iommu.yaml | 33 - description: configuration registers for MMU instance 0
34 - description: configuration registers for MMU instance 1
39 - description: interruption for MMU instance 0
40 - description: interruption for MMU instance 1
59 rockchip,disable-mmu-reset:
62 Do not use the mmu reset operation.
63 Some mmu instances may produce unexpected results
|
| H A D | ti,omap-iommu.txt | 22 back a bus error response on MMU faults.
25 register for enabling the MMU, and the MMU instance
32 /* OMAP3 ISP MMU */
33 mmu_isp: mmu@480bd400 {
43 mmu0_dsp2: mmu@41501000 {
52 mmu1_dsp2: mmu@41502000 {
|
| H A D | rockchip,iommu.txt | 24 - rockchip,disable-mmu-reset : Don't use the mmu reset operation.
25 Some mmu instances may produce unexpected results
|
| /freebsd-src/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | branch.json | 18 …still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off",
21 … still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off"
24 … the address. This event still counts when branch prediction is disabled due to the MMU being off",
27 …r the address. This event still counts when branch prediction is disabled due to the MMU being off"
30 … the address. This event still counts when branch prediction is disabled due to the MMU being off",
33 …d the address. This event still counts when branch prediction is disabled due to the MMU being off"
36 …ion. This event still counts when branch prediction is disabled due to the MMU being off. Conditio…
39 …ion. This event still counts when branch prediction is disabled due to the MMU being off. Conditio…
42 …he condition. This event still counts when branch prediction is disabled due to the MMU being off",
45 …the condition. This event still counts when branch prediction is disabled due to the MMU being off"
[all …]
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| H A D | cache.json | 144 … "PublicDescription": "L2 TLB walk cache access. This event does not count if the MMU is disabled",
147 … "BriefDescription": "L2 TLB walk cache access. This event does not count if the MMU is disabled"
150 … "PublicDescription": "L2 TLB walk cache refill. This event does not count if the MMU is disabled",
153 … "BriefDescription": "L2 TLB walk cache refill. This event does not count if the MMU is disabled"
|
| /freebsd-src/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/ |
| H A D | branch.json | 18 …r is retired. This event still counts when branch prediction is disabled due to the MMU being off",
21 …or is retired. This event still counts when branch prediction is disabled due to the MMU being off"
24 … the address. This event still counts when branch prediction is disabled due to the MMU being off",
27 …r the address. This event still counts when branch prediction is disabled due to the MMU being off"
30 … the address. This event still counts when branch prediction is disabled due to the MMU being off",
33 …d the address. This event still counts when branch prediction is disabled due to the MMU being off"
36 …ion. This event still counts when branch prediction is disabled due to the MMU being off. Conditio…
39 …ion. This event still counts when branch prediction is disabled due to the MMU being off. Conditio…
42 …he condition. This event still counts when branch prediction is disabled due to the MMU being off",
45 …the condition. This event still counts when branch prediction is disabled due to the MMU being off"
[all …]
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| H A D | cache.json | 147 …tion": "Level 2 TLB last-level walk cache access.This event does not count if the MMU is disabled",
150 …ption": "Level 2 TLB last-level walk cache access.This event does not count if the MMU is disabled"
153 …tion": "Level 2 TLB last-level walk cache refill.This event does not count if the MMU is disabled",
156 …ption": "Level 2 TLB last-level walk cache refill.This event does not count if the MMU is disabled"
159 …regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled",
162 … regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled"
165 …ription": "Level 2 TLB level-2 walk cache refill.This event does not count if the MMU is disabled",
168 …cription": "Level 2 TLB level-2 walk cache refill.This event does not count if the MMU is disabled"
|
| /freebsd-src/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a73/ |
| H A D | mmu.json | 3 "PublicDescription": "Duration of a translation table walk handled by the MMU",
6 "BriefDescription": "Duration of a translation table walk handled by the MMU"
9 "PublicDescription": "Duration of a Stage 1 translation table walk handled by the MMU",
12 "BriefDescription": "Duration of a Stage 1 translation table walk handled by the MMU"
15 "PublicDescription": "Duration of a Stage 2 translation table walk handled by the MMU",
18 "BriefDescription": "Duration of a Stage 2 translation table walk handled by the MMU"
|
| /freebsd-src/sys/contrib/device-tree/src/riscv/sophgo/ |
| H A D | sg2042-cpus.dtsi | 272 mmu-type = "riscv,sv39";
297 mmu-type = "riscv,sv39";
322 mmu-type = "riscv,sv39";
347 mmu-type = "riscv,sv39";
372 mmu-type = "riscv,sv39";
397 mmu-type = "riscv,sv39";
422 mmu-type = "riscv,sv39";
447 mmu-type = "riscv,sv39";
472 mmu-type = "riscv,sv39";
497 mmu-type = "riscv,sv39";
[all …]
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| /freebsd-src/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a75/ |
| H A D | mmu.json | 3 "PublicDescription": "Duration of a translation table walk handled by the MMU",
6 "BriefDescription": "Duration of a translation table walk handled by the MMU"
9 …"PublicDescription": "Duration of a Stage 1 translation table walk handled by the MMU. This event …
12 …"BriefDescription": "Duration of a Stage 1 translation table walk handled by the MMU. This event i…
15 …"PublicDescription": "Duration of a Stage 2 translation table walk handled by the MMU. This event …
18 …"BriefDescription": "Duration of a Stage 2 translation table walk handled by the MMU. This event i…
|
| H A D | cache.json | 135 …"PublicDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwa…
138 …"BriefDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwar…
153 …and preload instructions. This event does not take into account whether the MMU is enabled or not",
156 … and preload instructions. This event does not take into account whether the MMU is enabled or not"
|
| /freebsd-src/sys/contrib/device-tree/src/riscv/kendryte/ |
| H A D | k210.dtsi | 22 * The K210 has an sv39 MMU following the priviledge specification v1.9.
24 * support it and the K210 support enabled only for the !MMU case.
25 * Be consistent with this by setting the CPUs MMU type to "none".
36 mmu-type = "none";
54 mmu-type = "none";
|
| /freebsd-src/sys/powerpc/include/ |
| H A D | mmuvar.h | 193 const struct mmu_kobj *mmu = mmu_obj; \
195 f = mmu->funcs->func; \
197 mmu = mmu->base; \
198 } while (mmu != NULL); \
216 * Known MMU names
218 #define MMU_TYPE_BOOKE "mmu_booke" /* Book-E MMU specification */
|
| /freebsd-src/lib/libkvm/ |
| H A D | kvm_powerpc64.h | 53 /* MMU interface */
54 #define PPC64_MMU_OPS(kd) (kd)->vmst->mmu.ops
56 #define PPC64_MMU_DATA(kd) (kd)->vmst->mmu.data
74 struct ppc64_mmu mmu; member
|
| /freebsd-src/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/ |
| H A D | cache.json | 153 …ion": "Level 2 TLB last-level walk cache access. This event does not count if the MMU is disabled",
156 …tion": "Level 2 TLB last-level walk cache access. This event does not count if the MMU is disabled"
159 …ion": "Level 2 TLB last-level walk cache refill. This event does not count if the MMU is disabled",
162 …tion": "Level 2 TLB last-level walk cache refill. This event does not count if the MMU is disabled"
165 …regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled",
168 … regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled"
171 …iption": "Level 2 TLB level-2 walk cache refill. This event does not count if the MMU is disabled",
174 …ription": "Level 2 TLB level-2 walk cache refill. This event does not count if the MMU is disabled"
|
| /freebsd-src/sys/riscv/riscv/ |
| H A D | identcpu.c | 313 char mmu[16]; in parse_mmu_fdt()
316 if (OF_getprop(node, "mmu-type", mmu, sizeof(mmu)) > 0) { in parse_mmu_fdt()
317 if (strcmp(mmu, "riscv,sv48") == 0) in parse_mmu_fdt()
319 else if (strcmp(mmu, "riscv,sv57") == 0)
372 /* Check MMU features. */ in identify_cpu_features_fdt()
415 * MMU capabilities, e.g. Sv48. in update_global_capabilities()
540 printf(" MMU: %#b\n", desc->mmu_caps,
308 char mmu[16]; parse_mmu_fdt() local
|
| /freebsd-src/sys/ofed/drivers/infiniband/core/ |
| H A D | ib_umem_odp.c | 82 /* Account for a new mmu notifier in an ib_ucontext. */
88 /* Account for a terminating mmu notifier in an ib_ucontext.
98 /* No currently running mmu notifiers. Now is the chance to in ib_ucontext_notifier_end_account()
102 /* Prevent concurrent mmu notifiers from working on the in ib_ucontext_notifier_end_account()
288 * When using MMU notifiers, we will get a in ib_umem_odp_get()
307 * Note that at this point, no MMU notifier is running in ib_umem_odp_get()
374 * will be able to enventually obtain the mmu notifiers SRCU. Note in ib_umem_odp_release()
504 * An -EAGAIN error code is returned when a concurrent mmu notifier prevents
515 * @current_seq: the MMU notifiers sequance value for synchronization with
652 * the page lock. However, MMU notifiers are in ib_umem_odp_unmap_dma_pages()
[all …]
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| /freebsd-src/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a76-n1/ |
| H A D | cache.json | 47 … on a cycle, this event counts twice. This event counts regardless of whether the MMU is enabled.",
52 …which accesses the instruction L1 TLB.This event counts regardless of whether the MMU is enabled.",
72 … caused by either an instruction or data access.This event does not count if the MMU is disabled.",
77 …TLB (caused by a refill of any of the L1 TLBs). This event does not count if the MMU is disabled.",
|
| /freebsd-src/sys/contrib/device-tree/Bindings/nios2/ |
| H A D | nios2.txt | 27 - altr,has-mmu: Specifies CPU support MMU support, should be 1.
61 altr,has-mmu = <1>;
|
| /freebsd-src/stand/powerpc/ofw/ |
| H A D | cas.c | 94 /* byte 24: MMU */
101 /* byte 25: HPT MMU Extensions */
105 /* byte 26: Radix MMU Extensions */
257 DPRINTF("MMU 0x%02x RADIX_EXT 0x%02x\n", in ppc64_cas()
268 printf("cas: selected %s MMU\n", radix_mmu ? "radix" : "hash");
|
| /freebsd-src/sys/contrib/device-tree/Bindings/riscv/ |
| H A D | cpus.yaml | 65 mmu-type:
67 Identifies the largest MMU address translation mode supported by
175 mmu-type = "riscv,sv39";
198 mmu-type = "riscv,sv48";
|
| /freebsd-src/sys/powerpc/powerpc/ |
| H A D | pmap_dispatch.c | 32 * Dispatch MI pmap calls to the appropriate MMU implementation
38 * MMU handler when pmap_bootstrap() is called.
194 * MMU install routines. Highest priority wins, equal priority also
206 * Try and locate the MMU kobj corresponding to the name in pmap_mmu_install()
223 /* MMU "pre-bootstrap" init, used to install extra resolvers, etc. */
|
| /freebsd-src/sys/arm/arm/ |
| H A D | locore.S | 128 * valid. Disable all caches and the MMU, and invalidate everything
129 * before setting up new page tables and re-enabling the mmu.
272 * Init MMU
278 /* Setup TLB and MMU registers */
306 /* Enable MMU */
325 * Init SMP coherent mode, enable caching and switch to final MMU table.
528 * the cpu reset after turning the MMU off
|