| /freebsd-src/sys/contrib/device-tree/Bindings/net/ |
| H A D | ibm,emac.txt | 8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
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| H A D | xilinx_axienet.txt | 2 --------------------------------------------------------
15 For more details about mdio please refer phy.txt file in the same directory.
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
25 and optionally Ethernet core. If axistream-connected is
29 - phy-handle : Should point to the external phy device if exists. Pointing
32 - xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware
[all …]
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| H A D | brcm,bcmgenet.txt | 4 - compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2",
5 "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5", "brcm,bcm2711-genet-v5" or
6 "brcm,bcm7712-genet-v5".
7 - reg: address and length of the register set for the device
8 - interrupts and/or interrupts-extended: must be two cells, the first cell
11 optional third interrupt cell for Wake-on-LAN can be specified.
12 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
14 - phy-mode: see ethernet.txt file in the same directory
15 - #address-cells: should be 1
16 - #size-cells: should be 1
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| H A D | mdio-gpio.txt | 1 MDIO on GPIOs
4 - virtual,gpio-mdio
5 - microchip,mdio-smi0
7 MDC and MDIO lines connected to GPIO controllers are listed in the
10 MDC, MDIO.
12 Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases"
18 mdio-gpio0 = &mdio0;
21 mdio0: mdio {
22 compatible = "virtual,mdio-gpio";
23 #address-cells = <1>;
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| H A D | marvell-orion-mdio.txt | 1 * Marvell MDIO Ethernet Controller interface
5 identical unit that provides an interface with the MDIO bus.
11 - compatible: "marvell,orion-mdio" or "marvell,xmdio"
12 - reg: address and length of the MDIO registers. When an interrupt is
18 - interrupts: interrupt line number for the SMI error/done interrupt
19 - clocks: phandle for up to four required clocks for the MDIO instance
21 The child nodes of the MDIO driver are the individual PHY devices
22 connected to this MDIO bus. They must have a "reg" property given the
23 PHY address on the MDIO bus.
27 mdio {
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| H A D | mdio-mux.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common MDIO bus multiplexer/switch properties.
10 - Andrew Lunn <andrew@lunn.ch>
13 An MDIO bus multiplexer/switch will have several child busses that are
14 numbered uniquely in a device dependent manner. The nodes for an MDIO
18 mdio-parent-bus:
21 The phandle of the MDIO bus that this multiplexer's master-side port is
[all …]
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| H A D | qcom,ipq8064-mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ipq8064-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x MDIO bus controller
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 The ipq806x soc have a MDIO dedicated controller that is
14 used to communicate with the gmac phy connected.
17 - $ref: mdio.yaml#
21 const: qcom,ipq8064-mdio
[all …]
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| H A D | mdio-mux-multiplexer.txt | 1 Properties for an MDIO bus multiplexer consumer device
3 This is a special case of MDIO mux when MDIO mux is defined as a consumer
7 Required properties in addition to the MDIO Bus multiplexer properties:
9 - compatible : should be "mmio-mux-multiplexer"
10 - mux-controls : mux controller node to use for operating the mux
11 - mdio-parent-bus : phandle to the parent MDIO bus.
13 each child node of mdio bus multiplexer consumer device represent a mdio
17 Documentation/devicetree/bindings/mux/mux-controller.txt
18 and Documentation/devicetree/bindings/net/mdio-mux.txt
24 fpga@66 { // fpga connected to i2c
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| H A D | mediatek,star-emac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
14 It's compliant with 802.3 standards and supports half- and full-duplex
15 modes with flow-control as well as CRC offloading and VLAN tags.
18 - $ref: ethernet-controller.yaml#
23 - mediatek,mt8516-eth
24 - mediatek,mt8518-eth
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| H A D | mdio-mux-mmioreg.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
[all …]
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| H A D | mdio-mux-mmioreg.txt | 1 Properties for an MDIO bus multiplexer controlled by a memory-mapped device
3 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
4 like an FPGA, is used to control which child bus is connected. The mdio-mux
5 node must be a child of the memory-mapped device. The driver currently only
6 supports devices with 8, 16 or 32-bit registers.
10 - compatible : string, must contain "mdio-mux-mmioreg"
12 - reg : integer, contains the offset of the register that controls the bus
16 - mux-mask : integer, contains an eight-bit mask that specifies which
18 'reg' property of each child mdio-mux node must be constrained by
23 The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes.
[all …]
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| H A D | fsl-enetc.txt | 9 - reg : Specifies PCIe Device Number and Function
12 - compatible : Should be "fsl,enetc".
14 1. The ENETC external port is connected to a MDIO configurable phy
16 1.1. Using the local ENETC Port MDIO interface
18 In this case, the ENETC node should include a "mdio" sub-node
19 that in turn should contain the "ethernet-phy" node describing the
26 - phy-handle : Phandle to a PHY on the MDIO bus.
29 - phy-connection-type : Defined in ethernet.txt.
31 - mdio : "mdio" node, defined in mdio.txt.
33 - ethernet-phy : "ethernet-phy" node, defined in phy.txt.
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| H A D | xlnx,axi-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-etherne
[all...] |
| H A D | marvell,mvusb.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell USB to MDIO Controller
10 - Tobias Waldekranz <tobias@waldekranz.com>
15 using the standard MDIO interface.
17 Since the device is connected over USB, there is no strict requirement of
23 - $ref: mdio.yaml#
33 - compatible
34 - reg
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| H A D | fsl-tsec-phy.txt | 1 * MDIO IO device
3 The MDIO is a bus to which the PHY devices are connected. For each
5 the definition of the PHY node in booting-without-of.txt for an example
9 - reg : Offset and length of the register set for the device, and optionally
14 - compatible : Should define the compatible device type for the
15 mdio. Currently supported strings/devices are:
16 - "fsl,gianfar-tb
[all...] |
| H A D | hisilicon-hip04-net.txt | 6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
11 port, port number connected to the controller
14 - phy-mode: see ethernet.txt [1].
17 - ph
[all...] |
| H A D | socionext-netsec.txt | 4 - compatible: Should be "socionext,synquacer-netsec"
5 - reg: Address and length of the control register area, followed by the
8 - interrupts: Should contain ethernet controller interrupt
9 - clocks: phandle to the PHY reference clock
10 - clock-names: Should be "phy_ref_clk"
11 - phy-mode: See ethernet.txt file in the same directory
12 - phy-handle: See ethernet.txt in the same directory.
14 - mdio device tree subnode: When the Netsec has a phy connected to its local
15 mdio, there must be device tree subnode with the following
18 - #address-cells: Must be <1>.
[all …]
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| H A D | xlnx,gmii-to-rgmii.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,gmii-t
[all...] |
| /freebsd-src/sys/contrib/device-tree/Bindings/net/dsa/ |
| H A D | marvell.txt | 2 ---------------------------------------
10 Marvell Switches are MDIO devices. The following properties should be
11 placed as a child node of an mdio device.
17 which is at a different MDIO base address in different switch families.
18 - "marvell,mv88e6085" : Switch has base address 0x10. Use with models:
22 - "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
24 - "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model:
28 - compatible : Should be one of "marvell,mv88e6085",
31 - reg : Address on the MII bus for the switch.
35 - reset-gpios : Should be a gpio specifier for a reset line
[all …]
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| H A D | qca8k.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
15 it is connected to. This is because there is no N:N mapping of port and PHY
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
19 the MDIO master is used for communication. Mixed external and internal
20 mdio-bus configurations are not supported by the hardware.
[all …]
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| H A D | qca8k.txt | 5 - compatible: should be one of:
10 - #size-cells: must be 0
11 - #address-cells: must be 1
15 - reset-gpios: GPIO to be used to reset the whole device
21 mdio-bus each subnode describing a port needs to have a valid phandle
22 referencing the internal PHY it is connected to. This is because there's no
24 To declare the internal mdio-bus configuration, declare a mdio node in the
26 PHY is connected to. In this config a internal mdio-bus is registered and
27 the mdio MASTER is used as communication.
29 Don't use mixed external and internal mdio-bus configurations, as this is
[all …]
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| H A D | marvell,mv88e6xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
22 - enum:
23 - marvell,mv88e6085
24 - marvell,mv88e6190
25 - marvell,mv88e6250
43 - items:
44 - const: marvell,turris-mox-mv88e6085
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| H A D | mediatek,mt7530.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...] |
| H A D | marvell,mv88e6060.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
15 MDIO address of the switch to be 0x10 or 0x00, and on the MDIO bus
16 connected to the switch, the PHYs inside the switch appear as
17 independent devices on address 0x00-0x04 or 0x10-0x14, so in difference
19 MDIO bus for the PHY devices.
31 reset-gpios:
37 - $ref: dsa.yaml#/$defs/ethernet-ports
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| /freebsd-src/sys/contrib/device-tree/Bindings/mux/ |
| H A D | reg-mux.txt | 1 Generic register bitfield-based multiplexer controller bindings
7 - compatible : should be one of
8 "reg-mux" : if parent device of mux controller is not syscon device
9 "mmio-mux" : if parent device of mux controller is syscon device
10 - #mux-control-cells : <1>
11 - mux-reg-masks : an array of register offset and pre-shifted bitfield mask
13 * Standard mux-controller bindings as decribed in mux-controller.txt
16 - idle-states : if present, the state the muxes will have when idle. The
21 pair in the mux-reg-masks array.
27 fpga@66 { // fpga connected to i2c
[all …]
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