/freebsd-src/sys/contrib/device-tree/Bindings/phy/ |
H A D | phy-mtk-ufs.txt | 1 MediaTek Universal Flash Storage (UFS) M-PHY binding 2 -------------------------------------------------------- 4 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro. 5 Each UFS M-PHY node should have its own node. 7 To bind UFS M-PHY with UFS host controller, the controller node should 8 contain a phandle reference to UFS M-PHY node. 10 Required properties for UFS M-PHY nodes: 11 - compatible : Compatible list, contains the following controller: 12 "mediatek,mt8183-ufsphy" for ufs phy 14 - reg : Address and length of the UFS M-PHY register set. [all …]
|
H A D | mediatek,ufs-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: MediaTek Universal Flash Storage (UFS) M-PHY 11 - Stanley Chu <stanley.chu@mediatek.com> 12 - Chunfeng Yun <chunfeng.yun@mediatek.com> 15 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro. 16 Each UFS M-PHY node should have its own node. 17 To bind UFS M-PHY with UFS host controller, the controller node should [all …]
|
H A D | starfive,jh7110-usb-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: StarFive JH7110 USB 2.0 PHY 10 - Minda Chen <minda.chen@starfivetech.com> 14 const: starfive,jh7110-usb-phy 19 "#phy-cells": 24 - description: PHY 125m 25 - description: app 125m [all …]
|
H A D | phy-mtk-tphy.txt | 1 MediaTek T-PHY binding 2 -------------------------- 4 T-phy controller supports physical layer functionality for a number of 8 - compatible : should be one of 9 "mediatek,generic-tphy-v1" 10 "mediatek,generic-tphy-v2" 11 "mediatek,mt2701-u3phy" (deprecated) 12 "mediatek,mt2712-u3phy" (deprecated) 13 "mediatek,mt8173-u3phy"; 14 make use of "mediatek,generic-tphy-v1" on mt2701 instead and [all …]
|
H A D | phy-rockchip-inno-usb2.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip USB2.0 phy with inno IP block 10 - Heiko Stuebner <heiko@sntech.de> 15 - rockchip,px30-usb2phy 16 - rockchip,rk3128-usb2phy 17 - rockchip,rk3228-usb2phy 18 - rockchip,rk3308-usb2phy [all …]
|
H A D | phy-mtk-xsphy.txt | 1 MediaTek XS-PHY binding 2 -------------------------- 4 The XS-PHY controller supports physical layer functionality for USB3.1 8 - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy", 9 soc-model is the name of SoC, such as mt3611 etc; 12 - "mediatek,mt3611-xsphy" 14 - #address-cells, #size-cells : should use the same values as the root node 15 - ranges: must be present 18 - reg : offset and length of register shared by multiple U3 ports, 21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate [all …]
|
H A D | rockchip,inno-usb2phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip USB2.0 phy with inno IP block 10 - Heiko Stuebner <heiko@sntech.de> 15 - rockchip,px30-usb2phy 16 - rockchip,rk3128-usb2phy 17 - rockchip,rk3228-usb2phy 18 - rockchip,rk3308-usb2phy [all …]
|
H A D | rockchip,rk3288-dp-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/rockchip,rk3288-dp-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip specific extensions to the Analogix Display Port PHY 10 - Heiko Stuebner <heiko@sntech.de> 14 const: rockchip,rk3288-dp-phy 19 clock-names: 20 const: 24m 22 "#phy-cells": [all …]
|
H A D | rockchip-dp-phy.txt | 1 Rockchip specific extensions to the Analogix Display Port PHY 2 ------------------------------------ 5 - compatible : should be one of the following supported values: 6 - "rockchip.rk3288-dp-phy" 7 - clocks: from common clock binding: handle to dp clock. 9 - clock-names: from common clock binding: 10 Required elements: "24m" 11 - #phy-cells : from the generic PHY bindings, must be 0; 16 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; 20 edp_phy: edp-phy { [all …]
|
/freebsd-src/tools/tools/net80211/wlantxtime/ |
H A D | wlantxtime.c | 1 /*- 2 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting 28 * IEEE 802.11 PHY-related support. 51 uint8_t phy; /* CCK/OFDM/TURBO */ member 72 exit(-1); \ 84 exit(-1); in panic() 102 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },/* 1 Mb */ 103 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },/* 2 Mb */ 104 [2] = { .phy = CCK, 5500, 0x04, B(11), 1 },/* 5.5 Mb */ 105 [3] = { .phy = CCK, 11000, 0x04, B(22), 1 },/* 11 Mb */ [all …]
|
/freebsd-src/sys/contrib/device-tree/Bindings/net/ |
H A D | nvidia,tegra234-mgbe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller 10 - Thierry Reding <treding@nvidia.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 const: nvidia,tegra234-mgbe 20 reg-names: 22 - const: hypervisor [all …]
|
H A D | sunplus,sp7021-emac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/net/sunplus,sp7021-emac.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Wells Lu <wellslutw@gmail.com> 14 Sunplus SP7021 dual 10M/100M Ethernet MAC controller. 19 const: sunplus,sp7021-emac 33 ethernet-ports: 36 description: Ethernet ports to PHY 39 "#address-cells": [all …]
|
H A D | qca,ar803x.yaml | 1 # SPDX-License-Identifier: GPL-2.0+ 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Atheros AR803x PHY 10 - Andrew Lunn <andrew@lunn.ch> 11 - Florian Fainelli <f.fainelli@gmail.com> 12 - Heiner Kallweit <hkallweit1@gmail.com> 18 - $ref: ethernet-phy.yaml# 21 qca,clk-out-frequency: 26 qca,clk-out-strength: [all …]
|
/freebsd-src/sys/contrib/dev/mediatek/mt76/mt7915/ |
H A D | debugfs.c | 1 // SPDX-License-Identifier: ISC 29 dev->ibf = !!val; in mt7915_implicit_txbf_set() 39 *val = dev->ibf; in mt7915_implicit_txbf_get() 52 struct mt7915_phy *phy = file->private_data; in mt7915_sys_recovery_set() local 53 struct mt7915_dev *dev = phy->dev; in mt7915_sys_recovery_set() 54 bool band = phy->mt76->band_idx; in mt7915_sys_recovery_set() 60 return -EINVAL; in mt7915_sys_recovery_set() 63 return -EFAULT; in mt7915_sys_recovery_set() 65 if (count && buf[count - 1] == '\n') in mt7915_sys_recovery_set() 66 buf[count - 1] = '\0'; in mt7915_sys_recovery_set() [all …]
|
/freebsd-src/sys/dev/usb/net/ |
H A D | if_udav.c | 3 /*- 4 * SPDX-License-Identifier: BSD-3-Clause 17 * 3. Neither the name of the author nor the names of any co-contributors 36 * DM9601(DAVICOM USB to Ethernet MAC Controller with Integrated 10/100 PHY) 38 * http://ptm2.cc.utu.fi/ftp/network/cards/DM9601/From_NET/DM9601-DS-P01-930914.pdf 175 /* Corega USB-TXC */ 239 udav_csr_read(sc, UDAV_PAR, ue->ue_eaddr, ETHER_ADDR_LEN); in udav_attach_post() 247 if (uaa->usb_mode != USB_MODE_HOST) in udav_probe() 249 if (uaa->info.bConfigIndex != UDAV_CONFIG_INDEX) in udav_probe() 251 if (uaa->info.bIfaceIndex != UDAV_IFACE_INDEX) in udav_probe() [all …]
|
H A D | if_aue.c | 1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 21 * 4. Neither the name of the author nor the names of any co-contributors 57 * the station address and a 64-bit multicast hash table. The chip supports 64 * the controller uses an external PHY chip, it's possible that board 65 * designers might simply choose a 10Mbps PHY. 319 err = uether_do_request(&sc->sc_ue, &req, &val, 1000); in aue_csr_read_1() 338 err = uether_do_request(&sc->sc_ue, &req, &val, 1000); in aue_csr_read_2() 356 if (uether_do_request(&sc->sc_ue, &req, &val, 1000)) { in aue_csr_write_1() 374 if (uether_do_request(&sc->sc_ue, &req, &val, 1000)) { in aue_csr_write_2() [all …]
|
H A D | if_axe.c | 1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 4 * Copyright (c) 1997, 1998, 1999, 2000-2003 18 * 4. Neither the name of the author nor the names of any co-contributors 53 * It uses an external PHY (reference designs use a RealTek chip), 54 * and has a 64-bit multicast hash filter. There is some information 58 * - You must set bit 7 in the RX control register, otherwise the 60 * - You must initialize all 3 IPG registers, or you won't be able 313 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); in axe_cmd() 319 axe_miibus_readreg(device_t dev, int phy, int reg) in axe_miibus_readreg() argument [all …]
|
/freebsd-src/sys/contrib/device-tree/src/arm64/nvidia/ |
H A D | tegra234-p3768-0000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 compatible = "nvidia,p3768-0000"; 11 stdout-path = "serial0:115200n8"; 23 vcc-supply = <&vdd_1v8_sys>; 24 address-width = <8>; 27 read-only; 32 current-speed = <115200>; 37 assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>; 38 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 48 usb2-0 { [all …]
|
/freebsd-src/sys/contrib/device-tree/src/riscv/microchip/ |
H A D | mpfs-tysom-m.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 * Original all-in-one devicetree: 4 * Copyright (C) 2020-2022 - Aldec 6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com> 9 /dts-v1/; 12 #include "mpfs-tysom-m-fabric.dtsi" 15 model = "Aldec TySOM-M-MPFS250T-REV2"; 16 compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs"; 31 stdout-path = "serial1:115200n8"; 47 compatible = "gpio-leds"; [all …]
|
/freebsd-src/sys/dev/cxgb/ |
H A D | cxgb_main.c | 2 SPDX-License-Identifier: BSD-2-Clause 4 Copyright (c) 2007-2009, Chelsio Inc. 153 {PCI_VENDOR_ID_CHELSIO, 0x0036, 3, "S320E-CR"}, 154 {PCI_VENDOR_ID_CHELSIO, 0x0037, 7, "N320E-G2"}, 176 nitems(cxgb_identifiers) - 1); 228 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which 240 "MSI- 1332 struct mbuf *m; init_tp_parity() local 1442 struct mbuf *m; send_pktsched_cmd() local 2093 struct cphy *phy = &p->phy; cxgb_build_medialist() local 2096 int m = IFM_ETHER | IFM_FDX; cxgb_build_medialist() local 2550 struct cphy *phy = &pi->phy; cxgb_extension_ioctl() local 2572 struct cphy *phy = &pi->phy; cxgb_extension_ioctl() local 2741 struct ch_pm *m = (struct ch_pm *)data; cxgb_extension_ioctl() local 2756 struct ch_pm *m = (struct ch_pm *)data; cxgb_extension_ioctl() local 2788 struct ch_mtus *m = (struct ch_mtus *)data; cxgb_extension_ioctl() local 2811 struct ch_mtus *m = (struct ch_mtus *)data; cxgb_extension_ioctl() local 3270 struct mbuf *m; set_filter() local 3522 cpl_not_handled(struct sge_qset * qs __unused,struct rsp_desc * r __unused,struct mbuf * m) cpl_not_handled() argument 3620 cxgb_debugnet_transmit(if_t ifp,struct mbuf * m) cxgb_debugnet_transmit() argument [all...] |
/freebsd-src/sys/arm/allwinner/ |
H A D | if_awg.c | 1 /*- 71 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg)) 72 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val)) 74 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx) 75 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx); 76 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 77 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 86 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 87 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 88 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 231 awg_miibus_readreg(device_t dev,int phy,int reg) awg_miibus_readreg() argument 260 awg_miibus_writereg(device_t dev,int phy,int reg,int val) awg_miibus_writereg() argument 607 struct mbuf *m; awg_encap() local 744 struct mbuf *m; awg_newbuf_rx() local 958 struct mbuf *m; awg_start_locked() local 1190 struct mbuf *m, *mh, *mt; awg_rxintr() local [all...] |
H A D | aw_usbphy.c | 1 /*- 27 * Allwinner USB PHY 46 #include <dev/phy/phy_usb.h> 133 { "allwinner,sun4i-a10-usb-phy", (uintptr_t)&a10_usbphy_conf }, 134 { "allwinner,sun5i-a13-usb-ph 164 CLR4(res,o,m) global() argument 165 SET4(res,o,m) global() argument 336 intptr_t phy; awusbphy_phy_enable() local 405 intptr_t phy; awusbphy_set_mode() local [all...] |
/freebsd-src/sys/dev/bwn/ |
H A D | if_bwn.c | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org> 544 sc->sc_dev = dev; in bwn_attach() 546 sc->sc_debug = bwn_debug; in bwn_attach() 553 sc->sc_quirks = bhnd_device_quirks(dev, bwn_devices, in bwn_attach() 558 sc->sc_quirk in bwn_attach() 956 bwn_transmit(struct ieee80211com * ic,struct mbuf * m) bwn_transmit() argument 983 struct mbuf *m; bwn_start() local 1026 bwn_tx_isfull(struct bwn_softc * sc,struct mbuf * m) bwn_tx_isfull() argument 1055 bwn_tx_start(struct bwn_softc * sc,struct ieee80211_node * ni,struct mbuf * m) bwn_tx_start() argument 1084 struct mbuf *m, *m_new; bwn_pio_tx_start() local 1182 struct mbuf *m; bwn_dma_tx_start() local 1562 struct bwn_phy *phy = &mac->mac_phy; bwn_phy_getinfo() local 1822 bwn_raw_xmit(struct ieee80211_node * ni,struct mbuf * m,const struct ieee80211_bpf_params * params) bwn_raw_xmit() argument 1961 struct bwn_phy *phy = &mac->mac_phy; bwn_set_channel() local 2397 struct bwn_phy *phy = &mac->mac_phy; bwn_chip_init() local 3513 bwn_dma_set_redzone(struct bwn_dma_ring * dr,struct mbuf * m) bwn_dma_set_redzone() argument 3529 bwn_dma_check_redzone(struct bwn_dma_ring * dr,struct mbuf * m) bwn_dma_check_redzone() argument 3839 struct bwn_phy *phy = &mac->mac_phy; bwn_dummy_transmission() local 4551 struct bwn_phy *phy = &(mac->mac_phy); bwn_switch_channel() local 5567 struct mbuf *m; bwn_dma_rxeof() local 5672 struct mbuf *m; bwn_pio_rxeof() local 5803 struct mbuf *m; bwn_dma_newbuf() local 5925 struct bwn_phy *phy = &mac->mac_phy; bwn_rx_rssi_calc() local 5974 bwn_rxeof(struct bwn_mac * mac,struct mbuf * m,const void * _rxhdr) bwn_rxeof() argument 6226 struct bwn_phy *phy = &mac->mac_phy; bwn_phy_txpower_check() local 6322 struct bwn_phy *phy = &mac->mac_phy; bwn_set_txhdr_phyctl1() local 6392 bwn_set_txhdr(struct bwn_mac * mac,struct ieee80211_node * ni,struct mbuf * m,struct bwn_txhdr * txhdr,uint16_t cookie) bwn_set_txhdr() argument 6394 const struct bwn_phy *phy = &mac->mac_phy; bwn_set_txhdr() local 6817 struct mbuf *m = m0; bwn_pio_write_mbuf_2() local 7063 bwn_rx_radiotap(struct bwn_mac * mac,struct mbuf * m,const struct bwn_rxhdr4 * rxhdr,struct bwn_plcp6 * plcp,int rate,int rssi,int noise) bwn_rx_radiotap() argument [all...] |
/freebsd-src/sys/contrib/device-tree/src/mips/ralink/ |
H A D | mt7621.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 #include <dt-bindings/interrupt-controller/mips-gic.h> 3 #include <dt-binding [all...] |
/freebsd-src/sys/contrib/device-tree/Bindings/ufs/ |
H A D | ufs-mediatek.txt | 3 UFS nodes are defined to describe on-chip UFS hardware macro. 6 To bind UFS PHY with UFS host controller, the controller node should 7 contain a phandle reference to UFS M-PHY node. 10 - compatible : Compatible list, contains the following controller: 11 "mediatek,mt8183-ufshci" for MediaTek UFS host controller 13 "mediatek,mt8192-ufshci" for MediaTek UFS host controller 15 - reg : Address and length of the UFS register set. 16 - phys : phandle to m-phy. 17 - clocks : List of phandle and clock specifier pairs. 18 - clock-names : List of clock input name strings sorted in the same [all …]
|