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/llvm-project/openmp/runtime/test/parallel/
H A D	omp_parallel_num_threads_list.c	22 // Initially, 5 levels specified via OMP_NUM_THREADS with 2 threads per level in test_omp_parallel_num_threads_list() 24 #pragma omp parallel reduction(+ : num_failed) // 1st level in test_omp_parallel_num_threads_list() 28 #pragma omp parallel reduction(+ : num_failed) // 2nd level in test_omp_parallel_num_threads_list() 32 #pragma omp parallel reduction(+ : num_failed) // 3rd level in test_omp_parallel_num_threads_list() 36 } // end 3rd level parallel in test_omp_parallel_num_threads_list() 37 } // end 2nd level parallel in test_omp_parallel_num_threads_list() 38 } // end 1st level parallel in test_omp_parallel_num_threads_list() 41 #pragma omp parallel reduction(+ : num_failed) num_threads(4) // 1st level in test_omp_parallel_num_threads_list() 45 #pragma omp parallel reduction(+ : num_failed) // 2nd level in test_omp_parallel_num_threads_list() 49 #pragma omp parallel reduction(+ : num_failed) // 3rd level in test_omp_parallel_num_threads_list() [all …]
/llvm-project/polly/lib/External/isl/
H A D	isl_scan.c	89 * We basically perform a depth first search, where in each level i 94 * in turn and then continue to the next level. 96 * The search is implemented iteratively. "level" identifies the current 98 * level and false if we want the next value. 111 int level; in isl_basic_set_scan() local 146 level = 0; in isl_basic_set_scan() 149 while (level >= 0) { in isl_basic_set_scan() 152 res = isl_tab_min(tab, B->row[1 + level], in isl_basic_set_scan() 153 bset->ctx->one, &min->el[level], NULL, 0); in isl_basic_set_scan() 158 isl_seq_neg(B->row[1 + level] + 1, in isl_basic_set_scan() [all …]
/llvm-project/clang/include/clang/Frontend/
H A D	DiagnosticRenderer.h	65 /// The level of the last diagnostic emitted. 67 /// The level of the last diagnostic emitted. Used to detect level changes 69 DiagnosticsEngine::Level LastLevel = DiagnosticsEngine::Ignored; 77 DiagnosticsEngine::Level Level, 83 DiagnosticsEngine::Level Level, 87 DiagnosticsEngine::Level Level, 98 DiagnosticsEngine::Level Level) {} in beginDiagnostic() argument 100 DiagnosticsEngine::Level Level) {} in endDiagnostic() argument 105 DiagnosticsEngine::Level Level); 110 void emitCaret(FullSourceLoc Loc, DiagnosticsEngine::Level Level, [all …]
/llvm-project/clang-tools-extra/test/clang-tidy/checkers/readability/
H A D	function-cognitive-complexity.cpp	82 // CHECK-NOTES: :[[@LINE-1]]:3: note: +1, including nesting penalty of 0, nesting level increased to 1{{$}} in unittest_b1_00() 83 // CHECK-NOTES: :[[@LINE-2]]:9: note: +1, including nesting penalty of 0, nesting level increased to 1{{$}} in unittest_b1_00() 86 // CHECK-NOTES: :[[@LINE-1]]:5: note: +2, including nesting penalty of 1, nesting level increased to 2{{$}} in unittest_b1_00() 87 // CHECK-NOTES: :[[@LINE-2]]:11: note: +2, including nesting penalty of 1, nesting level increased to 2{{$}} in unittest_b1_00() 89 // CHECK-NOTES: :[[@LINE-1]]:12: note: +1, nesting level increased to 2{{$}} in unittest_b1_00() 90 // CHECK-NOTES: :[[@LINE-2]]:18: note: +3, including nesting penalty of 2, nesting level increased to 3{{$}} in unittest_b1_00() 92 // CHECK-NOTES: :[[@LINE-1]]:7: note: +1, nesting level increased to 2{{$}} in unittest_b1_00() 95 // CHECK-NOTES: :[[@LINE-1]]:10: note: +1, nesting level increased to 1{{$}} in unittest_b1_00() 96 // CHECK-NOTES: :[[@LINE-2]]:16: note: +2, including nesting penalty of 1, nesting level increased to 2{{$}} in unittest_b1_00() 99 // CHECK-NOTES: :[[@LINE-1]]:5: note: +2, including nesting penalty of 1, nesting level increase in unittest_b1_00() [all...]
/llvm-project/lldb/test/API/functionalities/data-formatter/data-formatter-skip-summary/
H A D	TestDataFormatterSkipSummary.py	57 self.runCmd('type summary add --summary-string "Level 1" "DeepData_1"') 58 self.runCmd('type summary add --summary-string "Level 2" "DeepData_2" -e') 59 self.runCmd('type summary add --summary-string "Level 3" "DeepData_3"') 60 self.runCmd('type summary add --summary-string "Level 4" "DeepData_4"') 61 self.runCmd('type summary add --summary-string "Level 5" "DeepData_5"') 67 "(DeepData_1) data1 = Level 1", 68 "(DeepData_2) data2 = Level 2 {", 69 "m_child1 = Level 3", 70 "m_child2 = Level 3", 71 "m_child3 = Level [all...]
/llvm-project/clang/test/CodeGenObjC/
H A D	local-static-block.m	10 … (^ArrayRecurs)(NSArray addresses, unsigned long level) = ^(NSArray addresses, unsigned long le… 15 separatedAddresses = ArrayRecurs((NSArray )rawAddress, level+1); 21 extern unsigned long level; 25 ArrayRecurs(address, level); 27 … (^ArrayRecurs)(NSArray addresses, unsigned long level) = ^(NSArray addresses, unsigned long le… 32 separatedAddresses = ArrayRecurs((NSArray )rawAddress, level+1); 36 ArrayRecurs(address, level); 39 … (^ArrayRecurs)(NSArray addresses, unsigned long level) = ^(NSArray addresses, unsigned long le… 44 separatedAddresses = ArrayRecurs((NSArray )rawAddress, level+1); 48 ArrayRecurs(address, level); [all …]
/llvm-project/clang-tools-extra/test/clang-tidy/checkers/android/
H A D	comparison-in-temp-failure-retry.c	22 …// CHECK-MESSAGES: :[[@LINE-1]]:28: warning: top-level comparison in TEMP_FAILURE_RETRY [android-c… in test() 24 // CHECK-MESSAGES: :[[@LINE-1]]:29: warning: top-level comparison in TEMP_FAILURE_RETRY in test() 26 // CHECK-MESSAGES: :[[@LINE-1]]:34: warning: top-level comparison in TEMP_FAILURE_RETRY in test() 31 // CHECK-MESSAGES: :[[@LINE-1]]:40: warning: top-level comparison in TEMP_FAILURE_RETRY in test() 33 // CHECK-MESSAGES: :[[@LINE-1]]:41: warning: top-level comparison in TEMP_FAILURE_RETRY in test() 35 // CHECK-MESSAGES: :[[@LINE-1]]:46: warning: top-level comparison in TEMP_FAILURE_RETRY in test() 40 // CHECK-MESSAGES: :[[@LINE-1]]:19: warning: top-level comparison in TEMP_FAILURE_RETRY in test() 43 // CHECK-MESSAGES: :[[@LINE-1]]:36: warning: top-level comparison in TEMP_FAILURE_RETRY in test() 48 // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: top-level comparison in TEMP_FAILURE_RETRY in test() 51 // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: top-level comparison in TEMP_FAILURE_RETRY in test() [all …]
/llvm-project/llvm/test/MC/Mips/mips3/
H A D	invalid-mips4.s	8 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 9 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 31 …$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 32 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 33 …$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 34 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 35 …$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 36 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 37 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 38 …$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
H A D	invalid-mips5.s	9 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 10 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 43 …$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 44 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 45 …$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 46 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 47 …$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 48 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 49 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 50 …$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
/llvm-project/llvm/lib/Passes/
H A D	PassBuilderPipelines.cpp	219 // independent of the opt level and exposed through the frontend. 222 cl::desc("Enable loop header duplication at any optimization level")); 334 OptimizationLevel Level) { in invokeLateLoopOptimizationsEPCallbacks() argument 336 C(FPM, Level); in invokeLateLoopOptimizationsEPCallbacks() 339 LoopPassManager &LPM, OptimizationLevel Level) { in invokeLoopOptimizerEndEPCallbacks() argument 341 C(LPM, Level); in invokeLoopOptimizerEndEPCallbacks() 344 OptimizationLevel Level) { in invokeScalarOptimizerLateEPCallbacks() argument 346 C(LPM, Level); in invokeScalarOptimizerLateEPCallbacks() 349 FunctionPassManager &FPM, OptimizationLevel Level) { in invokeCGSCCOptimizerLateEPCallbacks() argument 351 C(FPM, Level); in invokeCGSCCOptimizerLateEPCallbacks() 329 invokePeepholeEPCallbacks(FunctionPassManager & FPM,OptimizationLevel Level) invokePeepholeEPCallbacks() argument 354 invokeVectorizerStartEPCallbacks(FunctionPassManager & FPM,OptimizationLevel Level) invokeVectorizerStartEPCallbacks() argument 359 invokeOptimizerEarlyEPCallbacks(ModulePassManager & MPM,OptimizationLevel Level) invokeOptimizerEarlyEPCallbacks() argument 364 invokeOptimizerLastEPCallbacks(ModulePassManager & MPM,OptimizationLevel Level) invokeOptimizerLastEPCallbacks() argument 369 invokeFullLinkTimeOptimizationEarlyEPCallbacks(ModulePassManager & MPM,OptimizationLevel Level) invokeFullLinkTimeOptimizationEarlyEPCallbacks() argument 374 invokeFullLinkTimeOptimizationLastEPCallbacks(ModulePassManager & MPM,OptimizationLevel Level) invokeFullLinkTimeOptimizationLastEPCallbacks() argument 379 invokePipelineStartEPCallbacks(ModulePassManager & MPM,OptimizationLevel Level) invokePipelineStartEPCallbacks() argument 384 invokePipelineEarlySimplificationEPCallbacks(ModulePassManager & MPM,OptimizationLevel Level) invokePipelineEarlySimplificationEPCallbacks() argument 402 buildO1FunctionSimplificationPipeline(OptimizationLevel Level,ThinOrFullLTOPhase Phase) buildO1FunctionSimplificationPipeline() argument 542 buildFunctionSimplificationPipeline(OptimizationLevel Level,ThinOrFullLTOPhase Phase) buildFunctionSimplificationPipeline() argument 769 addPreInlinerPasses(ModulePassManager & MPM,OptimizationLevel Level,ThinOrFullLTOPhase LTOPhase) addPreInlinerPasses() argument 808 addPostPGOLoopRotation(ModulePassManager & MPM,OptimizationLevel Level) addPostPGOLoopRotation() argument 822 addPGOInstrPasses(ModulePassManager & MPM,OptimizationLevel Level,bool RunProfileGen,bool IsCS,bool AtomicCounterUpdate,std::string ProfileFile,std::string ProfileRemappingFile,IntrusiveRefCntPtr<vfs::FileSystem> FS) addPGOInstrPasses() argument 881 getInlineParamsFromOptLevel(OptimizationLevel Level) getInlineParamsFromOptLevel() argument 886 buildInlinerPipeline(OptimizationLevel Level,ThinOrFullLTOPhase Phase) buildInlinerPipeline() argument 982 buildModuleInlinerPipeline(OptimizationLevel Level,ThinOrFullLTOPhase Phase) buildModuleInlinerPipeline() argument 1021 buildModuleSimplificationPipeline(OptimizationLevel Level,ThinOrFullLTOPhase Phase) buildModuleSimplificationPipeline() argument 1221 addVectorPasses(OptimizationLevel Level,FunctionPassManager & FPM,bool IsFullLTO) addVectorPasses() argument 1366 buildModuleOptimizationPipeline(OptimizationLevel Level,ThinOrFullLTOPhase LTOPhase) buildModuleOptimizationPipeline() argument 1556 buildPerModuleDefaultPipeline(OptimizationLevel Level,bool LTOPreLink) buildPerModuleDefaultPipeline() argument 1597 buildFatLTODefaultPipeline(OptimizationLevel Level,bool ThinLTO,bool EmitSummary) buildFatLTODefaultPipeline() argument 1620 buildThinLTOPreLinkDefaultPipeline(OptimizationLevel Level) buildThinLTOPreLinkDefaultPipeline() argument 1673 buildThinLTODefaultPipeline(OptimizationLevel Level,const ModuleSummaryIndex * ImportSummary) buildThinLTODefaultPipeline() argument 1728 buildLTOPreLinkDefaultPipeline(OptimizationLevel Level) buildLTOPreLinkDefaultPipeline() argument 1735 buildLTODefaultPipeline(OptimizationLevel Level,ModuleSummaryIndex * ExportSummary) buildLTODefaultPipeline() argument 2052 buildO0DefaultPipeline(OptimizationLevel Level,bool LTOPreLink) buildO0DefaultPipeline() argument [all...]
/llvm-project/llvm/test/MC/Mips/mips1/
H A D	invalid-mips5-wrong-error.s	37 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 38 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 39 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 40 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 41 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 42 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 43 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 44 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 45 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 46 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
/llvm-project/llvm/utils/lit/tests/
H A D	xfail-cl.py	3 # RUN: %{lit} --xfail 'false.txt;false2.txt;top-level-suite :: b :: test.txt' \ 4 # RUN: --xfail-not 'true-xfail.txt;top-level-suite :: a :: test-xfail.txt' \ 8 # RUN: env LIT_XFAIL='false.txt;false2.txt;top-level-suite :: b :: test.txt' \ 9 # RUN: LIT_XFAIL_NOT='true-xfail.txt;top-level-suite :: a :: test-xfail.txt' \ 27 # CHECK-FILTER-DAG: {{^}}PASS: top-level-suite :: a :: test.txt 28 # CHECK-FILTER-DAG: {{^}}XFAIL: top-level-suite :: b :: test.txt 29 # CHECK-FILTER-DAG: {{^}}XFAIL: top-level-suite :: a :: false.txt 30 # CHECK-FILTER-DAG: {{^}}XFAIL: top-level-suite :: b :: false.txt 31 # CHECK-FILTER-DAG: {{^}}XFAIL: top-level-suite :: false.txt 32 # CHECK-FILTER-DAG: {{^}}XFAIL: top-level-suite :: false2.txt [all …]
/llvm-project/llvm/test/MC/Mips/mips2/
H A D	invalid-mips32.s	8 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 9 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 46 …$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 47 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 48 …$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 49 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 50 …$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 51 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 52 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 53 …$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
H A D	invalid-mips32r2.s	8 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 9 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 14 …8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 15 …7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 16 …4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 17 …6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 18 …8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 19 …6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 20 …6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 21 …2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
/llvm-project/mlir/include/mlir/Tools/lsp-server-support/
H A D	Logging.h	25 /// The level of significance for a log message. 26 enum class Level { Debug, Info, Error }; enum 28 /// Set the severity level of the logger. 29 static void setLogLevel(Level logLevel); 35 log(Level::Debug, fmt, llvm::formatv(fmt, std::forward<Ts>(vals)...)); in debug() 39 log(Level::Info, fmt, llvm::formatv(fmt, std::forward<Ts>(vals)...)); in info() 43 log(Level::Error, fmt, llvm::formatv(fmt, std::forward<Ts>(vals)...)); in error() 52 /// Start a log message with the given severity level. 53 static void log(Level logLevel, const char *fmt, 56 /// The minimum logging level. Messages with lower level are ignored. [all …]
/llvm-project/libcxx/test/libcxx/
H A D	transitive_includes_to_csv.py
/llvm-project/flang/test/Driver/
H A D	pic-flags.f90	24 ! CHECK-STATIC-IR-NOT: {{PIE\|PIC}} Level 28 ! CHECK-PIC-LEVEL1: -mrelocation-model pic -pic-level 1 31 ! CHECK-PIC-LEVEL1-IR-NOT: "PIE Level" 32 ! CHECK-PIC-LEVEL1-IR: !"PIC Level", i32 1} 33 ! CHECK-PIC-LEVEL1-IR-NOT: "PIE Level" 37 ! CHECK-PIC-LEVEL2: -mrelocation-model pic -pic-level 2 40 ! CHECK-PIC-LEVEL2-IR-NOT: "PIE Level" 41 ! CHECK-PIC-LEVEL2-IR: !"PIC Level", i32 2} 42 ! CHECK-PIC-LEVEL2-IR-NOT: "PIE Level" 46 ! CHECK-PIE-LEVEL1: -mrelocation-model pic -pic-level 1 -pic-is-pie [all …]
/llvm-project/openmp/runtime/test/ompt/parallel/
H A D	nested_lwt.c	81 // THREADS: {{^}}[[MASTER_ID]]: task level 0: parallel_id=[[PARALLEL_ID]], task_id=[[IMPLICIT_TASK_ID]], exit_frame=[[NESTED_TASK_FRAME_EXIT:0x[0-f]+]], reenter_frame=[[NULL]] in main() 82 // THREADS: {{^}}[[MASTER_ID]]: task level 1: parallel_id=[[IMPLICIT_PARALLEL_ID:[0-9]+]], task_id=[[PARENT_TASK_ID]], exit_frame=[[NULL]], reenter_frame=[[TASK_FRAME_ENTER]] in main() 86 // THREADS: {{^}}[[MASTER_ID]]: task level 0: parallel_id=[[NESTED_PARALLEL_ID]], task_id=[[NESTED_IMPLICIT_TASK_ID]], exit_frame=[[NESTED_NESTED_TASK_FRAME_EXIT:0x[0-f]+]], reenter_frame=[[NULL]] in main() 87 // THREADS: {{^}}[[MASTER_ID]]: task level 1: parallel_id=[[PARALLEL_ID]], task_id=[[IMPLICIT_TASK_ID]], exit_frame=[[NESTED_TASK_FRAME_EXIT]], reenter_frame=[[NESTED_TASK_FRAME_ENTER]] in main() 88 // THREADS: {{^}}[[MASTER_ID]]: task level 2: parallel_id=[[IMPLICIT_PARALLEL_ID]], task_id=[[PARENT_TASK_ID]], exit_frame=[[NULL]], reenter_frame=[[TASK_FRAME_ENTER]] in main() 92 // THREADS: {{^}}[[MASTER_ID]]: task level 0: parallel_id=[[NESTED_NESTED_PARALLEL_ID]], task_id=[[NESTED_NESTED_IMPLICIT_TASK_ID]], exit_frame=[[NESTED_NESTED_NESTED_TASK_FRAME_EXIT:0x[0-f]+]], reenter_frame=[[NULL]] in main() 93 // THREADS: {{^}}[[MASTER_ID]]: task level 1: parallel_id=[[NESTED_PARALLEL_ID]], task_id=[[NESTED_IMPLICIT_TASK_ID]], exit_frame=[[NESTED_NESTED_TASK_FRAME_EXIT]], reenter_frame=[[NESTED_NESTED_TASK_FRAME_ENTER]] in main() 94 // THREADS: {{^}}[[MASTER_ID]]: task level 2: parallel_id=[[PARALLEL_ID]], task_id=[[IMPLICIT_TASK_ID]], exit_frame=[[NESTED_TASK_FRAME_EXIT]], reenter_frame=[[NESTED_TASK_FRAME_ENTER]] in main() 95 // THREADS: {{^}}[[MASTER_ID]]: task level 3: parallel_id=[[IMPLICIT_PARALLEL_ID]], task_id=[[PARENT_TASK_ID]], exit_frame=[[NULL]], reenter_frame=[[TASK_FRAME_ENTER]] in main() 114 // THREADS: {{^}}[[THREAD_ID]]: task level in main() [all...]
H A D	nested.c	88 // THREADS: {{^}}[[MASTER_ID]]: task level 0: parallel_id=[[PARALLEL_ID]], task_id=[[IMPLICIT_TASK_ID]], exit_frame=[[EXIT]], reenter_frame=[[NULL]] in main() 89 // THREADS: {{^}}[[MASTER_ID]]: task level 1: parallel_id=[[IMPLICIT_PARALLEL_ID:[0-9]+]], task_id=[[PARENT_TASK_ID]], exit_frame=[[NULL]], reenter_frame=0x{{[0-f]+}} in main() 94 // THREADS: {{^}}[[MASTER_ID]]: task level 0: parallel_id=[[NESTED_PARALLEL_ID]], task_id=[[NESTED_IMPLICIT_TASK_ID]], exit_frame=[[NESTED_EXIT]], reenter_frame=[[NULL]] in main() 95 // THREADS: {{^}}[[MASTER_ID]]: task level 1: parallel_id=[[PARALLEL_ID]], task_id=[[IMPLICIT_TASK_ID]], exit_frame=[[EXIT]], reenter_frame=0x{{[0-f]+}} in main() 96 // THREADS: {{^}}[[MASTER_ID]]: task level 2: parallel_id=[[IMPLICIT_PARALLEL_ID]], task_id=[[PARENT_TASK_ID]], exit_frame=[[NULL]], reenter_frame=0x{{[0-f]+}} in main() 101 // THREADS: {{^}}[[MASTER_ID]]: task level 0: parallel_id=[[NESTED_PARALLEL_ID]], task_id=[[NESTED_IMPLICIT_TASK_ID]], exit_frame=[[NESTED_EXIT]], reenter_frame=0x{{[0-f]+}} in main() 104 // THREADS: {{^}}[[MASTER_ID]]: task level 0: parallel_id=[[NESTED_PARALLEL_ID]], task_id=[[NESTED_IMPLICIT_TASK_ID]], exit_frame=[[NESTED_EXIT]], reenter_frame=[[NULL]] in main() 107 // THREADS: {{^}}[[MASTER_ID]]: task level 0: parallel_id=[[NESTED_PARALLEL_ID]], task_id=[[NESTED_IMPLICIT_TASK_ID]], exit_frame=[[NULL]], reenter_frame=[[NULL]] in main() 113 // THREADS: {{^}}[[MASTER_ID]]: task level 0: parallel_id=[[PARALLEL_ID]], task_id=[[IMPLICIT_TASK_ID]], exit_frame=[[EXIT]], reenter_frame=[[NULL]] in main() 116 // THREADS: {{^}}[[MASTER_ID]]: task level in main() [all...]
/llvm-project/llvm/lib/Support/
H A D	IntervalMap.cpp	25 NodeRef Path::getLeftSibling(unsigned Level) const { in getLeftSibling() 27 if (Level == 0) in getLeftSibling() 31 unsigned l = Level - 1; in getLeftSibling() 43 for (++l; l != Level; ++l) in getLeftSibling() 48 void Path::moveLeft(unsigned Level) { in moveLeft() argument 49 assert(Level != 0 && "Cannot move the root node"); in moveLeft() 54 l = Level - 1; in moveLeft() 59 } else if (height() < Level) in moveLeft() 61 path.resize(Level + 1, Entry(nullptr, 0, 0)); in moveLeft() 68 for (++l; l != Level; ++l) { in moveLeft() [all …]
/llvm-project/mlir/include/mlir/Dialect/SparseTensor/IR/
H A D	SparseTensorAttrDefs.td	40 // the index refers to a dimension (an axis of the semantic tensor) or a level 61 "level attribute"> { 62 let returnType = [{::mlir::sparse_tensor::Level}]; 129 and level to refer to the axes of the actual storage format, i.e., the 134 (for example, to linearize dimensions as a single level in the storage). 141 - An ordered sequence of level specifications, each of which includes a required 142 level-type, which defines how the level should be stored. Each level-type 144 - a **level [all...]
H A D	SparseTensorType.h	25 /// types; in particular, to make the "dimension" vs "level" distinction 29 /// the "dimension" vs "level" distinction overt. 36 /// "dimension" vs "level" distinction overt, and to avoid needing to 183 /// Returns true for tensors where every level is dense. 187 /// Returns true for tensors where every level is ordered. 191 /// Translates between level / dimension coordinate space. 241 /// Returns the level-rank. 242 Level getLvlRank() const { return lvlRank; } in getLvlRank() 247 /// Returns the level-shape. 253 /// Returns the batched level [all...]
/llvm-project/flang/test/Semantics/
H A D	get_team.f90	18 !___ standard-conforming statements with optional level argument present ___ 29 result_team = get_team(level=initial_team) 30 result_team = get_team(level=n) 33 !ERROR: 'level=' argument has unacceptable rank 1 36 !ERROR: Actual argument for 'level=' has bad type 'LOGICAL(4)' 39 !ERROR: Actual argument for 'level=' has bad type 'REAL(4)' 45 !ERROR: Actual argument for 'level=' has bad type 'REAL(4)' 46 result_team = get_team(level=3.4) 52 result_team = get_team(level=initial_team, level [all...]
/llvm-project/clang/lib/Analysis/FlowSensitive/
H A D	WatchedLiteralsSolver.cpp	58 /// (inclusive). The current level is stored in `Level`. At each level the 60 /// consistent partial assignment, `Level` will be incremented. Otherwise, if 62 /// `Level` until it reaches the most recent level where a decision was made. 63 size_t Level = 0; member in clang::dataflow::__anond292cd9c0111::WatchedLiteralsSolverImpl 72 /// State of the solver at a particular level. 81 /// State of the solver at a particular level. It keeps track of previous 129 // Initialize the state at the root level to a decision so that in in WatchedLiteralsSolverImpl() 130 // `reverseForcedMoves` we don't have to check that `Level >= 0` on each in WatchedLiteralsSolverImpl() 177 // Backtrack and rewind the `Level` until the most recent non-forced in solve() 181 // If the root level is reached, then all possible assignments lead to in solve() [all …]
/llvm-project/clang/test/Driver/
H A D	attr-availability-fuchsia.c	1 // Test that `-ffuchsia-api-level` is propagated to cc1. 4 // RUN: %clang -target x86_64-unknown-fuchsia -ffuchsia-api-level=16 -c %s -### 2>&1\| FileCheck %s 10 // RUN: %clang -target x86_64-unknown-linux-gnu -ffuchsia-api-level=16 -c %s -### 2>&1 \| FileCheck … 12 // Check Fuchsia API level macro. 13 // RUN: %clang -target x86_64-unknown-fuchsia -ffuchsia-api-level=15 -c %s -o %t 16 // RUN: %clang -target x86_64-unknown-fuchsia -ffuchsia-api-level=16 -c %s -o %t 19 // Check using a non-integer Fuchsia API level. 20 // RUN: not %clang -target x86_64-unknown-fuchsia -ffuchsia-api-level=16.0.0 -c %s 2>&1\| FileCheck… 23 // CHECK: "-ffuchsia-api-level=16" 29 // CHECK-ERROR: error: invalid integral value '16.0.0' in '-ffuchsia-api-level=16.0.0'

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