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/freebsd-src/lib/libpmc/pmu-events/arch/arm64/hisilicon/hip08/
H A D	metrics.json	74 "PublicDescription": "Idle by itlb miss L3 topdown metric", 75 "BriefDescription": "Idle by itlb miss L3 topdown metric", 81 "PublicDescription": "Idle by icache miss L3 topdown metric", 82 "BriefDescription": "Idle by icache miss L3 topdown metric", 88 "PublicDescription": "BP misp flush L3 topdown metric", 89 "BriefDescription": "BP misp flush L3 topdown metric", 95 "PublicDescription": "OOO flush L3 topdown metric", 96 "BriefDescription": "OOO flush L3 topdown metric", 102 "PublicDescription": "Static predictor flush L3 topdown metric", 103 "BriefDescription": "Static predictor flush L3 topdown metric", [all …]
/freebsd-src/sys/contrib/device-tree/Bindings/interconnect/
H A D	qcom,osm-l3.yaml	`4 $id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml# 7 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider 13 L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM. 14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests 22 - qcom,sc7180-osm-l3 23 - qcom,sc8180x-osm-l3 24 - qcom,sdm670-osm-l3 25 - qcom,sdm845-osm-l3 26 - qcom,sm6350-osm-l3 27 - qcom,sm8150-osm-l3 [all …]`
/freebsd-src/lib/libpmc/pmu-events/arch/x86/ivybridge/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", 18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", 23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", 28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 43 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-s… 48 …"PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-… [all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/haswell/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", 18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", 23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", 28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 43 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-s… 48 …"PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-… [all …]
H A D	uncore.json	31 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor c… 32 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor … 67 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line i… 68 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line … 103 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in so… 104 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in s… 115 "BriefDescription": "L3 Lookup read request that access cache and found line in M-state.", 116 "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.", 127 "BriefDescription": "L3 Lookup write request that access cache and found line in M-state.", 128 "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.", [all …]
H A D	memory.json	228 "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", 236 "PublicDescription": "Counts all demand & prefetch code reads miss in the L3", 241 …"BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned … 249 …"PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned… 254 "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", 262 "PublicDescription": "Counts all demand & prefetch data reads miss in the L3", 267 …"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned … 275 …"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned… 280 "BriefDescription": "miss in the L3", 288 "PublicDescription": "miss in the L3", [all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", 18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", 23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", 28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 43 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-s… 48 …"PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-… [all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/tremontx/
H A D	memory.json	36 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 47 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 58 …": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.", 69 …": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.", 80 …d instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.", 91 …d instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.", 102 …are prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.", 113 …are prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.", 146 …d software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 157 …d software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", [all …]
H A D	cache.json	91 …hat miss in the Last Level Cache (LLC). If the platform has an L3 cache, the LLC is the L3 cache, … 103 …struction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, … 221 …"BriefDescription": "Counts the number of retired loads that hit in the L3 cache, in which a snoop… 281 "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.", 378 "BriefDescription": "Counts all code reads that were supplied by the L3 cache.", 389 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 400 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 411 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 422 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 433 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was n… [all …]
/freebsd-src/lib/libc/i386/string/
H A D	strncmp.S	`69 jz L3 71 jne L3 76 * movb n(%eax),%bl; testb %bl, %bl; je L3; cmpb n(%ecx); jne L3 78 * movb n(%eax),%bl; cmpb n(%ecx); jne L3; testb %bl,%bl; je return_0 91 jz L3 93 jne L3 101 jz L3 103 jne L3 111 jz L3 113 jne L3 [all …]`
H A D	strcmp.S	`61 je L3 63 jne L3 68 je L3 70 jne L3 75 je L3 77 jne L3 82 je L3 84 jne L3 89 je L3 91 jne L3 [all …]`
/freebsd-src/lib/libpmc/pmu-events/arch/powerpc/power8/
H A D	cache.json	5 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 6 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 11 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 12 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 65 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand … 66 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either o… 71 "BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)", 77 …sor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load… 78 …sor's data cache was reloaded from a localtion other than the local core's L3 due to either only d… 83 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co… [all …]
H A D	marked.json	35 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 41 …ation in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node … 47 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 53 …uration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node … 155 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked … 161 …sor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load… 167 …"Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load… 173 "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load", 179 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co… 185 …"BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due … [all …]
H A D	frontend.json	89 …uction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 90 …uction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 95 …truction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 96 …truction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 149 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an… 150 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 due to e… 156 "PublicDescription": "Inst from L3 miss" 161 …nstruction cache was reloaded from a localtion other than the local core's L3 due to a instruction… 162 …nstruction cache was reloaded from a localtion other than the local core's L3 due to either an ins… 167 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with disp… [all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/haswellx/
H A D	memory.json	228 "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", 236 "PublicDescription": "Counts all demand & prefetch code reads miss in the L3", 241 …"BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned … 249 …"PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned… 254 "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", 262 "PublicDescription": "Counts all demand & prefetch data reads miss in the L3", 267 …"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned … 275 …"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned… 280 …"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned … 288 …"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned… [all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/skylake/
H A D	uncore.json	19 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor c… 20 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor … 55 "BriefDescription": "L3 Lookup write request that access cache and found line in M-state", 56 "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.", 67 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state", 68 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 79 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state", 80 "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.", 91 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state", 92 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", [all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/broadwell/
H A D	uncore.json	19 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor c… 20 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor … 55 "BriefDescription": "L3 Lookup read request that access cache and found line in M-state", 56 "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.", 67 "BriefDescription": "L3 Lookup write request that access cache and found line in M-state", 68 "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.", 79 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state", 80 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 91 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state", 92 "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.", [all …]
/freebsd-src/lib/libpmc/
H A D	pmc.corei7uc.3	136 has missed the L3. 137 The GQ read tracker L3 miss to fill occupancy count is divided by this count 138 to obtain the average cache line read L3 miss latency. 139 The latency represents the time after which the L3 has determined that the 141 The time between a GQ read tracker allocation and the L3 determining that the 142 cache line has missed is the average L3 hit latency. 143 The total L3 cache line read miss latency is the hit latency + L3 miss 148 tracker queue that hit or miss the L3. 149 The GQ read tracker L3 hit occupancy count is divided by this count to obtain 150 the average L3 hit latency. [all …]
H A D	pmc.westmereuc.3	143 has missed the L3. 144 The GQ read tracker L3 miss to fill occupancy count is divided by this count 145 to obtain the average cache line read L3 miss latency. 146 The latency represents the time after which the L3 has determined that the 148 The time between a GQ read tracker allocation and the L3 determining that 149 the cache line has missed is the average L3 hit latency. 150 The total L3 cache line read miss latency is the hit latency + L3 miss 155 tracker queue that hit or miss the L3. 156 The GQ read tracker L3 hit occupancy count is divided by this count to obtain the average L3 hit la… 160 tracker, have missed in the L3 and have not acquired a Request Transaction ID. [all …]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/omap/
H A D	l3-noc.txt	`1 * TI - L3 Network On Chip (NoC) 7 - compatible : Should be "ti,omap3-l3-smx" for OMAP3 family 8 Should be "ti,omap4-l3-noc" for OMAP4 family 9 Should be "ti,omap5-l3-noc" for OMAP5 family 10 Should be "ti,dra7-l3-noc" for DRA7 family 11 Should be "ti,am4372-l3-noc" for AM43 family 12 - reg: Contains L3 register address range for each noc domain. 18 compatible = "ti,omap4-l3-noc", "simple-bus";`
/freebsd-src/lib/libpmc/pmu-events/arch/x86/skylakex/
H A D	memory.json	3 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 13 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 231 "BriefDescription": "Demand Data Read requests who miss L3 cache", 236 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 241 …"BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the sup… 251 … "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ … 260 …"BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the su… 270 "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.", 282 …"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified dat… 294 …"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared … [all …]
/freebsd-src/lib/libpmc/pmu-events/arch/powerpc/power9/
H A D	other.json	35 "BriefDescription": "L3 initiated LCO received retry on port 2 (can try 4 times)" 45 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load" 50 …try was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due… 120 …"BriefDescription": "L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to … 160 "BriefDescription": "L3 PF from Off chip memory" 190 …"BriefDescription": "TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modifie… 205 …uration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due… 235 … "BriefDescription": "Core TM load hits line in L3 in TM_SC state and causes it to be invalidated" 245 "BriefDescription": "L3 PF sent with nodal scope port 1, counts even retried requests" 260 "BriefDescription": "L3 CO received retry port 3 (memory only), every retry counted" [all …]
H A D	marked.json	10 …ory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The sour… 20 …ble Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due… 50 …Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This imp… 70 …Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due… 85 …Instruction cache was reloaded from a location other than the local core's L3 due to a instruction… 95 …try was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due… 100 …Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due… 110 … "Duration in cycles to reload from a location other than the local core's L3 due to a marked load" 180 …ocessor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due… 185 …essor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due… [all …]
/freebsd-src/sys/arm64/vmm/
H A D	vmm_mmu.c	76 pt_entry_t l3 __diagused; in vmmpmap_release_l3() 80 l3 = (pd_entry_t )PHYS_TO_DMAP(l2e & ~ATTR_MASK); in vmmpmap_release_l3() 82 KASSERT(l3[i] == 0, ("%s: l3 still mapped: %p %lx", __func__, in vmmpmap_release_l3() 83 &l3[i], l3[i])); in vmmpmap_release_l3() 242 pt_entry_t new_l2e, l2e, l2, l3; in vmmpmap_l3_table() local 278 l3 = (pt_entry_t )PHYS_TO_DMAP(l2e & ~ATTR_MASK); in vmmpmap_l3_table() 279 return (l3); in vmmpmap_l3_table() 288 pd_entry_t l3e, l3; in vmmpmap_enter() local 343 pd_entry_t l3, l3e, *l3_list; vmmpmap_remove() local [all...]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/icelakex/
H A D	memory.json	3 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 155 …1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 166 …n cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cache… 177 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 188 … demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cache… 199 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 210 …ership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supp… 221 … prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 232 …(except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cache… 243 …fDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, a… [all …]

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