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/freebsd-src/contrib/wpa/src/l2_packet/
H A Dl2_packet_winpcap.c65 int l2_packet_get_own_addr(struct l2_packet_data *l2, u8 *addr) in l2_packet_get_own_addr() argument
67 os_memcpy(addr, l2->own_addr, ETH_ALEN); in l2_packet_get_own_addr()
72 int l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, in l2_packet_send() argument
78 if (l2 == NULL) in l2_packet_send()
81 if (l2->l2_hdr) { in l2_packet_send()
82 ret = pcap_sendpacket(l2->pcap, buf, len); in l2_packet_send()
90 os_memcpy(eth->h_source, l2->own_addr, ETH_ALEN); in l2_packet_send()
93 ret = pcap_sendpacket(l2->pcap, (u8 *) eth, mlen); in l2_packet_send()
105 struct l2_packet_data *l2 = (struct l2_packet_data *) user; in l2_packet_receive_cb() local
112 if (l2->l2_hdr) { in l2_packet_receive_cb()
[all …]
H A Dl2_packet_pcap.c43 int l2_packet_get_own_addr(struct l2_packet_data *l2, u8 *addr) in l2_packet_get_own_addr() argument
45 os_memcpy(addr, l2->own_addr, ETH_ALEN); in l2_packet_get_own_addr()
51 static int l2_packet_init_libdnet(struct l2_packet_data *l2) in l2_packet_init_libdnet() argument
55 l2->eth = eth_open(l2->ifname); in l2_packet_init_libdnet()
56 if (!l2->eth) { in l2_packet_init_libdnet()
59 l2->ifname, strerror(errno)); in l2_packet_init_libdnet()
63 if (eth_get(l2->eth, &own_addr) < 0) { in l2_packet_init_libdnet()
66 l2->ifname, strerror(errno)); in l2_packet_init_libdnet()
67 eth_close(l2->eth); in l2_packet_init_libdnet()
68 l2->eth = NULL; in l2_packet_init_libdnet()
[all …]
H A Dl2_packet_privsep.c29 static int wpa_priv_cmd(struct l2_packet_data *l2, int cmd, in wpa_priv_cmd() argument
43 msg.msg_name = &l2->priv_addr; in wpa_priv_cmd()
44 msg.msg_namelen = sizeof(l2->priv_addr); in wpa_priv_cmd()
46 if (sendmsg(l2->fd, &msg, 0) < 0) { in wpa_priv_cmd()
47 wpa_printf(MSG_ERROR, "L2: sendmsg(cmd): %s", strerror(errno)); in wpa_priv_cmd()
55 int l2_packet_get_own_addr(struct l2_packet_data *l2, u8 *addr) in l2_packet_get_own_addr() argument
57 os_memcpy(addr, l2->own_addr, ETH_ALEN); in l2_packet_get_own_addr()
62 int l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, in l2_packet_send() argument
81 msg.msg_name = &l2->priv_addr; in l2_packet_send()
82 msg.msg_namelen = sizeof(l2->priv_addr); in l2_packet_send()
[all …]
H A Dl2_packet_ndis.c56 struct l2_packet_data *l2[2]; member
84 int l2_packet_get_own_addr(struct l2_packet_data *l2, u8 *addr) in l2_packet_get_own_addr() argument
86 os_memcpy(addr, l2->own_addr, ETH_ALEN); in l2_packet_get_own_addr()
91 int l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, in l2_packet_send() argument
102 if (l2 == NULL) in l2_packet_send()
112 if (l2->l2_hdr) { in l2_packet_send()
122 os_memcpy(eth->h_source, l2->own_addr, ETH_ALEN); in l2_packet_send()
134 wpa_printf(MSG_DEBUG, "L2(NDISUIO): Wait for pending " in l2_packet_send()
140 wpa_printf(MSG_DEBUG, "L2(NDISUIO): " in l2_packet_send()
148 wpa_printf(MSG_DEBUG, "L2(NDISUIO): WriteFile failed: %d", in l2_packet_send()
[all …]
H A Dl2_packet_linux.c108 int l2_packet_get_own_addr(struct l2_packet_data *l2, u8 *addr) in l2_packet_get_own_addr() argument
110 os_memcpy(addr, l2->own_addr, ETH_ALEN); in l2_packet_get_own_addr()
115 int l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, in l2_packet_send() argument
122 if (l2 == NULL) in l2_packet_send()
124 if (l2->l2_hdr) { in l2_packet_send()
125 ret = send(l2->fd, buf, len, 0); in l2_packet_send()
133 ll.sll_ifindex = l2->ifindex; in l2_packet_send()
137 ret = sendto(l2->fd, buf, len, 0, (struct sockaddr *) &ll, in l2_packet_send()
150 struct l2_packet_data *l2 = eloop_ctx; in l2_packet_receive() local
170 if (l2 in l2_packet_receive()
221 struct l2_packet_data *l2 = eloop_ctx; l2_packet_receive_br() local
277 struct l2_packet_data *l2; l2_packet_init() local
347 struct l2_packet_data *l2; l2_packet_init_bridge() local
425 l2_packet_deinit(struct l2_packet_data * l2) l2_packet_deinit() argument
446 l2_packet_get_ip_addr(struct l2_packet_data * l2,char * buf,size_t len) l2_packet_get_ip_addr() argument
479 l2_packet_notify_auth_start(struct l2_packet_data * l2) l2_packet_notify_auth_start() argument
484 l2_packet_set_packet_filter(struct l2_packet_data * l2,enum l2_packet_filter_type type) l2_packet_set_packet_filter() argument
[all...]
H A Dl2_packet_freebsd.c53 int l2_packet_get_own_addr(struct l2_packet_data *l2, u8 *addr) in l2_packet_get_own_addr()
55 os_memcpy(addr, l2->own_addr, ETH_ALEN);
60 int l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, in l2_packet_send()
63 if (!l2->l2_hdr) { in l2_packet_send()
69 os_memcpy(eth->h_source, l2->own_addr, ETH_ALEN); in l2_packet_send()
72 ret = pcap_inject(l2->pcap, (u8 *) eth, len + sizeof(*eth)); in l2_packet_send()
76 return pcap_inject(l2->pcap, buf, len);
82 struct l2_packet_data *l2 = eloop_ctx; in l2_packet_receive()
96 if (!l2->rx_callback || !packet || hdr->caplen < sizeof(*ethhdr)) in l2_packet_receive()
100 if (l2 in l2_packet_receive()
50 l2_packet_get_own_addr(struct l2_packet_data * l2,u8 * addr) l2_packet_get_own_addr() argument
57 l2_packet_send(struct l2_packet_data * l2,const u8 * dst_addr,u16 proto,const u8 * buf,size_t len) l2_packet_send() argument
79 struct l2_packet_data *l2 = eloop_ctx; l2_packet_receive() local
113 l2_packet_init_libpcap(struct l2_packet_data * l2,unsigned short protocol) l2_packet_init_libpcap() argument
244 struct l2_packet_data *l2; l2_packet_init() local
282 l2_packet_deinit(struct l2_packet_data * l2) l2_packet_deinit() argument
295 l2_packet_get_ip_addr(struct l2_packet_data * l2,char * buf,size_t len) l2_packet_get_ip_addr() argument
331 l2_packet_notify_auth_start(struct l2_packet_data * l2) l2_packet_notify_auth_start() argument
336 l2_packet_set_packet_filter(struct l2_packet_data * l2,enum l2_packet_filter_type type) l2_packet_set_packet_filter() argument
[all...]
H A Dl2_packet_none.c30 int l2_packet_get_own_addr(struct l2_packet_data *l2, u8 *addr) in l2_packet_get_own_addr() argument
32 os_memcpy(addr, l2->own_addr, ETH_ALEN); in l2_packet_get_own_addr()
37 int l2_packet_send(struct l2_packet_data *l2, const u8 *dst_addr, u16 proto, in l2_packet_send() argument
40 if (l2 == NULL) in l2_packet_send()
45 * whether l2->l2_hdr is set). in l2_packet_send()
54 struct l2_packet_data *l2 = eloop_ctx; in l2_packet_receive() local
62 l2->rx_callback(l2->rx_callback_ctx, NULL /* TODO: src addr */, in l2_packet_receive()
73 struct l2_packet_data *l2; in l2_packet_init() local
75 l2 = os_zalloc(sizeof(struct l2_packet_data)); in l2_packet_init()
76 if (l2 == NULL) in l2_packet_init()
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dl2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
16 "fsl,mpc8541-l2-cache-controller"
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/cache/
H A Dfreescale-l2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
16 "fsl,mpc8541-l2-cache-controller"
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/amdzen4/
H A Dcache.json23 "BriefDescription": "Demand data cache fills from local L2 cache.",
29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
71 "BriefDescription": "Any data cache fills from local L2 cache.",
77 "BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.",
83 …"BriefDescription": "Any data cache fills from local L2 cache or L3 cache or different L2 cache in…
149 …move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2).",
191 "BriefDescription": "Software prefetch data cache fills from local L2 cache.",
197 …"BriefDescription": "Software prefetch data cache fills from L3 cache or different L2 cache in the…
239 "BriefDescription": "Hardware prefetch data cache fills from local L2 cache.",
245 …"BriefDescription": "Hardware prefetch data cache fills from L3 cache or different L2 cache in the…
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A Dcache.json15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
58 …"BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS). The number…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
105 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/amdzen2/
H A Dcache.json5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A Dcache.json5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
/freebsd-src/sys/powerpc/mpc85xx/
H A Dmpc85xx_cache.c55 {"fsl,8540-l2-cache-controller", 1},
56 {"fsl,8541-l2-cache-controller", 1},
57 {"fsl,8544-l2-cache-controller", 1},
58 {"fsl,8548-l2-cache-controller", 1},
59 {"fsl,8555-l2-cache-controller", 1},
60 {"fsl,8568-l2-cache-controller", 1},
61 {"fsl,b4420-l2-cache-controller", 1},
62 {"fsl,b4860-l2-cache-controller", 1},
63 {"fsl,bsc9131-l2-cache-controller", 1},
64 {"fsl,bsc9132-l2-cache-controller", 1},
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/bonnell/
H A Dcache.json59 "BriefDescription": "Cycles L2 address bus is in use.",
107 "BriefDescription": "Cycles the L2 cache data bus is busy.",
115 "BriefDescription": "Cycles the L2 transfers data to the core.",
123 "BriefDescription": "L2 cacheable instruction fetch requests",
131 "BriefDescription": "L2 cacheable instruction fetch requests",
139 "BriefDescription": "L2 cacheable instruction fetch requests",
147 "BriefDescription": "L2 cacheable instruction fetch requests",
155 "BriefDescription": "L2 cacheable instruction fetch requests",
163 "BriefDescription": "L2 cache reads",
171 "BriefDescription": "L2 cache reads",
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/goldmont/
H A Dcache.json37 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
41 "BriefDescription": "L2 cache request misses",
46 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
51 "BriefDescription": "L2 cache requests",
56 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
68 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
109 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
116 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
121 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
128 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/goldmontplus/
H A Dcache.json45 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
49 "BriefDescription": "L2 cache request misses",
56 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
61 "BriefDescription": "L2 cache requests",
68 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
81 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
125 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
133 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
138 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
146 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/knightslanding/
H A Dcache.json3 … number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condit…
19 "BriefDescription": "Counts the number of L2 cache misses",
27 "BriefDescription": "Counts the total number of L2 cache references.",
35 … a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictio…
79 "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2",
89 "BriefDescription": "Counts the number of load micro-ops retired that miss in the L2",
126 … forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Vali…
137 …rwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid …
148 … data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
159 …or reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/silvermont/
H A Dcache.json7 … eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests …
20 … "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ",
24 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the I…
28 "BriefDescription": "L2 cache request misses",
32 …licDescription": "This event counts the total number of L2 cache references and the number of L2 c…
37 "BriefDescription": "L2 cache requests from this core",
41 …his event counts requests originating from the core that references a cache line in the L2 cache.",
83 "BriefDescription": "Loads hit L2",
88 "PublicDescription": "This event counts the number of load ops retired that hit in the L2.",
93 "BriefDescription": "Loads missed L2",
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/broadwellde/
H A Dcache.json55 "BriefDescription": "Not rejected writebacks that hit L2 cache",
60 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
65 "BriefDescription": "L2 cache lines filling L2",
70 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does…
75 "BriefDescription": "L2 cache lines in E state filling L2",
80 …licDescription": "This event counts the number of L2 cache lines in the Exclusive state filling th…
85 "BriefDescription": "L2 cache lines in I state filling L2",
90 …licDescription": "This event counts the number of L2 cache lines in the Invalidate state filling t…
95 "BriefDescription": "L2 cache lines in S state filling L2",
100 …ublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the…
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/
H A Dcache.json102 …L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this ev…
105 …L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this ev…
114 …: "L2 cache write streaming mode. This event counts for each cycle where the core is in write stre…
117 …: "L2 cache write streaming mode. This event counts for each cycle where the core is in write stre…
144 … "PublicDescription": "L2 TLB walk cache access. This event does not count if the MMU is disabled",
147 … "BriefDescription": "L2 TLB walk cache access. This event does not count if the MMU is disabled"
150 … "PublicDescription": "L2 TLB walk cache refill. This event does not count if the MMU is disabled",
153 … "BriefDescription": "L2 TLB walk cache refill. This event does not count if the MMU is disabled"
156 …"PublicDescription": "L2 TLB IPA cache access. This event counts on each access to the IPA cache. …
159 …"BriefDescription": "L2 TLB IPA cache access. This event counts on each access to the IPA cache. I…
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/haswell/
H A Dcache.json63 "BriefDescription": "Not rejected writebacks that hit L2 cache",
68 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
73 "BriefDescription": "L2 cache lines filling L2",
78 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
83 "BriefDescription": "L2 cache lines in E state filling L2",
88 "PublicDescription": "L2 cache lines in E state filling L2.",
93 "BriefDescription": "L2 cache lines in I state filling L2",
98 "PublicDescription": "L2 cache lines in I state filling L2.",
103 "BriefDescription": "L2 cache lines in S state filling L2",
108 "PublicDescription": "L2 cache lines in S state filling L2.",
[all …]
/freebsd-src/sys/contrib/libsodium/test/default/
H A Dmetamorphic.c18 size_t l1, l2; in mm_generichash() local
39 l2 = randombytes_uniform((uint32_t) (mlen - l1)); in mm_generichash()
41 crypto_generichash_update(&st, m + l1, l2); in mm_generichash()
42 crypto_generichash_update(&st, m + l1 + l2, mlen - l1 - l2); in mm_generichash()
64 size_t l1, l2; in mm_onetimeauth() local
79 l2 = randombytes_uniform((uint32_t) (mlen - l1)); in mm_onetimeauth()
81 crypto_onetimeauth_update(&st, m + l1, l2); in mm_onetimeauth()
82 crypto_onetimeauth_update(&st, m + l1 + l2, mlen - l1 - l2); in mm_onetimeauth()
104 size_t l1, l2; in mm_hmacsha256() local
119 l2 = randombytes_uniform((uint32_t) (mlen - l1)); in mm_hmacsha256()
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/ivybridge/
H A Dcache.json56 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
65 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
70 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
75 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
80 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
85 …"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-reject…
95 "BriefDescription": "L2 cache lines filling L2",
100 "PublicDescription": "L2 cache lines filling L2.",
105 "BriefDescription": "L2 cache lines in E state filling L2",
110 "PublicDescription": "L2 cache lines in E state filling L2.",
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/powerpc/power8/
H A Dcache.json5 …essor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different…
6 …essor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different…
11 …ocessor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different…
12 …ocessor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
35 …sor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load…
36 …sor's data cache was reloaded from a localtion other than the local core's L2 due to either only d…
41 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
[all …]

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