Searched full:hss (Results 1 – 14 of 14) sorted by relevance
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#8 title: Intel IXP4xx V.35 WAN High Speed Serial Link (HSS)14 The Intel IXP4xx HSS makes use of the IXP4xx NPE (Network20 const: intel,ixp4xx-hss24 description: The HSS instance30 - description: phandle to the NPE this HSS instance is using32 description: phandle to the NPE this HSS instance is using104 description: Clock internal GPIO line, driving this high will make the HSS
47 hss@[0-9]+$:48 $ref: /schemas/net/intel,ixp4xx-hss.yaml#50 description: Optional node for the High Speed Serial link (HSS), the52 used for the HSS.70 hss@0 {71 compatible = "intel,ixp4xx-hss";
146 hss@0 {147 compatible = "intel,ixp4xx-hss";153 hss@1 {154 compatible = "intel,ixp4xx-hss";
10 * (HSS) link for a V.35 WAN interface.117 /* HSS links */119 hss@0 {134 hss@1 {
1653 "XAUI1 HSS PCS Registers"); in qls_mpi_core_dump()1670 "XFI1 HSS PCS Registers"); in qls_mpi_core_dump()1676 "XFI1 HSS TX Registers"); in qls_mpi_core_dump()1682 "XFI1 HSS RX Registers"); in qls_mpi_core_dump()1688 "XFI1 HSS PLL Registers"); in qls_mpi_core_dump()1700 "XAUI2 HSS PCS Registers"); in qls_mpi_core_dump()1717 "XFI2 HSS PCS Registers"); in qls_mpi_core_dump()1723 "XFI2 HSS TX Registers"); in qls_mpi_core_dump()1729 "XFI2 HSS RX Registers"); in qls_mpi_core_dump()1735 "XFI2 HSS PLL Registers"); in qls_mpi_core_dump()
167 BCOBJS+=${SRCS:N*.[hsS]:N*.asm:${OBJS_SRCS_FILTER:ts:}:S/$/.bco/g}168 LLOBJS+=${SRCS:N*.[hsS]:N*.asm:${OBJS_SRCS_FILTER:ts:}:S/$/.llo/g}
290 BCOBJS+= ${SRCS:N*.[hsS]:N*.asm:${OBJS_SRCS_FILTER:ts:}:S/$/.bco/g}291 LLOBJS+= ${SRCS:N*.[hsS]:N*.asm:${OBJS_SRCS_FILTER:ts:}:S/$/.llo/g}
110 Copper DB-9 and Copper HSS-DC connectors are also fine. Copper &&
207 status = "disabled"; /* Reserved for the HSS */
303 status = "disabled"; /* Reserved for the HSS */
372 * Hierarchical Signature System (HSS)
112 #define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f) \ argument114 .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \
26278 @Article{Shamir:1979:HSS,
66071 …T_E5 (0x1<<0) // HSS Core Reset. Asynchr…66229 …T_E5 (0x1<<0) // HSS Core Reset. Asynchr…66419 …T_E5 (0x1<<0) // HSS Core Reset. Asynchr…66579 …T_E5 (0x1<<0) // HSS Core Reset. Asynchr…