Home
last modified time | relevance | path

Searched full:hart (Results 1 – 25 of 65) sorted by relevance

123

/freebsd-src/sys/contrib/device-tree/Bindings/iio/addac/
H A Dadi,ad74115.yaml70 10 - Current output with HART
71 11 - Current input, externally-powered, with HART
72 12 - Current input, loop-powered, with HART
188 adi,dac-hart-slew:
190 description: Whether to use a HART-compatible slew rate.
268 3 - Control HART CD
269 4 - Monitor HART CD
270 5 - Monitor HART EOM status
282 3 - Control HART RXD
283 4 - Monitor HART RXD
[all …]
H A Dadi,ad74413r.yaml20 The AD74413R differentiates itself from the AD74412R by being HART-compatible.
81 HART functions are not supported on AD74412R.
/freebsd-src/sys/riscv/riscv/
H A Dmp_machdep.c151 init_secondary(uint64_t hart) in init_secondary() argument
157 cpuid = hart; in init_secondary()
166 /* Workaround: make sure wfi doesn't halt the hart */ in init_secondary()
188 /* Activate this hart in the kernel pmap. */ in init_secondary()
189 CPU_SET_ATOMIC(hart, &kernel_pmap->pm_active); in init_secondary()
318 /* Check if this hart supports MMU. */ in cpu_check_mmu()
331 uint64_t hart; in cpu_init_fdt() local
348 hart = reg[0]; in cpu_init_fdt()
350 hart <<= 32; in cpu_init_fdt()
351 hart | in cpu_init_fdt()
[all...]
H A Dplic.c135 int hart; in plic_get_hartid()
138 if (OF_searchencprop(intc, "#interrupt-cells", &hart, in plic_get_hartid()
139 sizeof(hart)) == -1) { in plic_get_hartid()
147 * interested in, so search for its hart ID.
149 if (OF_searchencprop(OF_parent(intc), "reg", (pcell_t *)&hart, in plic_irq_dispatch()
150 sizeof(hart)) == -1) { in plic_irq_dispatch()
155 return (hart); in plic_irq_dispatch()
305 int hart; in plic_attach()
367 * its hart ID. in plic_attach()
369 * 3. Convert the hart t in plic_attach()
125 int hart; plic_get_hartid() local
259 int hart; plic_attach() local
[all...]
H A Didentcpu.c331 u_int hart; in identify_cpu_features_fdt()
339 hart = pcpu_find(cpu)->pc_hart; in identify_cpu_features_fdt()
352 reg != hart) in identify_cpu_features_fdt()
359 "for CPU %d, hart %u\n", __func__, cpu, hart); in identify_cpu_features_fdt()
379 printf("%s: could not find FDT node for CPU %u, hart %u\n",
380 __func__, cpu, hart);
515 u_int hart; in printcpuinfo()
518 hart = pcpu_find(cpu)->pc_hart; in printcpuinfo()
532 printf("CPU %-3u: Vendor=%s Core=%s (Hart
326 u_int hart; identify_cpu_features_fdt() local
475 u_int hart; printcpuinfo() local
[all...]
H A Dmachdep.c117 uint32_t boot_hart = BOOT_HART_INVALID; /* The hart we booted on. */
477 uint32_t hart; in initriscv()
505 * Look for the boot hart ID. This was either passed in directly from in initriscv()
510 if (OF_getencprop(chosen, "boot-hartid", &hart, sizeof(hart)) != -1) { in initriscv()
511 boot_hart = hart; in initriscv()
515 panic("Boot hart ID was not properly set"); in initriscv()
486 uint32_t hart; initriscv() local
H A Dsbi.c161 printf("SBI: PolarFire Hart Software Services %lu\n", in sbi_print_version()
263 sbi_hsm_hart_start(u_long hart, u_long start_addr, u_long priv) in sbi_hsm_hart_start() argument
267 ret = SBI_CALL3(SBI_EXT_ID_HSM, SBI_HSM_HART_START, hart, start_addr, in sbi_hsm_hart_start()
279 sbi_hsm_hart_status(u_long hart) in sbi_hsm_hart_status() argument
283 ret = SBI_CALL1(SBI_EXT_ID_HSM, SBI_HSM_HART_STATUS, hart); in sbi_hsm_hart_status()
H A Dlocore.S58 * - a0 = hart ID
61 * Multiple CPUs might enter from this point, so we perform a hart lottery and
72 /* Pick a hart to run the boot process. */
84 /* Store the boot hart */
H A Daplic.c198 * interested in, so search for its hart ID. in fdt_get_hartid()
386 /* Get the hart ID from the CLIC's phandle. */ in aplic_setup_direct_mode()
396 device_printf(dev, "Invalid cpu for hart %d\n", hartid); in aplic_setup_direct_mode()
455 /* APLIC with IMSIC on hart is not supported */ in aplic_attach()
527 device_printf(dev, "Bind irq %d to cpu%d (hart %d)\n", src->irq, in aplic_bind_intr()
H A Dpmap.c861 CPU_SET(PCPU_GET(hart), &kernel_pmap->pm_active); in pmap_bootstrap()
1007 CPU_CLR(PCPU_GET(hart), &mask); in pmap_invalidate_page()
1022 CPU_CLR(PCPU_GET(hart), &mask);
1042 CPU_CLR(PCPU_GET(hart), &mask); in pmap_extract()
5079 u_int hart;
5087 hart = PCPU_GET(hart); in sysctl_kmaps_dump()
5089 CPU_SET_ATOMIC(hart, &pmap->pm_active); in sysctl_kmaps_dump()
5090 CPU_CLR_ATOMIC(hart, &oldpmap->pm_active); in sysctl_kmaps_dump()
5092 CPU_SET(hart, in sysctl_kmaps_dump()
4844 u_int hart; pmap_activate_sw() local
4877 u_int hart; pmap_activate_boot() local
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
7 Every interrupt is ultimately routed through a hart's HLIC before it
8 interrupts that hart.
40 definition of the hart whose CSRs control these local interrupts.
H A Dsifive,plic-1.0.0.txt7 hart contexts in the system, via the external interrupt source in each hart.
9 A hart context is a privilege mode in a hardware execution thread. For example,
11 privilege modes per hart; machine mode and supervisor mode.
H A Dsifive,plic-1.0.0.yaml14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
17 A hart context is a privilege mode in a hardware execution thread. For example,
19 privilege modes per hart; machine mode and supervisor mode.
/freebsd-src/sys/riscv/include/
H A Dsbi.h96 /* Hart State Management (HSM) Extension */
189 /* Hart State Management extension functions. */
192 * Start execution on the specified hart at physical address start_addr. The
193 * register a0 will contain the hart's ID, and a1 will contain the value of
196 int sbi_hsm_hart_start(u_long hart, u_long start_addr, u_long priv);
199 * Stop execution on the current hart. Interrupts should be disabled, or this
205 * Get the execution status of the specified hart. The status will be one of:
211 int sbi_hsm_hart_status(u_long hart);
H A Dpcpu.h48 uint32_t pc_hart; /* Hart ID */ \
/freebsd-src/sys/contrib/device-tree/Bindings/riscv/
H A Dcpus.yaml18 hart: A hardware execution context, which contains all the state
62 Identifies that the hart uses the RISC-V instruction set
63 and identifies the type of the hart.
68 this hart. These values originate from the RISC-V Privileged
81 The hart ID of this CPU node.
114 by this hart (see ./idle-states.yaml).
190 // Example 2: Spike ISA Simulator with 1 Hart
H A Dextensions.yaml18 This document defines properties that indicate whether a hart supports a
37 supported by the hart. These are documented in the RISC-V
56 The base ISA implemented by this hart, as described by the 20191213
65 description: Extensions supported by the hart.
/freebsd-src/contrib/ntp/
H A DChangeLog6 stepped. <hart@ntp.org>
8 <hart@ntp.org>
10 * [Bug 3910] Memory leak using openssl-3 <hart@ntp.org>
12 <hart@ntp.org>
14 <hart@ntp.org>
15 * [Bug 3901] LIB_GETBUF isn't thread-safe. <hart@ntp.org>
17 Windows. <hart@ntp.org>
19 duplicate associations. <hart@ntp.org>
20 * [Bug 3872] Ignore restrict mask for hostname. <hart@ntp.org>
23 declaration from ntp_types.h to config.h. <hart@ntp.org>
[all …]
H A DNEWS24 stepped. <hart@ntp.org>
26 <hart@ntp.org>
28 * [Bug 3910] Memory leak using openssl-3 <hart@ntp.org>
30 <hart@ntp.org>
32 <hart@ntp.org>
33 * [Bug 3901] LIB_GETBUF isn't thread-safe. <hart@ntp.org>
35 Windows. <hart@ntp.org>
37 duplicate associations. <hart@ntp.org>
38 * [Bug 3872] Ignore restrict mask for hostname. <hart@ntp.org>
41 declaration from ntp_types.h to config.h. <hart@ntp.org>
[all …]
H A DCOPYRIGHT32 Hart, Danny Mayer, Martin Burnicki, and possibly others is:
97 21. [22]Dave Hart <davehart@gmail.com> General maintenance, IPv6
132 Hart-Davis <d@hd.org> ARCRON MSF clock driver
/freebsd-src/contrib/ntp/sntp/
H A DCOPYRIGHT32 Hart, Danny Mayer, Martin Burnicki, and possibly others is:
97 21. [22]Dave Hart <davehart@gmail.com> General maintenance, IPv6
132 Hart-Davis <d@hd.org> ARCRON MSF clock driver
/freebsd-src/sys/contrib/device-tree/Bindings/timer/
H A Dsifive,clint.yaml17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
/freebsd-src/sys/contrib/device-tree/Bindings/cpu/
H A Didle-states.yaml57 RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
58 standard mechanism for OS to request HART state transitions.
60 The platform specific suspend (or idle) states of a hart can be either
62 preserve HART registers and CSR values for all privilege modes whereas
63 a non-retentive suspend state will not preserve HART registers and CSR
/freebsd-src/contrib/ntp/sntp/m4/
H A Dsnprintf.m41 # Modified by Dave Hart for integration into NTP 4.2.7 <hart@ntp.org>
/freebsd-src/contrib/ntp/html/
H A Dcopyright.html37 <p>Content starting in 2011 from Harlan Stenn, Juergen Perlinger, Dave Hart, Danny Mayer, Martin Bu…
91 …<li><a href="mailto:%20davehart@gmail.com">Dave Hart &lt;davehart@gmail.com&gt;</a> General mainte…
113 …t;derek@toybox.demon.co.uk&gt;</a> and <a href="mailto:%20d@hd.org">Damon Hart-Davis &lt;d@hd.org&…

123