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/freebsd-src/sys/contrib/device-tree/Bindings/misc/
H A Dxlnx,sd-fec.txt4 which provides high-throughput LDPC and Turbo Code implementations.
6 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
12 - compatible: Must be "xlnx,sd-fec-1.1"
13 - clock-names : List of input clock names from the following:
14 - "core_clk", Main processing clock for processing core (required)
15 - "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required)
16 - "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)
17 - "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)
18 - "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional)
19 - "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional)
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/freebsd-src/sys/contrib/device-tree/Bindings/fpga/
H A Dxilinx-pr-decoupler.txt11 Softcore is compatible with the Xilinx LogiCORE pr-decoupler.
15 and AXI4-Lite interfaces on a Reconfigurable Partition when it is
24 - compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
25 "xlnx,pr-decoupler" or
26 "xlnx,dfx-axi-shutdown-manager-1.00" followed by
27 "xlnx,dfx-axi-shutdown-manager"
28 - regs : base address and size for decoupler module
29 - clocks : input clock to IP
30 - clock-names : should contain "aclk"
32 See Documentation/devicetree/bindings/fpga/fpga-region.txt and
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H A Dxlnx,pr-decoupler.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 - $ref: fpga-bridge.yaml#
22 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
24 bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a
28 Please refer to fpga-region.txt and fpga-bridge.txt in this directory for
34 - items:
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/freebsd-src/sys/contrib/device-tree/Bindings/media/xilinx/
H A Dxlnx,csi2rxss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@amd.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
14 traffic from compliant camera sensors and send the output as AXI4 Stream
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
19 AXI4 Stream video data.
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/freebsd-src/sys/contrib/device-tree/Bindings/media/
H A Dallegro,al5e.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Tretter <m.tretter@pengutronix.de>
12 description: |-
23 - items:
24 - const: allegro,al5e-1.1
25 - const: allegro,al5e
26 - items:
27 - const: allegro,al5d-1.1
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/freebsd-src/sys/contrib/device-tree/Bindings/gpio/
H A Dxlnx,gpio-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neeli Srinivas <srinivas.neeli@amd.com>
14 to an AXI4-Lite interface. The AXI GPIO can be configured as either
15 a single or a dual-channel device. The width of each channel is
22 - xlnx,xps-gpio-1.00.a
27 "#gpio-cells":
33 gpio-controller: true
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/freebsd-src/share/misc/
H A Dpci_vendors5 # Date: 2024-11-25 03:15:02
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-250
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