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/freebsd-src/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_radio.c63 * Take the MHz channel value and set the Channel value
71 * (freq_ref = 40MHz)
75 * (freq_ref = 40MHz/(24>>amode_ref_sel))
77 * For 5GHz channels which are 5MHz spaced,
79 * (freq_ref = 40MHz)
161 channel_sel = (freq * 4) / 75; in ar9300_set_channel()
162 channel_frac = (((freq * 4) % 75) * 0x20000) / 75; in ar9300_set_channel()
164 channel_sel = (freq * 2) / 75; in ar9300_set_channel()
165 channel_frac = (((freq * 2) % 75) * 0x20000) / 75; in ar9300_set_channel()
197 channel_sel = freq / 75 ; in ar9300_set_channel()
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/freebsd-src/sys/dev/usb/video/
H A Dudl.h138 static const uint8_t udl_reg_vals_640x480_60[UDL_MODE_SIZE] = { /* 25.17 Mhz 59.9 Hz
144 static const uint8_t udl_reg_vals_640x480_67[UDL_MODE_SIZE] = { /* 30.25 MHz 66.6 Hz MAC
150 static const uint8_t udl_reg_vals_640x480_72[UDL_MODE_SIZE] = { /* 31.50 Mhz 72.8 Hz
156 static const uint8_t udl_reg_vals_640x480_75[UDL_MODE_SIZE] = { /* 31.50 Mhz 75.7 Hz
162 static const uint8_t udl_reg_vals_800x480_61[UDL_MODE_SIZE] = { /* 33.00 MHz 61.9 Hz */
167 static const uint8_t udl_reg_vals_800x600_56[UDL_MODE_SIZE] = { /* 36.00 MHz 56.2 Hz
173 static const uint8_t udl_reg_vals_800x600_60[UDL_MODE_SIZE] = { /* 40.00 MHz 60.3 Hz
179 static const uint8_t udl_reg_vals_800x600_72[UDL_MODE_SIZE] = { /* 50.00 MHz 72.1 Hz
185 static const uint8_t udl_reg_vals_800x600_74[UDL_MODE_SIZE] = { /* 50.00 MHz 74.4 Hz */
190 static const uint8_t udl_reg_vals_800x600_75[UDL_MODE_SIZE] = { /* 49.50 MHz 75.0 Hz
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/usb/
H A Ddwc3-xilinx.txt8 "bus_clk" Master/Core clock, have to be >= 125 MHz for SS
9 operation and >= 60MHz for HS operation
50 interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
/freebsd-src/sys/dev/videomode/
H A Dmodelines39 # 640x480 @ 75Hz (VESA) hsync: 37.5kHz
54 # 800x600 @ 75Hz (VESA) hsync: 46.9kHz
69 # 1024x768 @ 75Hz (VESA) hsync: 60.0kHz
78 # 1152x864 @ 75Hz (VESA) hsync: 67.5kHz
81 # 1280x768 @ 75Hz (non-standard) hsync: 60.6kHz
96 # 1280x1024 @ 75Hz (VESA) hsync: 80.0kHz
111 # 1600x1200 @ 75Hz (VESA) hsync: 93.8kHz
117 # 1680x1050 @ 60.00Hz (GTF) hsync: 65.22 kHz; pclk: 147.14 MHz
123 # 1792x1344 @ 75Hz (VESA) hsync: 106.3kHz
129 # 1856x1392 @ 75Hz (VESA) hsync: 112.5kHz
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H A Dedidreg.h134 #define EDID_EST_TIMING_640_480_75 0x0400 /* 640x480 @ 75Hz */
138 #define EDID_EST_TIMING_800_600_75 0x0040 /* 800x600 @ 75Hz */
139 #define EDID_EST_TIMING_832_624_75 0x0020 /* 832x624 @ 75Hz */
143 #define EDID_EST_TIMING_1024_768_75 0x0002 /* 1024x768 @ 75Hz */
144 #define EDID_EST_TIMING_1280_1024_75 0x0001 /* 1280x1024 @ 75Hz */
230 #define EDID_DESC_RANGE_MAX_CLOCK(ptr) (((ptr)[9]) * 10) /* MHz */
/freebsd-src/sys/contrib/device-tree/Bindings/input/
H A Diqs626a.yaml238 enum: [75, 100, 150, 200]
283 0: 4 MHz (1 MHz)
284 1: 2 MHz (500 kHz)
285 2: 1 MHz (250 kHz)
397 0: 16 MHz (4 MHz)
398 1: 8 MHz (2 MHz)
399 2: 4 MHz (1 MHz)
400 3: 2 MHz (500 kHz)
603 0: 4 MHz (1 MHz)
604 1: 2 MHz (500 kHz)
[all …]
H A Diqs269a.yaml180 0: 16 MHz (4 MHz)
181 1: 8 MHz (2 MHz)
182 2: 4 MHz (1 MHz)
183 3: 2 MHz (500 kHz)
389 0: 4 MHz (1 MHz)
390 1: 2 MHz (500 kHz)
391 2: 1 MHz (250 kHz)
411 enum: [75, 100, 150, 200]
/freebsd-src/contrib/tcpdump/
H A Dprint-802_11.c430 * 0 for 20 MHz, 1 for 40 MHz;
436 { /* 20 Mhz */ { 6.5f, /* SGI */ 7.2f, },
437 /* 40 Mhz */ { 13.5f, /* SGI */ 15.0f, },
441 { /* 20 Mhz */ { 13.0f, /* SGI */ 14.4f, },
442 /* 40 Mhz */ { 27.0f, /* SGI */ 30.0f, },
446 { /* 20 Mhz */ { 19.5f, /* SGI */ 21.7f, },
447 /* 40 Mhz */ { 40.5f, /* SGI */ 45.0f, },
451 { /* 20 Mhz */ { 26.0f, /* SGI */ 28.9f, },
452 /* 40 Mhz */ { 54.
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/freebsd-src/usr.sbin/powerd/
H A Dpowerd.c66 #define DEFAULT_ACTIVE_PERCENT 75
748 "MHz\n", freqs[numfreqs - 1]);
758 "MHz\n", freqs[0]);
835 "changing frequency to %d MHz\n",
854 "changing frequency to %d MHz\n",
908 printf("load %3d%%, current freq %4d MHz (%2d), wanted freq %4d MHz\n",
915 " speed from %d MHz to %d MHz\n",
/freebsd-src/sys/contrib/device-tree/src/arm/st/
H A Dste-nomadik-nhk15.dts229 /* 320 ns min period ~= 3 MHz */
257 70 71 72 73 74 75 76 77 78 79
/freebsd-src/sys/dev/bwn/
H A Dif_bwnreg.h290 #define BWN_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */
833 77, 77, 77, 76, 76, 76, 75, 75, 74, 74, 73, 73, 73, 72, 72, 71, \
1059 #define BWN_TXH_PHY1_BW_10 0x0000 /* 10 MHz */
1060 #define BWN_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */
1061 #define BWN_TXH_PHY1_BW_20 0x0002 /* 20 MHz */
1062 #define BWN_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */
1063 #define BWN_TXH_PHY1_BW_40 0x0004 /* 40 MHz */
1064 #define BWN_TXH_PHY1_BW_40DUP 0x0005 /* 40 MHz duplicate */
/freebsd-src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-data-modul-edm-sbc.dts35 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
55 * 1 / 83 ns ~= 12 MHz , but since the PWM input clock is 24 MHz
57 * result is exactly 12 MHz, which is fine for SGTL5000 MCLK.
991 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
1003 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
1044 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
1061 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
H A Dimx8mm-data-modul-edm-sbc.dts35 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
819 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
833 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
864 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
881 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
/freebsd-src/contrib/ntp/html/drivers/
H A Ddriver7.html27 7.850 and 14.670 MHz in upper sideband, compatible AM mode. An ordinary
54 … device <tt>/dev/icom</tt> and, if successful will tune the radio to 3.331 MHz. The 1-kHz offset i…
115 frequncy is encoded as 0 for 3.330 MHz, 1 for 7.850 MHz and 2
116 for 14.670 MHz.</dd>
125 …<dd>Specifies the propagation delay for CHU (45:18N 75:45N), in seconds and fraction, with default…
/freebsd-src/sys/contrib/dev/athk/ath11k/
H A Ddebugfs_htt_stats.h90 HTT_STATS_PDEV_TWT_SESSIONS_TAG = 75,
467 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
505 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
1263 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
1353 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
1769 * ... where max_bw == 4 for 160mhz
/freebsd-src/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl-hummingboard2.dtsi271 * 3.2v 5v 74 75
482 pinctrl_hummingboard2_usdhc2_100mhz: hummingboard2-usdhc2-100mhz {
493 pinctrl_hummingboard2_usdhc2_200mhz: hummingboard2-usdhc2-200mhz {
/freebsd-src/sys/kern/
H A Dkern_cpu.c803 * For instance, a level of 50 Mhz derived from 100 Mhz + 50% is in cpufreq_expand_set()
804 * preferable to 200 Mhz + 25% because absolute settings are more in cpufreq_expand_set()
824 * derived level of 1000 MHz/25% if a level in cpufreq_expand_set()
825 * of 500 MHz/100% already exists. in cpufreq_expand_set()
900 * one absolute setting of 800 Mhz uses less power than one composed in cpufreq_dup_set()
901 * of an absolute setting of 1600 Mhz and a relative setting at 50%. in cpufreq_dup_set()
902 * Also for example (2), a level of 800 Mhz/75% is preferable to in cpufreq_dup_set()
903 * 1600 Mhz/2 in cpufreq_dup_set()
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/freebsd-src/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zcu111-revA.dts126 /* 48MHz reference crystal */
234 i2c-mux@75 { /* u23 */
453 /* refclk9 used for PS_REF_CLK 33.3 MHz */
519 i2c-mux@75 {
H A Dzynqmp-zcu102-revA.dts142 /* 48MHz reference crystal */
284 i2c-mux@75 { /* u60 */
576 /* refclk9 used for PS_REF_CLK 33.3 MHz */
619 i2c-mux@75 {
H A Dzynqmp-zcu106-revA.dts142 /* 48MHz reference crystal */
295 i2c-mux@75 { /* u60 */
577 /* refclk9 used for PS_REF_CLK 33.3 MHz */
630 i2c-mux@75 {
/freebsd-src/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra186-clock.h430 #define TEGRA186_CLK_I2C3 75
755 /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
757 /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
791 /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
827 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
831 /** Fixed 408MHz PLL for use by peripheral clocks */
866 /** Fixed frequency 960MHz PLL for USB and EAVB */
/freebsd-src/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi3660.dtsi65 capacity-dmips-mhz = <592>;
79 capacity-dmips-mhz = <592>;
92 capacity-dmips-mhz = <592>;
105 capacity-dmips-mhz = <592>;
118 capacity-dmips-mhz = <1024>;
132 capacity-dmips-mhz = <1024>;
145 capacity-dmips-mhz = <1024>;
158 capacity-dmips-mhz = <1024>;
484 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
/freebsd-src/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-bmc-delta-ahe50dc.dts138 spi-max-frequency = <50000000>; // 50 MHz
293 pca9541@75 {
/freebsd-src/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8996.dtsi52 capacity-dmips-mhz = <1024>;
71 capacity-dmips-mhz = <1024>;
85 capacity-dmips-mhz = <1024>;
104 capacity-dmips-mhz = <1024>;
1297 * 624Mhz is only available on speed bins 0 and 3.
1298 * 560Mhz is only available on speed bins 0, 2 and 3.
3296 blsp2_uart2: serial@75b0000 {
3306 blsp2_uart3: serial@75b1000 {
3316 blsp2_i2c1: i2c@75b5000 {
3333 blsp2_i2c2: i2c@75b600
[all...]
/freebsd-src/contrib/wpa/src/common/
H A Dqca-vendor.h448 * QCA_WLAN_VENDOR_ATTR_MAC_ADDR and optionally frequency (MHz) in
1091 * (CU) of each 20 MHz sub-channel of the entire connected channel using
1296 QCA_NL80211_VENDOR_SUBCMD_GET_WIFI_CONFIGURATION = 75,
1584 /* Frequency in MHz, various uses. Unsigned 32 bit value */
1851 /* A 32-bit unsigned value; the P2P listen frequency (MHz); must be one
1934 * channel width (in MHz).
1947 * 20 MHz, 40 MHz, and 80 MHz channels. The value is the center frequency index
1948 * of the primary 80 MHz segmen
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