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/freebsd-src/sys/contrib/device-tree/Bindings/mfd/
H A Domap-usb-host.txt40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
/freebsd-src/contrib/wpa/src/common/
H A Dieee802_11_common.c1375 * @freq: Frequency (MHz) to convert in ieee80211_chan_to_freq_cn()
1701 case 32: /* channels 1..7; 40 MHz */ in reason2str()
1702 case 33: /* channels 5..11; 40 MHz */ in reason2str()
1707 case 2: /* channels 52,56,60,64; dfs */ in status2str()
1708 case 22: /* channels 36,44; 40 MHz */ in status2str()
1709 case 23: /* channels 52,60; 40 MHz */ in status2str()
1710 case 27: /* channels 40,48; 40 MHz */ in status2str()
1711 case 28: /* channels 56,64; 40 MHz */ in status2str()
1716 case 24: /* channels 100-140; 40 MHz */ in status2str()
[all...]
H A Dhw_features_common.c116 int allowed[] = { 36, 44, 52, 60, 100, 108, 116, 124, 132, 140, in allowed_ht40_channel_pair()
138 "HT40: control channel: %d (%d MHz), secondary channel: %d (%d MHz)", in allowed_ht40_channel_pair()
141 /* Verify that HT40 secondary channel is an allowed 20 MHz in allowed_ht40_channel_pair()
291 wpa_printf(MSG_DEBUG, "Found overlapping 20 MHz HT BSS: " in check_20mhz_bss()
316 wpa_printf(MSG_DEBUG, "40 MHz affected channel range: [%d,%d] MHz", in check_40mhz_2g4()
324 /* Check for overlapping 20 MHz BSS */ in check_40mhz_2g4()
328 "Overlapping 20 MHz BSS is found"); in check_40mhz_2g4()
352 "40 MHz pr in check_40mhz_2g4()
[all...]
/freebsd-src/sys/dev/usb/video/
H A Dudl.h138 static const uint8_t udl_reg_vals_640x480_60[UDL_MODE_SIZE] = { /* 25.17 Mhz 59.9 Hz
144 static const uint8_t udl_reg_vals_640x480_67[UDL_MODE_SIZE] = { /* 30.25 MHz 66.6 Hz MAC
150 static const uint8_t udl_reg_vals_640x480_72[UDL_MODE_SIZE] = { /* 31.50 Mhz 72.8 Hz
156 static const uint8_t udl_reg_vals_640x480_75[UDL_MODE_SIZE] = { /* 31.50 Mhz 75.7 Hz
162 static const uint8_t udl_reg_vals_800x480_61[UDL_MODE_SIZE] = { /* 33.00 MHz 61.9 Hz */
167 static const uint8_t udl_reg_vals_800x600_56[UDL_MODE_SIZE] = { /* 36.00 MHz 56.2 Hz
173 static const uint8_t udl_reg_vals_800x600_60[UDL_MODE_SIZE] = { /* 40.00 MHz 60.3 Hz
179 static const uint8_t udl_reg_vals_800x600_72[UDL_MODE_SIZE] = { /* 50.00 MHz 72.1 Hz
185 static const uint8_t udl_reg_vals_800x600_74[UDL_MODE_SIZE] = { /* 50.00 MHz 74.4 Hz */
190 static const uint8_t udl_reg_vals_800x600_75[UDL_MODE_SIZE] = { /* 49.50 MHz 75.0 Hz
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/devfreq/
H A Drk3399_dmc.txt64 - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
70 MHz (Mega Hz). When DDR frequency is less than
75 the ODT disable frequency in MHz (Mega Hz).
101 then ODT disable frequency in MHz (Mega Hz).
128 MHz (Mega Hz). When the DDR frequency is less then
134 value is 60.
157 the PHY side ODT strength. Default value is 60.
205 rockchip,lpddr4_drv = <60>;
211 rockchip,phy_lpddr4_odt = <60>;
/freebsd-src/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_dfs.c29 /* 20MHz */
34 RADAR_SPEC(3, 60, 20, 46, 300, 640, 80, 4900, 10100, 80, 0,
38 /* 40MHz */
43 RADAR_SPEC(3, 60, 20, 46, 300, 640, 80, 4900, 10100, 80, 0,
47 /* 80MHz */
52 RADAR_SPEC(3, 60, 20, 46, 300, 640, 80, 4900, 10100, 80, 0,
59 /* 20MHz */
66 RADAR_SPEC(2, 60, 15, 63, 640, 2080, 32, 19600, 40200, 32, 0,
68 /* 40MHz */
75 RADAR_SPEC(2, 60, 15, 63, 640, 2080, 32, 19600, 40200, 32, 0,
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/regulator/
H A Dmax8952.txt15 - 0: 26 MHz
16 - 1: 13 MHz
17 - 2: 19.2 MHz
18 Defaults to 26 MHz if not specified.
33 vdd_arm_reg: pmic@60 {
H A Dmaxim,max8952.yaml62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
91 pmic@60 {
/freebsd-src/sys/contrib/dev/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
16 {cpu_to_le16(160), {50, 58, 60, 62, 64, 52, 54, 56},
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
52 /* frequency 5200MHz */
[all...]
/freebsd-src/sys/net80211/
H A Dieee80211_dfs.c56 static int ieee80211_nol_timeout = 30*60; /* 30 minutes */
61 static int ieee80211_cac_timeout = 60; /* 60 seconds */
148 "CAC timer on channel %u (%u MHz) stopped due to radar\n", in cac_timeout()
157 "CAC timer on channel %u (%u MHz) expired; " in cac_timeout()
190 if_printf(vap->iv_ifp, "start %d second CAC timer on channel %u (%u MHz)\n", in ieee80211_dfs_cac_start()
209 if_printf(vap->iv_ifp, "stop CAC timer on channel %u (%u MHz)\n", in ieee80211_dfs_cac_stop()
253 "(%u MHz) cleared after timeout\n", in dfs_timeout()
275 ic_printf(ic, "radar detected on channel %u (%u MHz)\n", in announce_radar()
278 ic_printf(ic, "radar detected on channel %u (%u MHz), " in announce_radar()
279 "moving to channel %u (%u MHz)\n", in announce_radar()
H A Dieee80211_regdomain.h62 CTRY_BERMUDA = 60,
258 SKU_SR9 = 0x0298, /* Ubiquiti SR9 (900MHz/GSM) */
259 SKU_XR9 = 0x0299, /* Ubiquiti XR9 (900MHz/GSM) */
260 SKU_GZ901 = 0x029a, /* Zcomax GZ-901 (900MHz/GSM) */
261 SKU_XC900M = 0x029b, /* Xagyl XC900M (900MHz/GSM) */
266 * offset channel spacing (905MHz-
267 * 925MHz) versus the XR9 (907MHz-
268 * 922MHz), giving an extra channel.
/freebsd-src/sys/contrib/dev/iwlwifi/cfg/
H A Dax210.c105 .d3_debug_data_length = 60 * 1024, \
201 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz";
202 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz";
203 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz";
204 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz";
207 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)";
209 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)";
211 "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)";
213 "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)";
215 "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireles
[all...]
H A D22000.c93 .d3_debug_data_length = 60 * 1024, \
205 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz";
206 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz";
208 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz";
211 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)";
213 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)";
215 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)";
217 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)";
245 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
283 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/usb/
H A Dqcom,dwc3.yaml81 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
82 60MHz for HS operation.
87 mode. Its frequency should be 19.2MHz.
189 - description: Master/Core clock, has to be >= 125 MHz
190 for SS operation and >= 60MHz for HS operation.
H A Ddwc3-xilinx.txt8 "bus_clk" Master/Core clock, have to be >= 125 MHz for SS
9 operation and >= 60MHz for HS operation
H A Ddwc3-xilinx.yaml39 - description: Master/Core clock, has to be >= 125 MHz
40 for SS operation and >= 60MHz for HS operation.
/freebsd-src/sys/contrib/device-tree/Bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
124 Defines the auto PD disable frequency in MHz.
128 minimum: 1000000 # In case anyone thought this was MHz.
176 minimum: 1000000 # In case anyone thought this was MHz.
223 minimum: 1000000 # In case anyone thought this was MHz.
235 default: 60
283 default: 60
/freebsd-src/sys/contrib/device-tree/Bindings/input/
H A Diqs269a.yaml180 0: 16 MHz (4 MHz)
181 1: 8 MHz (2 MHz)
182 2: 4 MHz (1 MHz)
183 3: 2 MHz (500 kHz)
221 approximately 60-ms pulse to be asserted on the GPIO4 pin.
336 Decreases the internal measurement capacitance from 60 pF to 15 pF.
389 0: 4 MHz (1 MHz)
390 1: 2 MHz (500 kHz)
391 2: 1 MHz (250 kHz)
H A Diqs626a.yaml192 Decreases the internal measurement capacitance from 60 pF to 15 pF.
283 0: 4 MHz (1 MHz)
284 1: 2 MHz (500 kHz)
285 2: 1 MHz (250 kHz)
397 0: 16 MHz (4 MHz)
398 1: 8 MHz (2 MHz)
399 2: 4 MHz (1 MHz)
400 3: 2 MHz (500 kHz)
530 Decreases the internal measurement capacitance from 60 pF to 15 pF.
603 0: 4 MHz (1 MHz)
[all …]
/freebsd-src/sys/contrib/dev/iwlwifi/fw/
H A Drs.c46 { "60", "64QAM 5/6"},
57 "20Mhz",
58 "40Mhz",
59 "80Mhz",
60 "160 Mhz",
61 "320Mhz",
/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dsilabs,si5351.txt61 /* 25MHz reference crystal */
71 si5351a: clock-generator@60 {
78 /* connect xtal input to 25MHz reference */
91 * - set initial clock frequency of 74.25MHz
/freebsd-src/sys/contrib/device-tree/src/arm/marvell/
H A Ddove-cubox.dts45 /* 25MHz reference crystal */
90 si5351: clock-generator@60 {
97 /* connect xtal input to 25MHz reference */
/freebsd-src/sys/contrib/device-tree/src/arm64/qcom/
H A Dipq9574-rdp-common.dtsi52 debounce-interval = <60>;
97 * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
102 * corner parts to operate at 800MHz
/freebsd-src/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c131 PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz)
132 PLLU: Clock source for USB PHY, provides 12/60/480 MHz
136 PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum)
216 /* PLLM: 880 MHz Clock source for EMC 2x clock */
240 /* PLLC: 600 MHz Clock source for general use */
253 /* PLLC2: 600 MHz Clock source for engine scaling */
264 /* PLLC3: 600 MHz Clock source for engine scaling */
275 /* PLLC4: 600 MHz Clock source for ISP/VI units */
288 /* PLLP: 408 MHz Clock source for most peripherals */
298 /* PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) */
[all …]
/freebsd-src/sys/dev/videomode/
H A Dmodelines33 # 640x480 @ 60Hz (Industry standard) hsync: 31.5kHz
48 # 800x600 @ 60Hz (VESA) hsync: 37.9kHz
63 # 1024x768 @ 60Hz (VESA) hsync: 48.4kHz
84 # 1280x960 @ 60Hz (VESA) hsync: 60.0kHz
90 # 1280x1024 @ 60Hz (VESA) hsync: 64.0kHz
102 # 1600x1200 @ 60Hz (VESA) hsync: 75.0kHz
117 # 1680x1050 @ 60.00Hz (GTF) hsync: 65.22 kHz; pclk: 147.14 MHz
120 # 1792x1344 @ 60Hz (VESA) hsync: 83.6kHz
126 # 1856x1392 @ 60Hz (VESA) hsync: 86.3kHz
132 # 1920x1440 @ 60Hz (VESA) hsync: 90.0kHz
[all …]

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