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/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Darmada3700-periph-clock.txt36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
H A Dstarfive,jh7100-clkgen.yaml22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
/freebsd-src/sys/contrib/device-tree/Bindings/input/touchscreen/
H A Dstmpe.txt15 1 -> 50 us
21 7 -> 50 ms
29 6 -> 50 ms
35 1 -> 50 mA (typical 80 mA max)
53 0 -> 1.625 MHz
54 1 -> 3.25 MHz
55 2 || 3 -> 6.5 MHz
78 /* 3.25 MHz ADC clock speed */
99 * 50 mA typical 80 mA max touchscreen drivers
/freebsd-src/sys/contrib/dev/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
16 {cpu_to_le16(160), {50, 58, 60, 62, 64, 52, 54, 56},
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
52 /* frequency 5200MHz */
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dmicrel.txt23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
H A Dnxp,tja11xx.yaml54 typically derived from an external 25MHz crystal. Alternatively,
55 a 50MHz clock signal generated by an external oscillator can be
56 connected to pin REF_CLK. A third option is to connect a 25MHz
H A Drockchip-dwmac.txt32 - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
34 PHY provides the reference clock(50MHz), "output" means GMAC provides the
H A Drockchip-dwmac.yaml79 For RGMII, it must be "input", means main clock(125MHz)
81 For RMII, "input" means PHY provides the reference clock(50MHz),
/freebsd-src/sys/dev/sfxge/common/
H A Def10_tlv_layout.h459 uint16_t clk_sys; /* MHz */
460 uint16_t clk_dpcpu; /* MHz */
461 uint16_t clk_icore; /* MHz */
462 uint16_t clk_pcs; /* MHz */
470 uint16_t clk_sys; /* MHz */
471 uint16_t clk_mc; /* MHz */
472 uint16_t clk_rmon; /* MHz */
473 uint16_t clk_vswitch; /* MHz */
474 uint16_t clk_dpcpu; /* MHz */
475 uint16_t clk_pcs; /* MHz */
[all …]
/freebsd-src/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_radio.c63 * Take the MHz channel value and set the Channel value
71 * (freq_ref = 40MHz)
75 * (freq_ref = 40MHz/(24>>amode_ref_sel))
77 * For 5GHz channels which are 5MHz spaced,
79 * (freq_ref = 40MHz)
154 * freq_ref = (50 / (refdiva >> a_mode_ref_sel)); in ar9300_set_channel()
169 * freq_ref = (50 / (refdiva >> a_mode_ref_sel)); in ar9300_set_channel()
192 * freq_ref = (50 / (refdiva >> amoderefsel)); in ar9300_set_channel()
/freebsd-src/sys/arm/freescale/imx/
H A Dimx6_anatop.c119 * 396MHz, it also says that the ARM and SOC voltages can't differ by
124 uint32_t mhz; member
136 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked
170 * can't be more than 50mV above or 200mV below them. We keep them the in vdd_set()
266 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz); in cpufreq_nearest_oppt()
281 if (op->mhz > sc->cpu_curmhz) { in cpufreq_set_clock()
289 * - Set the PLL into bypass mode; cpu should now be running at 24mhz. in cpufreq_set_clock()
291 * - Wait for the LOCK bit to come on; it takes ~50 loop iterations. in cpufreq_set_clock()
294 cpufreq_mhz_to_div(sc, op->mhz, &corediv, &plldiv); in cpufreq_set_clock()
316 if (op->mhz < s in cpufreq_set_clock()
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam5729-beagleboneai.dts422 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
444 * 50 mA typical 80 mA max touchscreen drivers
555 /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */
556 /* HS: High speed up to 50 MHz (3.3 V signaling). */
557 /* SDR12: SDR up to 25 MHz (1.8 V signaling). */
558 /* SDR25: SDR up to 50 MHz (1.8 V signaling). */
559 /* SDR50: SDR up to 100 MHz (1.8 V signaling). */
560 /* SDR104: SDR up to 208 MHz (1.
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/mfd/
H A Dst,stmpe.yaml79 0 = 1.625 MHz
80 1 = 3.25 MHz
81 2, 3 = 6.5 MHz
156 1 = 50 us
162 7 = 50 ms
175 6 = 50 ms
190 1 = 50 mA (typical 80 mA max)
/freebsd-src/contrib/wpa/wpa_supplicant/
H A Dop_classes.c59 * In 80 MHz, the bandwidth "spans" 12 channels (e.g., 36-48), in get_center_80mhz()
129 * In 160 MHz, the bandwidth "spans" 28 channels (e.g., 36-64), in get_center_160mhz()
149 const u8 center_channels_5ghz[] = { 50, 114, 163 }; in verify_160mhz()
199 * In 320 MHz, the bandwidth "spans" 60 channels (e.g., 65-125), in verify_channel()
275 * valid 20 MHz channels. Override earlier allow_channel() in wpas_op_class_supported()
276 * result and use only the 80 MHz specific version. in wpas_op_class_supported()
282 * valid 20 MHz channels. Override earlier allow_channel() in wpas_op_class_supported()
283 * result and use only the 160 MHz specific version. in wpas_op_class_supported()
289 * valid 20 MHz channels. Override earlier allow_channel() in wpas_op_class_supported()
290 * result and use only the 80 MHz specifi in wpas_op_class_supported()
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6sx-softing-vining-2000.dts417 pinctrl_usdhc2_50mhz: usdhc2grp-50mhz {
430 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
441 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
452 pinctrl_usdhc4_50mhz: usdhc4grp-50mhz {
468 pinctrl_usdhc4_100mhz: usdhc4-100mhz {
483 pinctrl_usdhc4_200mhz: usdhc4-200mhz {
/freebsd-src/sys/dts/arm/
H A Dzybo.dts47 clock-frequency = <50000000>; // 50Mhz PS_CLK
51 clock-frequency = <325000000>; // 325Mhz
/freebsd-src/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-st.txt41 - max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for
/freebsd-src/sys/contrib/device-tree/src/powerpc/
H A Dac14xx.dts26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
145 bus-frequency = <80000000>; /* 80 MHz ips bus */
189 at24@50 {
258 1E 4C 50 00 00 00 01 01 01 01 01 01 01 01 01 01
/freebsd-src/sys/contrib/dev/athk/
H A Ddfs_pattern_detector.c37 #define MIN_PPB_THRESH 50
43 #define WIDTH_LOWER(X) ((X*(100-WIDTH_TOLERANCE)+50)/100)
44 #define WIDTH_UPPER(X) ((X*(100+WIDTH_TOLERANCE)+50)/100)
93 FCC_PATTERN(5, 50, 100, 1000, 2000, 1, 1, true),
113 JP_PATTERN(2, 0, 1, 1388, 1388, 1, 18, 50, false),
114 JP_PATTERN(3, 0, 4, 4000, 4000, 1, 18, 50, false),
115 JP_PATTERN(4, 0, 5, 150, 230, 1, 23, 50, false),
116 JP_PATTERN(5, 6, 10, 200, 500, 1, 16, 50, false),
117 JP_PATTERN(6, 11, 20, 200, 500, 1, 12, 50, false),
118 JP_PATTERN(7, 50, 100, 1000, 2000, 1, 3, 50, true),
[all …]
/freebsd-src/sys/contrib/dev/iwlwifi/cfg/
H A D22000.c205 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz";
206 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz";
208 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz";
211 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)";
213 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)";
215 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)";
217 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)";
245 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
283 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
309 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
[all...]
/freebsd-src/contrib/wpa/src/common/
H A Dieee802_11_common.c45 /* Microsoft OUI (00:50:F2) with OUI Type 1: in ieee802_11_parse_vendor_specific()
1375 * @freq: Frequency (MHz) to convert in ieee80211_chan_to_freq_cn()
1701 case 32: /* channels 1..7; 40 MHz */ in reason2str()
1702 case 33: /* channels 5..11; 40 MHz */ in reason2str()
1708 case 22: /* channels 36,44; 40 MHz */ in status2str()
1709 case 23: /* channels 52,60; 40 MHz */ in status2str()
1710 case 27: /* channels 40,48; 40 MHz */ in status2str()
1711 case 28: /* channels 56,64; 40 MHz */ in status2str()
1716 case 24: /* channels 100-140; 40 MHz */ in status2str()
1721 case 25: /* channels 149,157; 40 MHz */ in status2str()
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/pinctrl/
H A Dintel,pinctrl-keembay.yaml78 0 - Fast(~100MHz)
79 1 - Slow(~50MHz)
/freebsd-src/sys/contrib/device-tree/Bindings/spi/
H A Djcore,spi.txt18 fixed 50 MHz.
/freebsd-src/sys/contrib/device-tree/Bindings/mtd/
H A Dspear_smi.txt23 clock-rate = <50000000>; /* 50MHz */
/freebsd-src/sys/net80211/
H A Dieee80211_regdomain.h56 CTRY_BANGLADESH = 50, /* Bangladesh */
258 SKU_SR9 = 0x0298, /* Ubiquiti SR9 (900MHz/GSM) */
259 SKU_XR9 = 0x0299, /* Ubiquiti XR9 (900MHz/GSM) */
260 SKU_GZ901 = 0x029a, /* Zcomax GZ-901 (900MHz/GSM) */
261 SKU_XC900M = 0x029b, /* Xagyl XC900M (900MHz/GSM) */
266 * offset channel spacing (905MHz-
267 * 925MHz) versus the XR9 (907MHz-
268 * 922MHz), giving an extra channel.

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