| /freebsd-src/sys/contrib/device-tree/src/arm/arm/ |
| H A D | vexpress-v2p-ca15-tc1.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15 MPCore (V2P-CA15)
8 * HBI-0237A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA1
[all...] |
| /freebsd-src/lib/libpmc/pmu-events/arch/x86/sandybridge/ |
| H A D | cache.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
14 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 "CounterHTOff": "0,1,2,3,4,5,6,7",
32 "CounterHTOff": "0,1,2,3,4,5,6,7",
42 "CounterHTOff": "0,1,2,3,4,5,6,7",
52 "CounterHTOff": "0,1,2,3,4,5,6,7",
92 "CounterHTOff": "0,1,2,3,4,5,6,7",
101 "CounterHTOff": "0,1,2,3,4,5,6,7",
110 "CounterHTOff": "0,1,2,3,4,5,6,7",
119 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
|
| /freebsd-src/lib/libpmc/pmu-events/arch/x86/tremontx/ |
| H A D | uncore-other.json | 11 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
23 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
166 "ScaleUnit": "4Bytes",
182 "ScaleUnit": "4Bytes",
198 "ScaleUnit": "4Bytes",
214 "ScaleUnit": "4Bytes",
227 "ScaleUnit": "4Bytes",
240 "ScaleUnit": "4Bytes",
253 "ScaleUnit": "4Bytes",
266 "ScaleUnit": "4Bytes",
[all …]
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| /freebsd-src/sys/dev/bhnd/bhndb/ |
| H A D | bhndb_pci.c | 1 /*-
2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
36 * PCI-specific implementation for the BHNDB bridge driver.
38 * Provides support for bridging from a PCI parent bus to a BHND-compatible
39 * bus (e.g. bcma or siba) via a Broadcom PCI core configured in end-point
42 * This driver handles all initial generic host-level PCI interactions with a
43 * PCI/PCIe bridge core operating in endpoint mode. Once the bridged bhnd(4)
44 * bus has been enumerated, this driver works in tandem with a core-specific
67 #include <dev/bhnd/cores/pci/bhnd_pcireg.h>
112 struct bhnd_core_info **cores, u_in
169 struct bhnd_core_info *cores; /**< erom-owned core table */ global() member
357 struct bhnd_core_info *cores, hostb_core; bhndb_pci_attach() local
1429 bhndb_pci_probe_copy_core_table(struct bhndb_pci_probe * probe,struct bhnd_core_info ** cores,u_int * ncores) bhndb_pci_probe_copy_core_table() argument
1447 bhndb_pci_probe_free_core_table(struct bhnd_core_info * cores) bhndb_pci_probe_free_core_table() argument
[all...] |
| H A D | bhndb.c | 1 /*-
2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
39 * a BHND-compatible bus (e.g. bcma or siba).
58 #include <dev/bhnd/cores/chipc/chipcreg.h>
80 struct bhnd_core_info *cores, u_int ncores,
86 struct bhnd_core_info *cores, u_int ncores,
90 struct bhnd_core_info *cores, u_int ncores,
119 * Default bhndb(4) implementation of DEVICE_PROBE().
122 * and is compatible with bhndb(4) bridges attached via bhndb_attach_bridge().
172 (unsigned long long) sc->chipi in bhndb_child_location()
185 bhndb_hw_matches(struct bhndb_softc * sc,struct bhnd_core_info * cores,u_int ncores,const struct bhndb_hw * hw) bhndb_hw_matches() argument
229 bhndb_init_region_cfg(struct bhndb_softc * sc,bhnd_erom_t * erom,struct bhndb_resources * br,struct bhnd_core_info * cores,u_int ncores,const struct bhndb_hw_priority * table) bhndb_init_region_cfg() argument
470 bhndb_find_hwspec(struct bhndb_softc * sc,struct bhnd_core_info * cores,u_int ncores,const struct bhndb_hw ** hw) bhndb_find_hwspec() argument
510 bhndb_attach(device_t dev,struct bhnd_chipid * cid,struct bhnd_core_info * cores,u_int ncores,struct bhnd_core_info * bridge_core,bhnd_erom_class_t * erom_class) bhndb_attach() argument
[all...] |
| H A D | bhndb_hwdata.c | 1 /*-
39 * Resource priority specifications shared by all bhndb(4) bridge
55 * Define a core priority record for all cores matching @p devclass
97 * bcma(4)-based PCI devices.
103 * Runtime access to these cores is not required, and no register
114 * These devices do not sit in a performance-critical path and can be
136 * All other cores are assumed to require efficient runtime access to
152 * siba(4)-based PCI devices.
158 * Runtime access to these cores is not required, and no register
169 * These devices do not sit in a performance-critical path and can be
[all …]
|
| H A D | bhndb_pcireg.h | 1 /*-
32 * in BHND PCI/PCIE bridge cores:
36 * - PCI (cid=0x804, revision <= 12)
47 * - PCI (cid=0x804, revision >= 13)
48 * - PCIE (cid=0x820) with ChipCommon (revision <= 31)
59 * - PCIE (cid=0x820) with ChipCommon (revision >= 32)
70 * - PCIE Gen 2 (cid=0x83c)
82 * [0x0000+0x????] fixed ARM tightly-coupled memory (TCM).
84 * 4KB mapping, newer devices will vary.
88 * == PCI Cores Revision >= 3 ==
[all …]
|
| /freebsd-src/lib/libpmc/pmu-events/arch/x86/haswell/ |
| H A D | cache.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
56 "CounterHTOff": "0,1,2,3,4,5,6,7",
65 "CounterHTOff": "0,1,2,3,4,5,6,7",
75 "CounterHTOff": "0,1,2,3,4,5,6,7",
85 "CounterHTOff": "0,1,2,3,4,5,6,7",
95 "CounterHTOff": "0,1,2,3,4,5,6,7",
105 "CounterHTOff": "0,1,2,3,4,5,6,7",
115 "CounterHTOff": "0,1,2,3,4,5,6,7",
125 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
|
| /freebsd-src/lib/libpmc/pmu-events/arch/x86/haswellx/ |
| H A D | cache.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
56 "CounterHTOff": "0,1,2,3,4,5,6,7",
65 "CounterHTOff": "0,1,2,3,4,5,6,7",
75 "CounterHTOff": "0,1,2,3,4,5,6,7",
85 "CounterHTOff": "0,1,2,3,4,5,6,7",
95 "CounterHTOff": "0,1,2,3,4,5,6,7",
105 "CounterHTOff": "0,1,2,3,4,5,6,7",
115 "CounterHTOff": "0,1,2,3,4,5,6,7",
125 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
|
| /freebsd-src/share/man/man4/ |
| H A D | siba.4 | 34 .Bd -ragged -offset indent
41 .Bd -literal -offset indent
48 .Xr bhnd 4
55 These functional blocks, known as cores, use the Open Core Protocol
62 Not all cores contain both an initiator and a target agent.
63 Initiator agents are present in cores that contain
65 or DMA processors associated with communications cores.
67 .Xr bcma 4 ,
68 .Xr bhnd 4 ,
69 .Xr intro 4
[all …]
|
| H A D | smp.4 | 24 .Dd January 4, 2019
29 .Nd description of the FreeBSD Symmetric Multi-Processor kernel
35 kernel implements symmetric multi-processor support.
43 the read-only sysctl variable
46 The number of online threads per CPU core is available in the read-only sysctl
49 The number of physical CPU cores detected by the system is available in the
50 read-only sysctl variable
51 .Va kern.smp.cores .
54 allows specific CPUs on a multi-processor system to be disabled.
68 .Xr sched_ule 4
[all …]
|
| /freebsd-src/lib/libpmc/pmu-events/arch/x86/skylakex/ |
| H A D | cache.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
28 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
35 "CounterHTOff": "0,1,2,3,4,5,6,7",
47 "CounterHTOff": "0,1,2,3,4,5,6,7",
57 "CounterHTOff": "0,1,2,3,4,5,6,7",
67 "CounterHTOff": "0,1,2,3,4,5,6,7",
75 …n triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.",
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/arm/ |
| H A D | arm,vexpress-juno.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
37 further subvariants are released of the core tile, even more fine-granular
45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
49 - const: arm,vexpress,v2p-ca9
[all …]
|
| /freebsd-src/sys/dev/bwn/ |
| H A D | if_bwn_pcivar.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Landon Fuller <landonf@FreeBSD.org>
35 /** bwn_pci per-instance state. */
54 * Early dual-band devices did not support accessing multiple PHYs
56 * WLAN cores.
58 * However, not all cards with two WLAN cores are fully populated;
65 * Some early devices shipped with unconnected ethernet cores; set
66 * this quirk to treat these cores as unpopulated.
71 * Some PCI/PCIe "Intensi-fi" chipsets shipped with floating USB
[all …]
|
| /freebsd-src/lib/libpmc/pmu-events/arch/x86/jaketown/ |
| H A D | cache.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
14 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 "CounterHTOff": "0,1,2,3,4,5,6,7",
32 "CounterHTOff": "0,1,2,3,4,5,6,7",
42 "CounterHTOff": "0,1,2,3,4,5,6,7",
52 "CounterHTOff": "0,1,2,3,4,5,6,7",
92 "CounterHTOff": "0,1,2,3,4,5,6,7",
101 "CounterHTOff": "0,1,2,3,4,5,6,7",
110 "CounterHTOff": "0,1,2,3,4,5,6,7",
119 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
|
| /freebsd-src/usr.sbin/bhyve/ |
| H A D | bhyverun.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
126 * The acceptance of a null specification ('-c ""') is by design to match the
136 set_config_value("cores", "1"); in bhyve_topology_parse()
144 errx(4, "Failed to allocate memory"); in bhyve_topology_parse()
151 else if (strncmp(cp, "cores=", strlen("cores in bhyve_topology_parse()
500 uint16_t sockets, cores, threads, maxcpus; num_vcpus_allowed() local
[all...] |
| /freebsd-src/lib/libomp/ |
| H A D | kmp_i18n_default.inc | 2 // The file was generated from en_US.txt by message-converter.py on Sat Jul 27 14:17:03 2024. //
27 "value is not a multiple of 4k",
65 "cpuid leaf 4 not supported",
77 "cores",
111 "%1$s pragma (at %2$s:%3$s():%4$s)",
142 "Real-time scheduling policy is not supported.",
143 "OMP application is running at maximum priority with real-time scheduling policy. ",
187 "%1$s: range error ((%2$d-%3$d)/%4$d too big), not using affinity.",
207 "Too many threads to use analytical guided scheduling - switchin
[all...] |
| /freebsd-src/lib/libpmc/pmu-events/arch/x86/ivytown/ |
| H A D | cache.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
58 "CounterHTOff": "0,1,2,3,4,5,6,7",
67 "CounterHTOff": "0,1,2,3,4,5,6,7",
77 "CounterHTOff": "0,1,2,3,4,5,6,7",
85 …on": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the…
87 "CounterHTOff": "0,1,2,3,4,5,6,7",
97 "CounterHTOff": "0,1,2,3,4,5,6,7",
107 "CounterHTOff": "0,1,2,3,4,5,6,7",
117 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
|
| /freebsd-src/sys/amd64/vmm/ |
| H A D | x86.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
64 * Compute ceil(log2(x)). Returns -1 if x is zero.
70 return (x == 0 ? -1 : order_base_2(x)); in log2()
83 unsigned int func, regs[4], logical_cpus, param; in x86_emulate_cpuid()
85 uint16_t cores, maxcpus, sockets, threads; in x86_emulate_cpuid() local
113 * no multi-cor in x86_emulate_cpuid()
[all...] |
| /freebsd-src/sys/dev/bhnd/ |
| H A D | bhnd_erom_if.m | 1 #-
2 # Copyright (c) 2016-2017 Landon Fuller <landon@landonf.org>
43 # bhnd(4) device enumeration.
46 # tables used by bhnd(4) buses.
94 * @retval non-zero if an error occurs initializing the EROM parser,
114 * Parse all cores descriptors, returning the array in @p cores and the count
121 * @param[out] cores The table of parsed core descriptors.
122 * @param[out] num_cores The number of core records in @p cores.
125 * @retval non-zero if an error occurs, a regular unix error code will
130 struct bhnd_core_info **cores;
[all …]
|
| /freebsd-src/lib/libpmc/pmu-events/arch/x86/sapphirerapids/ |
| H A D | uncore-other.json | 24 "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
64 "BriefDescription": "Write request of 4 bytes made by IIO Part0 to Memory",
77 "BriefDescription": "Write request of 4 bytes made by IIO Part1 to Memory",
90 "BriefDescription": "Write request of 4 bytes made by IIO Part2 to Memory",
103 "BriefDescription": "Write request of 4 bytes made by IIO Part3 to Memory",
116 … "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
129 … "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
142 … "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
155 … "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
579 …"BriefDescription": "TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC…
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/bus/ |
| H A D | brcm,bus-axi.txt | 5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
9 The cores on the AXI bus are automatically detected by bcma with the
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
13 them manually through device tree. Use an interrupt-map to specify the
17 The top-level axi bus may contain children representing attached cores
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
29 #size-cells = <1>;
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/remoteproc/ |
| H A D | ti,pru-consumer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-consumer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
25 $ref: /schemas/types.yaml#/definitions/phandle-array
32 firmware-name:
33 $ref: /schemas/types.yaml#/definitions/string-array
37 firmwares for the PRU cores, the default firmware for the core from
39 correspond to the PRU cores listed in the 'ti,prus' property
[all …]
|
| /freebsd-src/lib/libpmc/pmu-events/arch/x86/broadwellx/ |
| H A D | cache.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
28 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
57 "CounterHTOff": "0,1,2,3,4,5,6,7",
67 "CounterHTOff": "0,1,2,3,4,5,6,7",
77 "CounterHTOff": "0,1,2,3,4,5,6,7",
87 "CounterHTOff": "0,1,2,3,4,5,6,7",
97 "CounterHTOff": "0,1,2,3,4,5,6,7",
107 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
|
| /freebsd-src/contrib/llvm-project/openmp/runtime/src/i18n/ |
| H A D | en_US.txt | 4 #//===----------------------------------------------------------------------===//
8 #// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
10 #//===----------------------------------------------------------------------===//
23 # * Changing type of placeholders (e.g. "line %1$d" -> "line %1$s").
30 # --------------------------------------------------------------------------------------------------
31 -*- META -*-
32 # --------------------------------------------------------------------------------------------------
44 # --------------------------------------------------------------------------------------------------
45 -*- STRINGS -*-
46 # --------------------------------------------------------------------------------------------------
[all …]
|