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/llvm-project/llvm/test/MC/AArch64/SME/
H A Dst1d.s6 // RUN: | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
8 // RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
11 // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
18 st1d {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3]
19 // CHECK-INST: st1d {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3]
24 st1d {za2h.d[w14, 1]}, p5, [x10, x21, lsl #3]
25 // CHECK-INST: st1d {za2h.d[w14, 1]}, p5, [x10, x21, lsl #3]
30 st1d {za3h.d[w15, 1]}, p3, [x13, x8, lsl #3]
31 // CHECK-INST: st1d {za3h.d[w15, 1]}, p3, [x13, x8, lsl #3]
36 st1d {za7h.d[w15, 1]}, p7, [sp]
[all …]
H A Dld1d.s6 // RUN: | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
8 // RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
11 // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
18 ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
19 // CHECK-INST: ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
24 ld1d {za2h.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
25 // CHECK-INST: ld1d {za2h.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
30 ld1d {za3h.d[w15, 1]}, p3/z, [x13, x8, lsl #3]
31 // CHECK-INST: ld1d {za3h.d[w15, 1]}, p3/z, [x13, x8, lsl #3]
36 ld1d {za7h.d[w15, 1]}, p7/z, [sp]
[all …]
/llvm-project/lld/test/ELF/
H A Dppc64-got-to-pcrel-relaxation.s8 # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s --check-prefix=CHECK-S
9 # RUN: llvm-objdump -d --no-show-raw-insn %ts | FileCheck %s --check-prefix=CHECK-D
10 # RUN: llvm-objdump -d --no-show-raw-insn %tn | FileCheck %s --check-prefix=CHECK-D
18 # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s --check-prefix=CHECK-S
19 # RUN: llvm-objdump -d --no-show-raw-insn %ts | FileCheck %s --check-prefix=CHECK-D
20 # RUN: llvm-objdump -d --no-show-raw-insn %tn | FileCheck %s --check-prefix=CHECK-D
25 # CHECK-S-NEXT: li 3, 0
33 # CHECK-D-LABEL: <check_LBZ_STB>:
34 # CHECK-D-NEXT: pld 8
35 # CHECK-D-NEXT: pld 9
[all …]
/llvm-project/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A Dasimd-st1.s12 st1 {v0.d}[0], [sp]
13 st1 {v0.2d}, [sp]
14 st1 {v0.2d, v1.2d}, [sp]
15 st1 {v0.2d, v1.2d, v2.2d}, [sp]
16 st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp]
24 st1 {v0.d}[0], [sp], #8
25 st1 {v0.2d}, [sp], #16
26 st1 {v0.2d, v1.2d}, [sp], #32
27 st1 {v0.2d, v1.2d, v2.2d}, [sp], #48
28 st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], #64
[all …]
H A Dasimd-ld2.s10 ld2 {v0.d, v1.d}[0], [sp]
11 ld2r {v0.2d, v1.2d}, [sp]
12 ld2 {v0.2d, v1.2d}, [sp]
18 ld2 {v0.d, v1.d}[0], [sp], #16
19 ld2r {v0.2d, v1.2d}, [sp], #16
20 ld2 {v0.2d, v1.2d}, [sp], #32
26 ld2 {v0.d, v1.d}[0], [sp], x0
27 ld2r {v0.2d, v1.2d}, [sp], x0
28 ld2 {v0.2d, v1.2d}, [sp], x0
56 # ALL-NEXT: [3]: RThroughput
[all …]
H A Dasimd-ld1.s13 ld1 {v0.d}[0], [sp]
14 ld1r {v0.2d}, [sp]
15 ld1 {v0.2d}, [sp]
16 ld1 {v0.2d, v1.2d}, [sp]
17 ld1 {v0.2d, v1.2d, v2.2d}, [sp]
18 ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp]
27 ld1 {v0.d}[0], [sp], #8
28 ld1r {v0.2d}, [sp], #8
29 ld1 {v0.2d}, [sp], #16
30 ld1 {v0.2d, v1.2d}, [sp], #32
[all …]
/llvm-project/llvm/test/tools/llvm-mca/AArch64/Neoverse/
H A DV2-forwarding.s71 sadalp v0.2d, v1.4s
72 sadalp v0.2d, v1.4s
73 sadalp v0.2d, v0.4s
78 ssra v0.2d, v1.2d, #1
79 ssra v0.2d, v1.2d, #1
80 ssra v0.2d, v0.2d, #1
85 fcmla v0.2d, v1.2d, v2.2d, #90
86 fcmla v0.2d, v1.2d, v2.2d, #90
87 fcmla v0.2d, v0.2d, v1.2d, #90
91 fmul v0.2d, v0.2d, v0.2d
[all …]
H A DN1-neon-instructions.s6 abs v0.2d, v0.2d
14 addhn v0.2s, v0.2d, v0.2d
18 addhn2 v0.4s, v0.2d, v0.2d
20 addp v0.2d, v0.2d, v0.2d
57 cmle v0.2d, v0.2d, 0
65 dup v0.2d,x28
72 ext v0.16b, v0.16b, v0.16b, #3
73 ext v0.8b, v0.8b, v0.8b, #3
77 fabs v0.2d, v0.2d
87 facgt v0.2d, v0.2d, v0.2d
[all …]
H A DN2-neon-instructions.s6 abs v0.2d, v0.2d
14 addhn v0.2s, v0.2d, v0.2d
18 addhn2 v0.4s, v0.2d, v0.2d
20 addp v0.2d, v0.2d, v0.2d
57 cmle v0.2d, v0.2d, 0
65 dup v0.2d,x28
72 ext v0.16b, v0.16b, v0.16b, #3
73 ext v0.8b, v0.8b, v0.8b, #3
77 fabs v0.2d, v0.2d
87 facgt v0.2d, v0.2d, v0.2d
[all …]
H A DV2-neon-instructions.s6 abs v0.2d, v0.2d
14 addhn v0.2s, v0.2d, v0.2d
18 addhn2 v0.4s, v0.2d, v0.2d
20 addp v0.2d, v0.2d, v0.2d
38 bfmlalb v0.4s, v0.8h, v0.h[3]
[all...]
/llvm-project/llvm/test/MC/AArch64/SME2/
H A Dmova.s6 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sme2 - | FileCheck %s --check-prefix=C…
8 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sme2 - | FileCheck %s --check-prefix=C…
10 // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
27 mova {z22.h, z23.h}, za1h.h[w15, 2:3] // 11000000-01000110-01100000-10110110
28 // CHECK-INST: mov { z22.h, z23.h }, za1h.h[w15, 2:3]
39 mova {z4.h, z5.h}, za0h.h[w12, 2:3] // 11000000-01000110-00000000-00100100
40 // CHECK-INST: mov { z4.h, z5.h }, za0h.h[w12, 2:3]
45 mova {z0.h, z1.h}, za0h.h[w12, 2:3] // 11000000-01000110-00000000-00100000
46 // CHECK-INST: mov { z0.h, z1.h }, za0h.h[w12, 2:3]
63 mova {z16.h, z17.h}, za0h.h[w14, 2:3] // 11000000-01000110-01000000-00110000
[all …]
H A Dldnt1d.s6 // RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \
9 // RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \
12 // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
17 ldnt1d {z0.d, z8.d}, pn8/z, [x0, x0, lsl #3] // 10100001-00000000-01100000-00001000
18 // CHECK-INST: ldnt1d { z0.d, z8.d }, pn8/z, [x0, x0, lsl #3]
23 ldnt1d {z21.d, z29.d}, pn13/z, [x10, x21, lsl #3] // 10100001-00010101-01110101-01011101
24 // CHECK-INST: ldnt1d { z21.d, z29.d }, pn13/z, [x10, x21, lsl #3]
29 ldnt1d {z23.d, z31.d}, pn11/z, [x13, x8, lsl #3] // 10100001-00001000-01101101-10111111
30 // CHECK-INST: ldnt1d { z23.d, z31.d }, pn11/z, [x13, x8, lsl #3]
35 ldnt1d {z23.d, z31.d}, pn15/z, [sp, xzr, lsl #3] // 10100001-00011111-01111111-11111111
[all …]
H A Dst1d.s6 // RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=C…
8 // RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=C…
10 // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
15 st1d {z0.d, z8.d}, pn8, [x0, x0, lsl #3] // 10100001-00100000-01100000-00000000
16 // CHECK-INST: st1d { z0.d, z8.d }, pn8, [x0, x0, lsl #3]
21 st1d {z21.d, z29.d}, pn13, [x10, x21, lsl #3] // 10100001-00110101-01110101-01010101
22 // CHECK-INST: st1d { z21.d, z29.d }, pn13, [x10, x21, lsl #3]
27 st1d {z23.d, z31.d}, pn11, [x13, x8, lsl #3] // 10100001-00101000-01101101-10110111
28 // CHECK-INST: st1d { z23.d, z31.d }, pn11, [x13, x8, lsl #3]
33 st1d {z23.d, z31.d}, pn15, [sp, xzr, lsl #3] // 10100001-00111111-01111111-11110111
[all …]
/llvm-project/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/
H A Dneon-instructions.s6 abs v0.2d, v0.2d
14 addhn v0.2s, v0.2d, v0.2d
18 addhn2 v0.4s, v0.2d, v0.2d
20 addp v0.2d, v0.2d, v0.2d
57 cmle v0.2d, v0.2d, 0
65 dup v0.2d,x28
72 ext v0.16b, v0.16b, v0.16b, #3
73 ext v0.8b, v0.8b, v0.8b, #3
77 fabs v0.2d, v0.2d
87 facgt v0.2d, v0.2d, v0.2d
[all …]
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Daix-prefixed-instruction-boundary.mir3 # RUN: llvm-objdump -D -r --mcpu=pwr10 %t.o | FileCheck --check-prefix=DIS %s
47 # DIS-NEXT: 0: 38 60 00 02 li 3, 2
48 # DIS-NEXT: 4: 06 00 00 00 38 63 00 0d paddi 3, 3, 13, 0
49 # DIS-NEXT: c: 06 00 00 00 38 63 00 0d paddi 3, 3, 13, 0
50 # DIS-NEXT: 14: 06 00 00 00 38 63 00 0d paddi 3, 3, 13, 0
51 # DIS-NEXT: 1c: 06 00 00 00 38 63 00 0d paddi 3, 3, 13, 0
52 # DIS-NEXT: 24: 06 00 00 00 38 63 00 0d paddi 3, 3, 13, 0
53 # DIS-NEXT: 2c: 06 00 00 00 38 63 00 0d paddi 3, 3, 13, 0
54 # DIS-NEXT: 34: 06 00 00 00 38 63 00 0d paddi 3, 3, 13, 0
55 # DIS-NEXT: 3c: 60 00 00 00 nop
[all …]
/llvm-project/clang/test/Analysis/
H A Dcfg-rich-constructors.cpp27 // CHECK-NEXT: 2: (CXXConstructExpr, [B1.3], C)
28 // CHECK-NEXT: 3: new C([B1.2])
36 // CHECK-NEXT: 3: (CXXConstructExpr, [B1.4], C)
37 // CHECK-NEXT: 4: new C([B1.3])
46 // CHECK-NEXT: 2: (CXXConstructExpr, [B1.3], C)
47 // CHECK-NEXT: 3: new C([B1.2])
48 // CHECK-NEXT: 4: [B1.3] (ImplicitCastExpr, BitCast, void *)
77 // CHECK-NEXT: 3: [B1.2] (CXXConstructExpr, [B1.4], C)
85 // CHECK-NEXT: 2: (CXXConstructExpr, [B1.3], C)
86 // CHECK-NEXT: 3: new C([B1.2])
[all …]
/llvm-project/llvm/test/tools/llvm-mca/AArch64/A64FX/
H A DA64FX-neon-instructions.s6 abs v0.2d, v0.2d
14 addhn v0.2s, v0.2d, v0.2d
18 addhn2 v0.4s, v0.2d, v0.2d
20 addp v0.2d, v0.2d, v0.2d
57 cmle v0.2d, v0.2d, 0
65 dup v0.2d,x28
72 ext v0.16b, v0.16b, v0.16b, #3
73 ext v0.8b, v0.8b, v0.8b, #3
77 fabs v0.2d, v0.2d
87 facgt v0.2d, v0.2d, v0.2d
[all …]
/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/
H A DA510-neon-instructions.s6 abs v0.2d, v0.2d
14 addhn v0.2s, v0.2d, v0.2d
18 addhn2 v0.4s, v0.2d, v0.2d
20 addp v0.2d, v0.2d, v0.2d
57 cmle v0.2d, v0.2d, 0
65 dup v0.2d,x28
72 ext v0.16b, v0.16b, v0.16b, #3
73 ext v0.8b, v0.8b, v0.8b, #3
77 fabs v0.2d, v0.2d
87 facgt v0.2d, v0.2d, v0.2d
[all …]
H A DA55-neon-instructions.s6 abs v0.2d, v0.2d
14 addhn v0.2s, v0.2d, v0.2d
18 addhn2 v0.4s, v0.2d, v0.2d
20 addp v0.2d, v0.2d, v0.2d
57 cmle v0.2d, v0.2d, 0
65 dup v0.2d,x28
72 ext v0.16b, v0.16b, v0.16b, #3
73 ext v0.8b, v0.8b, v0.8b, #3
77 fabs v0.2d, v0.2d
87 facgt v0.2d, v0.2d, v0.2d
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dcomplex-deinterleaving-add-mull-fixed-fast.ll10 ; CHECK-NEXT: fcmla v4.2d, v0.2d, v2.2d, #0
11 ; CHECK-NEXT: fcmla v5.2d, v1.2d, v3.2d, #0
12 ; CHECK-NEXT: fcmla v4.2d, v0.2d, v2.2d, #90
13 ; CHECK-NEXT: fcmla v5.2d, v1.2d, v3.2d, #90
19 %strided.vec28 = shufflevector <4 x double> %a, <4 x double> poison, <2 x i32> <i32 1, i32 3>
21 %strided.vec31 = shufflevector <4 x double> %b, <4 x double> poison, <2 x i32> <i32 1, i32 3>
25 %3 = fmul fast <2 x double> %strided.vec30, %strided.vec
27 %strided.vec34 = shufflevector <4 x double> %c, <4 x double> poison, <2 x i32> <i32 1, i32 3>
28 %4 = fadd fast <2 x double> %strided.vec33, %3
32 …leaved.vec = shufflevector <2 x double> %6, <2 x double> %7, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
[all …]
H A Dcomplex-deinterleaving-add-mull-fixed-contract.ll10 ; CHECK-NEXT: zip2 v4.2d, v2.2d, v3.2d
11 ; CHECK-NEXT: zip2 v5.2d, v0.2d, v1.2d
12 ; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d
13 ; CHECK-NEXT: zip1 v2.2d, v2.2d, v3.2d
14 ; CHECK-NEXT: fmul v1.2d, v5.2d, v4.2d
15 ; CHECK-NEXT: fmul v3.2d, v0.2d, v4.2d
16 ; CHECK-NEXT: fneg v1.2d, v1.2d
17 ; CHECK-NEXT: fmla v3.2d, v2.2d, v5.2d
18 ; CHECK-NEXT: fmla v1.2d, v2.2d, v0.2d
19 ; CHECK-NEXT: fadd v1.2d, v2.2d, v1.2d
[all …]
H A Dvector-popcnt-128-ult-ugt.ll12 …%3 = icmp ugt <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 …
13 %4 = sext <16 x i1> %3 to <16 x i8>
25 …%3 = icmp ult <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 …
26 %4 = sext <16 x i1> %3 to <16 x i8>
38 …%3 = icmp ugt <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 …
39 %4 = sext <16 x i1> %3 to <16 x i8>
46 ; CHECK-NEXT: movi v1.16b, #3
51 …%3 = icmp ult <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 …
52 %4 = sext <16 x i1> %3 to <16 x i8>
59 ; CHECK-NEXT: movi v1.16b, #3
[all …]
/llvm-project/libcxx/test/std/containers/views/mdspan/extents/
H A Dtypes.pass.cpp59 constexpr size_t D = std::dynamic_extent; in test()
60 testExtents<T, D>(); in test()
61 testExtents<T, 3>(); in test()
62 testExtents<T, 3, 3>(); in test()
63 testExtents<T, 3, D>(); in test()
64 testExtents<T, D, 3>(); in test()
65 testExtents<T, D, in test()
57 constexpr size_t D = std::dynamic_extent; test() local
[all...]
H A DCtorTestCombinations.h62 constexpr size_t D = std::dynamic_extent; in test()
66 test_construction<std::extents<T, 3>, Test>(std::array<TArg, 1>{3}); in test()
67 test_construction<std::extents<T, D>, Test>(std::array<TArg, 1>{3}); in test()
69 test_construction<std::extents<T, 3, 7>, Test>(std::array<TArg, 2>{3, 7}); in test()
70 test_construction<std::extents<T, 3, D>, Test>(std::array<TArg, 2>{3, in test()
61 constexpr size_t D = std::dynamic_extent; test() local
[all...]
/llvm-project/llvm/test/MC/Mips/
H A Dtarget-soft-float.s12 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
14 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
16 ceil.l.d $f2, $f2
17 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
19 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
20 cvt.d.l $f2, $f2
21 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
22 cvt.l.d $f2, $f2
23 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
25 # R2: :[[@LINE-1]]:3
[all...]

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