| /freebsd-src/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | dma.txt | 4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
[all …]
|
| /freebsd-src/lib/libpmc/ |
| H A D | pmc.corei7uc.3 | 8 .\" 2. Redistributions in binary form must reproduce the above copyright
40 CPUs contain PMCs conforming to version 2 of the
43 These CPUs contain 2 classes of PMCs:
44 .Bl -tag -width "Li PMC_CLASS_UCP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
59 .%T "Volume 3B: System Programming Guide, Part 2"
60 .%N "Order Number: 253669-033US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
[all …]
|
| H A D | pmc.westmereuc.3 | 8 .\" 2. Redistributions in binary form must reproduce the above copyright
40 CPUs contain PMCs conforming to version 2 of the
44 .Bl -tag -width "Li PMC_CLASS_UCP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
59 .%T "Volume 3B: System Programming Guide, Part 2"
60 .%N "Order Number: 253669-033US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
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|
| /freebsd-src/sys/contrib/device-tree/Bindings/input/ |
| H A D | iqs626a.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS626A is a 14-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
19 - $ref: touchscreen/touchscreen.yaml#
31 "#address-cells":
34 "#size-cells":
37 azoteq,suspend-mode:
[all …]
|
| H A D | iqs269a.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 - $ref: input.yaml#
16 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
17 additional Hall-effect and inductive sensing capabilities.
24 - azoteq,iqs269a
25 - azoteq,iqs269a-00
26 - azoteq,iqs269a-d0
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/iio/dac/ |
| H A D | adi,ad5770r.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandru Tachici <alexandru.tachici@analog.com>
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD5770R.pdf
21 - adi,ad5770r
26 avdd-supply:
31 iovdd-supply:
35 vref-supply:
41 adi,external-resistor:
[all …]
|
| H A D | ad5755.txt | 1 * Analog Devices AD5755 IIO Multi-Channel DAC Linux Driver
4 - compatible: Has to contain one of the following:
6 adi,ad5755-1
11 - reg: spi chip select number for the device
12 - spi-cpha or spi-cpol: is the only modes that is supported
15 - spi-max-frequency: Definition as per
16 Documentation/devicetree/bindings/spi/spi-bus.txt
19 See include/dt-bindings/iio/ad5755.h
20 - adi,ext-dc-dc-compenstation-resistor: boolean set if the hardware have an
23 - adi,dc-dc-phase:
[all …]
|
| H A D | adi,ad5755.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD5755 Multi-Channel DAC
10 - Sean Nyekjaer <sean.nyekjaer@prevas.dk>
15 - adi,ad5755
16 - adi,ad5755-1
17 - adi,ad5757
18 - adi,ad5735
19 - adi,ad5737
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | qcom,pm8018-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,pm8018-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
19 - qcom,pm8018-adc
20 - qcom,pm8038-adc
21 - qcom,pm8058-adc
22 - qcom,pm8921-adc
29 xoadc-ref-supply:
[all …]
|
| H A D | qcom,pm8xxx-xoadc.txt | 8 - compatible: should be one of:
9 "qcom,pm8018-adc"
10 "qcom,pm8038-adc"
11 "qcom,pm8058-adc"
12 "qcom,pm8921-adc"
14 - reg: should contain the ADC base address in the PMIC, typically
17 - xoadc-ref-supply: should reference a regulator that can supply
22 iio-bindings.txt for more details, but notice that this particular
24 identifying each ADC channel:
26 - #address-cells: should be set to <2>, the first cell is the
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/sound/ |
| H A D | tlv320adcx140.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
16 converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
[all …]
|
| H A D | st,sta32x.txt | 7 - compatible: "st,sta32x"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - Vdda-supply: regulator spec, providing 3.3V
17 - Vdd3-supply: regulator spec, providing 3.3V
18 - Vcc-supply: regulator spec, providing 5V - 26V
22 - clocks, clock-names: Clock specifier for XTI input clock.
24 and disabled when it is removed. The 'clock-names' must be set to 'xti'.
26 - st,output-conf: number, Selects the output configuration:
[all …]
|
| H A D | st,sta350.txt | 7 - compatible: "st,sta350"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - vdd-dig-suppl
[all...] |
| /freebsd-src/sys/contrib/device-tree/Bindings/dma/ |
| H A D | stericsson,dma40.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
24 2: SD/MMC controller 1 (unused)
25 3: SD/MMC controller 2 (unused)
[all …]
|
| H A D | ste-dma40.txt | 4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
19 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
[all …]
|
| /freebsd-src/sys/dts/powerpc/ |
| H A D | p3041si.dtsi | 4 * Copyright 2010-2011 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
35 /dts-v1/;
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
102 #address-cells = <1>;
103 #size-cells = <0>;
108 bus-frequency = <749999996>;
109 next-level-cache = <&L2_0>;
[all …]
|
| H A D | p2041si.dtsi | 20 * Foundation, either version 2 of that License or (at your option) any
35 /dts-v1/;
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
101 #address-cells = <1>;
102 #size-cells = <0>;
107 bus-frequency = <749999996>;
108 next-level-cache = <&L2_0>;
109 L2_0: l2-cache {
[all …]
|
| H A D | p5020si.dtsi | 4 * Copyright 2010-2011 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
35 /dts-v1/;
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
108 #address-cells = <1>;
109 #size-cells = <0>;
114 bus-frequency = <799999998>;
115 next-level-cache = <&L2_0>;
[all …]
|
| /freebsd-src/sys/contrib/device-tree/src/powerpc/fsl/ |
| H A D | elo3-dma-1.dtsi | 20 * Foundation, either version 2 of that License or (at your option) any
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
45 interrupts = <32 2 0 0>;
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
50 interrupts = <33 2 0 0>;
[all …]
|
| H A D | elo3-dma-0.dtsi | 20 * Foundation, either version 2 of that License or (at your option) any
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
45 interrupts = <28 2 0 0>;
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
50 interrupts = <29 2 0 0>;
[all …]
|
| H A D | elo3-dma-2.dtsi | 20 * Foundation, either version 2 of that License or (at your option) any
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
45 interrupts = <464 2 0 0>;
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
50 interrupts = <465 2 0 0>;
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | arm,mhuv2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tushar Khandelwal <tushar.khandelwal@arm.com>
11 - Viresh Kumar <viresh.kumar@linaro.org>
14 The Arm Message Handling Unit (MHU) Version 2 is a mailbox controller that has
15 between 1 and 124 channel windows (each 32-bit wide) to provide unidirectional
16 communication with remote processor(s), where the number of channel windows
33 - Data-transfer: Each transfer is made of one or more words, using one or more
34 channel windows.
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/dma/ti/ |
| H A D | k3-bcdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-bcdma.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Peter Ujfalusi <peter.ujfalusi@gmail.com>
16 mode channels of K3 UDMA-P.
20 optional triggers a block copy channel can service peripherals by accessing
23 Split channels can be used to service PSI-L based peripherals.
24 The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
25 with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
[all …]
|
| /freebsd-src/sys/contrib/openzfs/man/man5/ |
| H A D | vdev_id.conf.5 | 34 .Bl -tag -width "-h"
41 A defined alias takes precedence over a topology-derived name, but the
49 .Pa /dev/disk/by-vdev .
56 .It Sy channel [ Ns Ar pci_slot ] Ar port Ar name
57 Maps a physical path to a channel name (typically representing a single
62 .Pa /dev/by-enclosure
74 .Pa /dev/by-enclosure/ Ns Ao Ar prefix Ac Ns - N
[all...] |
| /freebsd-src/sys/amd64/vmm/io/ |
| H A D | vatpit.c | 1 /*-
12 * 2. Redistributions in binary form must reproduce the above copyright
52 #define VATPIT_LOCK(vatpit) mtx_lock_spin(&((vatpit)->mtx))
53 #define VATPIT_UNLOCK(vatpit) mtx_unlock_spin(&((vatpit)->mtx))
54 #define VATPIT_LOCKED(vatpit) mtx_owned(&((vatpit)->mtx))
73 #define TIMER_DIV(freq, hz) (((freq) + (hz) / 2) / (hz))
80 struct channel {
84 uint8_t cr[2];
85 uint8_t ol[2];
102 struct channel channe
79 struct channel { global() struct
101 struct channel channel[3]; global() member
122 vatpit_get_out(struct vatpit * vatpit,int channel) vatpit_get_out() argument
247 pit_readback1(struct vatpit * vatpit,int channel,uint8_t cmd) pit_readback1() argument
481 struct channel *channel; vatpit_snapshot() local
[all...] |