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/llvm-project/mlir/test/Integration/GPU/CUDA/TensorCore/
H A Dwmma-matmul-f32.mlir10 %0 = memref.alloc() : memref<16x16xf16>
11 %22 = memref.alloc() : memref<16x16xf32>
12 %1 = memref.alloc() : memref<16x16xf32>
17 %c16 = arith.constant 16 : index
24 memref.store %f1, %0[%arg0, %arg1] : memref<16x16xf16>
30 memref.store %f0, %22[%arg0, %arg1] : memref<16x16xf32>
34 %2 = memref.cast %0 : memref<16x16xf16> to memref<*xf16>
35 %33 = memref.cast %22 : memref<16x16xf32> to memref<*xf32>
36 %3 = memref.cast %1 : memref<16x16xf32> to memref<*xf32>
42 %A = gpu.subgroup_mma_load_matrix %0[%c0, %c0] {leadDimension = 16
[all...]
/llvm-project/llvm/test/Analysis/CostModel/X86/
H A Dmul-latency.ll16 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = mul i64 undef, 16
17 ; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2i64 = mul <2 x i64> undef, <i64 8, i64 16>
18 ; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4i64 = mul <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
19 ; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8i64 = mul <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
20 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = mul i32 undef, 16
21 ; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4i32 = mul <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
22 ; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8i32 = mul <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
23 ; SSE2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16i32 = mul <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i3
[all...]
H A Dmul.ll16 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = mul i64 undef, 16
17 ; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2i64 = mul <2 x i64> undef, <i64 8, i64 16>
18 ; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4i64 = mul <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
19 ; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8i64 = mul <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
20 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = mul i32 undef, 16
21 ; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4i32 = mul <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
22 ; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8i32 = mul <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
23 ; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16i32 = mul <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i3
[all...]
H A Dmul-sizelatency.ll16 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = mul i64 undef, 16
17 ; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2i64 = mul <2 x i64> undef, <i64 8, i64 16>
18 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V4i64 = mul <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
19 ; SSE2-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8i64 = mul <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
20 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = mul i32 undef, 16
21 ; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4i32 = mul <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
22 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8i32 = mul <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
23 ; SSE2-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16i32 = mul <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i3
[all...]
H A Dmul-codesize.ll16 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = mul i64 undef, 16
17 ; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2i64 = mul <2 x i64> undef, <i64 8, i64 16>
18 ; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V4i64 = mul <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
19 ; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V8i64 = mul <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
20 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = mul i32 undef, 16
21 ; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4i32 = mul <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
22 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8i32 = mul <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
23 ; SSE2-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16i32 = mul <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i3
[all...]
H A Drem-latency.ll23 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = srem <16 x i32> undef, undef
26 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i16 = srem <16 x i16> undef, undef
29 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i8 = srem <16 x i8> undef, undef
42 %V16i32 = srem <16 x i32> undef, undef
46 %V16i16 = srem <16 x i16> undef, undef
50 %V16i8 = srem <16 x i8> undef, undef
66 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = urem <16 x i32> undef, undef
69 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i16 = urem <16 x i16> undef, undef
72 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i8 = urem <16 x i8> undef, undef
85 %V16i32 = urem <16
[all...]
H A Drem-sizelatency.ll23 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = srem <16 x i32> undef, undef
26 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i16 = srem <16 x i16> undef, undef
29 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i8 = srem <16 x i8> undef, undef
42 %V16i32 = srem <16 x i32> undef, undef
46 %V16i16 = srem <16 x i16> undef, undef
50 %V16i8 = srem <16 x i8> undef, undef
66 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = urem <16 x i32> undef, undef
69 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i16 = urem <16 x i16> undef, undef
72 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i8 = urem <16 x i8> undef, undef
85 %V16i32 = urem <16
[all...]
H A Drem-codesize.ll23 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = srem <16 x i32> undef, undef
26 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i16 = srem <16 x i16> undef, undef
29 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i8 = srem <16 x i8> undef, undef
42 %V16i32 = srem <16 x i32> undef, undef
46 %V16i16 = srem <16 x i16> undef, undef
50 %V16i8 = srem <16 x i8> undef, undef
66 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = urem <16 x i32> undef, undef
69 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i16 = urem <16 x i16> undef, undef
72 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i8 = urem <16 x i8> undef, undef
85 %V16i32 = urem <16
[all...]
H A Ddiv-latency.ll23 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = sdiv <16 x i32> undef, undef
26 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i16 = sdiv <16 x i16> undef, undef
29 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i8 = sdiv <16 x i8> undef, undef
42 %V16i32 = sdiv <16 x i32> undef, undef
46 %V16i16 = sdiv <16 x i16> undef, undef
50 %V16i8 = sdiv <16 x i8> undef, undef
66 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = udiv <16 x i32> undef, undef
69 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i16 = udiv <16 x i16> undef, undef
72 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i8 = udiv <16 x i8> undef, undef
85 %V16i32 = udiv <16
[all...]
H A Ddiv-sizelatency.ll23 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = sdiv <16 x i32> undef, undef
26 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i16 = sdiv <16 x i16> undef, undef
29 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i8 = sdiv <16 x i8> undef, undef
42 %V16i32 = sdiv <16 x i32> undef, undef
46 %V16i16 = sdiv <16 x i16> undef, undef
50 %V16i8 = sdiv <16 x i8> undef, undef
66 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = udiv <16 x i32> undef, undef
69 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i16 = udiv <16 x i16> undef, undef
72 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i8 = udiv <16 x i8> undef, undef
85 %V16i32 = udiv <16
[all...]
H A Ddiv-codesize.ll23 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = sdiv <16 x i32> undef, undef
26 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i16 = sdiv <16 x i16> undef, undef
29 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i8 = sdiv <16 x i8> undef, undef
42 %V16i32 = sdiv <16 x i32> undef, undef
46 %V16i16 = sdiv <16 x i16> undef, undef
50 %V16i8 = sdiv <16 x i8> undef, undef
66 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = udiv <16 x i32> undef, undef
69 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i16 = udiv <16 x i16> undef, undef
72 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i8 = udiv <16 x i8> undef, undef
85 %V16i32 = udiv <16
[all...]
H A Ddiv.ll23 ; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V16i32 = sdiv <16 x i32> undef, undef
26 ; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V16i16 = sdiv <16 x i16> undef, undef
29 ; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V16i8 = sdiv <16 x i8> undef, undef
42 %V16i32 = sdiv <16 x i32> undef, undef
46 %V16i16 = sdiv <16 x i16> undef, undef
50 %V16i8 = sdiv <16 x i8> undef, undef
66 ; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V16i32 = udiv <16 x i32> undef, undef
69 ; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V16i16 = udiv <16 x i16> undef, undef
72 ; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V16i8 = udiv <16 x i8> undef, undef
85 %V16i32 = udiv <16
[all...]
H A Drem.ll23 ; SSE-NEXT: Cost Model: Found an estimated cost of 960 for instruction: %V16i32 = srem <16 x i32> undef, undef
26 ; SSE-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %V16i16 = srem <16 x i16> undef, undef
29 ; SSE-NEXT: Cost Model: Found an estimated cost of 1600 for instruction: %V16i8 = srem <16 x i8> undef, undef
42 ; AVX-NEXT: Cost Model: Found an estimated cost of 960 for instruction: %V16i32 = srem <16 x i32> undef, undef
45 ; AVX-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %V16i16 = srem <16 x i16> undef, undef
48 ; AVX-NEXT: Cost Model: Found an estimated cost of 1600 for instruction: %V16i8 = srem <16 x i8> undef, undef
61 ; AVX512-NEXT: Cost Model: Found an estimated cost of 960 for instruction: %V16i32 = srem <16 x i32> undef, undef
64 ; AVX512-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %V16i16 = srem <16 x i16> undef, undef
67 ; AVX512-NEXT: Cost Model: Found an estimated cost of 1600 for instruction: %V16i8 = srem <16 x i8> undef, undef
80 %V16i32 = srem <16
[all...]
/llvm-project/llvm/test/CodeGen/Hexagon/
H A Dreg-scavenger-valid-slot.ll39 %asmresult16 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 16
52 %1 = tail call { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16
[all...]
H A Dreg-scavengebug.ll7 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #0
10 declare <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32>) #0
13 declare <32 x i32> @llvm.hexagon.V6.vmpyubv(<16 x i32>, <16 x i32>) #0
16 declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #0
19 declare <16 x i32> @llvm.hexagon.V6.vaddh(<16
[all...]
/llvm-project/llvm/test/Analysis/CostModel/AMDGPU/
H A Dmul.ll13 ; ALL-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4i32 = mul <4 x i32> undef, undef
25 ; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8i32 = mul <8 x i32> undef, undef
68 ; SLOW16-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v3i16 = mul <3 x i16> undef, undef
69 ; SLOW16-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4i16 = mul <4 x i16> undef, undef
71 ; SLOW16-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v16i16 = mul <16 x i16> undef, undef
80 ; FAST16-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v5i16 = mul <5 x i16> undef, undef
81 ; FAST16-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16i16 = mul <16 x i16> undef, undef
90 ; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v5i16 = mul <5 x i16> undef, undef
91 ; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16i16 = mul <16 x i16> undef, undef
101 ; FAST16-SIZE-NEXT: Cost Model: Found an estimated cost of 16 fo
[all...]
H A Ddiv.ll22 ; FAST-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V16i32 = sdiv <16 x i32> undef, undef
25 ; FAST-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V16i16 = sdiv <16 x i16> undef, undef
28 ; FAST-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V16i8 = sdiv <16 x i8> undef, undef
41 ; SLOW-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V16i32 = sdiv <16 x i32> undef, undef
43 ; SLOW-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8i16 = sdiv <8 x i16> undef, undef
44 ; SLOW-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16i16 = sdiv <16 x i16> undef, undef
47 ; SLOW-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16i8 = sdiv <16
[all...]
H A Drem.ll22 ; FAST-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V16i32 = srem <16 x i32> undef, undef
25 ; FAST-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V16i16 = srem <16 x i16> undef, undef
28 ; FAST-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V16i8 = srem <16 x i8> undef, undef
41 ; SLOW-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V16i32 = srem <16 x i32> undef, undef
44 ; SLOW-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V16i16 = srem <16 x i16> undef, undef
47 ; SLOW-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %V16i8 = srem <16 x i8> undef, undef
60 ; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i32 = srem <16 x i32> undef, undef
63 ; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i16 = srem <16 x i16> undef, undef
66 ; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16i8 = srem <16
[all...]
/llvm-project/llvm/test/Analysis/CostModel/AArch64/
H A Ddiv.ll4 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
17 ; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %V16i32 = sdiv <16 x i32> undef, undef
22 ; CHECK-NEXT: Cost Model: Found an estimated cost of 176 for instruction: %V16i16 = sdiv <16 x i16> undef, undef
28 ; CHECK-NEXT: Cost Model: Found an estimated cost of 168 for instruction: %V16i8 = sdiv <16 x i8> undef, undef
44 %V16i32 = sdiv <16 x i32> undef, undef
50 %V16i16 = sdiv <16 x i16> undef, undef
57 %V16i8 = sdiv <16 x i8> undef, undef
75 ; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %V16i32 = udiv <16 x i32> undef, undef
80 ; CHECK-NEXT: Cost Model: Found an estimated cost of 176 for instruction: %V16i16 = udiv <16 x i16> undef, undef
86 ; CHECK-NEXT: Cost Model: Found an estimated cost of 168 for instruction: %V16i8 = udiv <16
[all...]
H A Drem.ll4 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
17 ; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V16i32 = srem <16 x i32> undef, undef
22 ; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V16i16 = srem <16 x i16> undef, undef
28 ; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V16i8 = srem <16 x i8> undef, undef
44 %V16i32 = srem <16 x i32> undef, undef
50 %V16i16 = srem <16 x i16> undef, undef
57 %V16i8 = srem <16 x i8> undef, undef
75 ; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V16i32 = urem <16 x i32> undef, undef
80 ; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V16i16 = urem <16 x i16> undef, undef
86 ; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V16i8 = urem <16
[all...]
/llvm-project/llvm/test/CodeGen/X86/
H A Davx512-vpternlog-commute.ll6 declare <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i32)
8 define <16 x i32> @vpternlog_v16i32_012(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2) {
13 …%1 = call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x…
14 ret <16 x i32> %1
17 define <16 x i32> @vpternlog_v16i32_102(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2) {
22 …%1 = call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %x1, <16 x i32> %x0, <16 x i32> %x…
23 ret <16 x i32> %1
26 define <16 x i32> @vpternlog_v16i32_210(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2) {
31 …%1 = call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %x2, <16 x i32> %x1, <16 x i32> %x…
32 ret <16 x i32> %1
[all …]
/llvm-project/llvm/test/MC/AArch64/
H A Dneon-tbl.s9 tbl v0.8b, { v1.16b }, v2.8b
10 tbl v0.8b, { v1.16b, v2.16b }, v2.8b
11 tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b
12 tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b
13 tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b
15 // CHECK: tbl v0.8b, { v1.16b }, v2.8b // encoding: [0x20,0x00,0x02,0x0e]
16 // CHECK: tbl v0.8b, { v1.16b, v2.16b }, v2.8b // encoding: [0x20,0x20,0x02,0x0e]
17 // CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b // encoding: [0x20,0x40,0x02,0x0e]
18 // CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b // encoding: [0x20,0x60,0x02,0x0e]
19 // CHECK: tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b // encoding: [0xe0,0x63,0x02,0x0e]
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dmisched-fusion-aes.ll24 declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %d, <16 x i8> %k)
25 declare <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %d)
26 declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %d, <16 x i8> %k)
27 declare <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %d)
29 define void @aesea(ptr %a0, ptr %b0, ptr %c0, <16 x i8> %d, <16 x i8> %e) {
30 %d0 = load <16 x i8>, ptr %a0
31 %a1 = getelementptr inbounds <16 x i8>, ptr %a0, i64 1
32 %d1 = load <16 x i8>, ptr %a1
33 %a2 = getelementptr inbounds <16 x i8>, ptr %a0, i64 2
34 %d2 = load <16 x i8>, ptr %a2
[all …]
/llvm-project/llvm/test/CodeGen/ARM/
H A Dmisched-fusion-aes.ll3 declare <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d, <16 x i8> %k)
4 declare <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %d)
5 declare <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d, <16 x i8> %k)
6 declare <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %d)
8 define void @aesea(ptr %a0, ptr %b0, ptr %c0, <16 x i8> %d, <16 x i8> %e) {
9 %d0 = load <16 x i8>, ptr %a0
10 %a1 = getelementptr inbounds <16 x i8>, ptr %a0, i64 1
11 %d1 = load <16 x i8>, ptr %a1
12 %a2 = getelementptr inbounds <16 x i8>, ptr %a0, i64 2
13 %d2 = load <16 x i8>, ptr %a2
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/llvm-project/llvm/test/CodeGen/SystemZ/
H A Dframe-19.ll5 ; We need to allocate a 16-byte spill slot and save the 8 call-saved FPRs.
6 ; The frame size should be exactly 160 + 16 + 8 * 8 = 240.
30 %v0 = load volatile <16 x i8>, ptr %ptr
31 %v1 = load volatile <16 x i8>, ptr %ptr
32 %v2 = load volatile <16 x i8>, ptr %ptr
33 %v3 = load volatile <16 x i8>, ptr %ptr
34 %v4 = load volatile <16 x i8>, ptr %ptr
35 %v5 = load volatile <16 x i8>, ptr %ptr
36 %v6 = load volatile <16 x i8>, ptr %ptr
37 %v7 = load volatile <16 x i8>, ptr %ptr
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