| /freebsd-src/sys/arm/nvidia/tegra124/ |
| H A D | tegra124_xusbpadctl.c | 1 /*-
8 * 1. Redistributions of source code must retain the above copyright
49 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
65 #define USB2_PORT_CAP_ULPI_PORT_INTERNAL (1 << 25)
66 #define USB2_PORT_CAP_ULPI_PORT_CAP (1 << 24)
67 #define USB2_PORT_CAP_PORT_REVERSE_ID(p) (1 << (3 + (p) * 4))
68 #define USB2_PORT_CAP_PORT_INTERNAL(p) (1 << (2 + (p) * 4))
76 #define SS_PORT_MAP_PORT_INTERNAL(p) (1 << (3 + (p) * 4))
80 #define ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
81 #define ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
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| /freebsd-src/sys/contrib/alpine-hal/ |
| H A D | al_hal_serdes_25g.c | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
73 struct al_serdes_c_regs __iomem *regs_base = obj->regs_base; in al_serdes_25g_reg_read()
94 return -1; in al_serdes_25g_reg_read()
97 al_reg_write32(®s_base->gen.reg_addr, addr); in al_serdes_25g_reg_read()
98 *data = al_reg_read32(®s_base->gen.reg_data); in al_serdes_25g_reg_read()
112 struct al_serdes_c_regs __iomem *regs_base = obj->regs_base; in al_serdes_25g_reg_write()
132 return -1; in al_serdes_25g_reg_write()
135 al_reg_write32(®s_base->gen.reg_addr, addr); in al_serdes_25g_reg_write()
136 al_reg_write32(®s_base->gen.reg_data, (data | SERDES_C_GEN_REG_DATA_STRB_MASK)); in al_serdes_25g_reg_write()
202 return -1; in al_serdes_25g_mailbox_send_cmd()
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| H A D | al_hal_serdes_interface.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
120 * Parallel loopback from the PMA receive lane data ports, to the
121 * transmit lane data ports
178 * Tx de-emphasis parameters
182 AL_SERDES_TX_DEEMP_C_PLUS, /*< c(1) */
183 AL_SERDES_TX_DEEMP_C_MINUS, /*< c(-1) */
196 * Transmit Amplitude control signal. Used to define the full-scale
198 * 000 - Not Supported
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| H A D | al_hal_serdes_hssp.c | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
51 /* c(+1) configurations */
56 /* c(-1) configurations */
111 * Lane Rx rate change software flow disable
115 enum al_serdes_lane lane);
124 * Lane Rx rate change software flow enable if all conditions met
128 enum al_serdes_lane lane);
508 enum al_serdes_lane lane) in al_serdes_lane_rx_rate_change_sw_flow_en() argument
510 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 201, 0xfc); in al_serdes_lane_rx_rate_change_sw_flow_en()
511 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 202, 0xff); in al_serdes_lane_rx_rate_change_sw_flow_en()
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| H A D | al_hal_serdes_internal_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
44 * Per lane register fields
47 * RX and TX lane hard reset
48 * 0 - Hard reset is asserted
49 * 1 - Hard reset is de-asserted
57 * RX and TX lane hard reset control
58 * 0 - Hard reset is taken from the interface pins
59 * 1 - Hard reset is taken from registers
66 /* RX lane power state control */
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| H A D | al_hal_serdes_hssp_internal_regs.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
43 * Per lane register fields
46 * RX and TX lane hard reset
47 * 0 - Hard reset is asserted
48 * 1 - Hard reset is de-asserted
56 * RX and TX lane hard reset control
57 * 0 - Hard reset is taken from the interface pins
58 * 1 - Hard reset is taken from registers
65 /* RX lane power state control */
74 /* TX lane power state control */
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64PerfectShuffle.h | 1 //===-- AArch64PerfectShuffle.h - AdvSIMD Perfect Shuffle Table -------
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| /freebsd-src/sys/arm64/nvidia/tegra210/ |
| H A D | tegra210_xusbpadctl.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
9 * 1. Redistributions of source code must retain the above copyright
50 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
56 #define FUSE_SKU_CALIB_0_HS_CURR_LEVEL_123(x, i) (((x) >> (11 + ((i) - 1) * 6)) & 0x3F);
68 #define USB2_PORT_CAP_PORT_REVERSE_ID(p) (1 << (3 + (p) * 4))
69 #define USB2_PORT_CAP_PORT_INTERNAL(p) (1 << (2 + (p) * 4))
77 #define SS_PORT_MAP_PORT_INTERNAL(p) (1 << (3 + (p) * 4))
81 #define ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
82 #define ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
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| /freebsd-src/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_eth_kr.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
38 * Ethernet KR auto-neg and link-training driver API
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
59 /* AN (Auto-negotiation) Advertisement Registers */
68 /* Set to 1 to indicate a Remote Fault condition.
73 /* Set to 1 to indicate that the device has next pages to send.
82 #define AL_ETH_AN_TECH_10GBASE_KX4 AL_BIT(1)
116 C72_CSTATE_UPDATED = 1,
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| H A D | al_hal_eth_kr.c | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
41 * @brief KR HAL driver for main functions (auto-neg, Link Training)
81 [AL_ETH_KR_AN_STATUS] = {1 , 0x4},
117 /* register 1 */
144 /* register 1 */
161 #define AL_ETH_KR_PMD_CONTROL_ENABLE 1
164 #define AL_ETH_KR_PMD_STATUS_RECEIVER_FRAME_LOCK_SHIFT 1
212 enum al_eth_an_lt_lane lane) in al_eth_an_lt_reg_read() argument
217 if (adapter->rev_id < AL_ETH_REV_ID_3) { in al_eth_an_lt_reg_read()
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| H A D | al_hal_eth_mac_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
398 /* [0x20] 1/2.5/10G MAC external configuration */
400 /* [0x24] 1/2.5/10G MAC status */
412 /* [0x3c] MDIO control register for MDIO interface 1 */
414 /* [0x40] MDIO information register for MDIO interface 1 */
422 /* [0x50] Reserved 1 out */
426 /* [0x58] Reserved 1 in */
611 * [0x7c] SERDES 32-bit interface shift configuration (when swap is
616 * [0x80] SERDES 32-bit interface shift configuration (when swap is
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| /freebsd-src/sys/contrib/device-tree/Bindings/usb/ |
| H A D | onnn,nb7vpq904m.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schema
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| /freebsd-src/sys/arm64/rockchip/ |
| H A D | rk_typec_phy.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
9 * 1. Redistributions of source code must retain the above copyright
56 #define USB3OTG_CON1_U3_DIS (1 << 0)
60 #define USB3PHY_CON0_USB2_ONLY (1 << 3)
84 #define TX_TXCC_MGNFS_MULT_000(lane) ((0x4050 | ((lane) << 9)) << 2) argument
85 #define XCVR_DIAG_BIDI_CTRL(lane) ((0x40e8 | ((lane) << 9)) << 2) argument
86 #define XCVR_DIAG_LANE_FCM_EN_MGN(lane) ((0x40f2 | ((lane) << 9)) << 2) argument
87 #define TX_PSC_A0(lane) ((0x4100 | ((lane) << 9)) << 2) argument
88 #define TX_PSC_A1(lane) ((0x4101 | ((lane) << 9)) << 2) argument
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| /freebsd-src/sys/contrib/device-tree/Bindings/media/ |
| H A D | video-interfaces.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
35 endpoint@1 { ... };
37 port@1 { ... };
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| /freebsd-src/sys/dev/drm2/ |
| H A D | drm_dp_helper.c | 39 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
43 int lane) in dp_get_lane_status() argument
45 int i = DP_LANE0_1_STATUS + (lane >> 1); in dp_get_lane_status()
46 int s = (lane & 1) * 4; in dp_get_lane_status()
56 int lane; in drm_dp_channel_eq_ok() local
62 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
63 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_channel_eq_ok()
74 int lane; in drm_dp_clock_recovery_ok() local
77 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
78 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_clock_recovery_ok()
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| /freebsd-src/sys/contrib/device-tree/Bindings/media/i2c/ |
| H A D | st,st-mipid02.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
11 - Sylvain Petinot <sylvain.petinot@foss.st.com>
14 MIPID02 has two CSI-2 input ports, only one of those ports can be
15 active at a time. Active port input stream will be de-serialized
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
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| H A D | st,st-mipid02.txt | 1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
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| /freebsd-src/contrib/arm-optimized-routines/math/aarch64/ |
| H A D | v_powf.c | |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 1 //===-- ARMInstrNEON.td - NEON support for ARM -------
[all...] |
| /freebsd-src/lib/libpmc/pmu-events/arch/x86/tremontx/ |
| H A D | uncore-other.json | 4 "Counter": "0,1,2,3",
7 "PerPkg": "1",
11 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
12 "Counter": "0,1,2,3",
17 "PerPkg": "1",
23 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
24 "Counter": "0,1,2,3",
29 "PerPkg": "1",
36 "Counter": "0,1,2,3",
41 "PerPkg": "1",
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| /freebsd-src/sys/dev/hwpmc/ |
| H A D | hwpmc_ppc970.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * 1. Redistributions of source code must retain the above copyright
44 /* MMCR0, PMC1 is 8 bytes in, PMC2 is 1 byte in. */
46 ((r & ~(0x1f << (7 * (1 - i) + 1))) | (x << (7 * (1 - i) + 1)))
47 /* MMCR1 has 6 PMC*SEL items (PMC3->PMC8), in sequence. */
49 ((r & ~(0x1f << (5 * (7 - i) + 2))) | (x << (5 * (7 - i) + 2)))
56 * Encoding 00 000 -- Add byte lane bit counters
57 * MMCR1[24:31] -- select bit matching PMC being an adder.
59 * PMCxSEL: 1x -- select from byte lane: 10 == lower lane (0/1), 11 == upper
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| /freebsd-src/sys/contrib/device-tree/Bindings/phy/ |
| H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
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|
| H A D | phy-mvebu-comphy.txt | 2 --------------------
12 - compatible: should be one of:
13 * "marvell,comphy-cp110" for Armada 7k/8k
14 * "marvell,comphy-a3700" for Armada 3700
15 - reg: should contain the COMPHY register(s) location(s) and length(s).
16 * 1 entry for Armada 7k/8k
17 * 4 entries for Armada 3700 along with the corresponding reg-names
20 * Lane 1 (PCIe/GbE)
21 * Lane 0 (USB3/GbE)
22 * Lane 2 (SATA/USB3)
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| H A D | phy-cadence-sierra.txt | 2 -----------------------
5 - compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
6 Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
7 - resets: Must contain an entry for each in reset-names.
9 - reset-names: Must include "sierra_reset" and "sierra_apb".
13 - reg: register range for the PHY.
14 - #address-cells: Must be 1
15 - #size-cells: Must be 0
18 - clocks: Must contain an entry in clock-names.
19 See ../clocks/clock-bindings.txt for details.
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUAtomicOptimizer.cpp | 1 //===-- AMDGPUAtomicOptimizer.cpp --------
[all...] |