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/llvm-project/llvm/test/MC/Disassembler/ARM/
H A Dthumbv8.1m.s4 [0x52 0xea 0x22 0x9e]
5 # CHECK: cinc lr, r2, lo @ encoding: [0x52,0xea,0x22,0x9e]
7 [0x57 0xea 0x47 0x9e]
8 # CHECK: cinc lr, r7, pl @ encoding: [0x57,0xea,0x47,0x9e]
10 [0x5c 0xea 0x3c 0xae]
11 # CHECK: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
13 [0x5a 0xea 0x3a 0xbe]
14 # CHECK: cneg lr, r10, hs @ encoding: [0x5a,0xea,0x3a,0xbe]
16 [0x59 0xea 0x7b 0x89]
17 # CHECK: csel r9, r9, r11, vc @ encoding: [0x59,0xea,0x7b,0x89]
[all …]
H A Dmve-scalar-shift.txt5 [0x50 0xea 0xef 0x51]
6 # CHECK: asrl r0, r1, #23 @ encoding: [0x50,0xea,0xef,0x51]
9 [0x5e 0xea 0xef 0x61]
10 # CHECK: asrl lr, r1, #27 @ encoding: [0x5e,0xea,0xef,0x61]
13 [0x50 0xea 0x2d 0x41]
14 # CHECK: asrl r0, r1, r4 @ encoding: [0x50,0xea,0x2d,0x41]
17 [0x5e 0xea 0xcf 0x21]
18 # CHECK: lsll lr, r1, #11 @ encoding: [0x5e,0xea,0xcf,0x21]
21 [0x5e 0xea 0x0d 0x41]
22 # CHECK: lsll lr, r1, r4 @ encoding: [0x5e,0xea,0x0d,0x41]
[all …]
H A Dthumb2-bit-15.txt4 [0x09,0xea,0x08,0x04]
7 [0x09,0xea,0x08,0x84]
11 [0x04,0xea,0xe8,0x01]
14 [0x04,0xea,0xe8,0x81]
18 [0x11,0xea,0x47,0x02]
21 [0x11,0xea,0x47,0x82]
25 [0x45,0xea,0x06,0x04]
28 [0x45,0xea,0x06,0x84]
31 [0x45,0xea,0x46,0x14]
34 [0x45,0xea,0x46,0x94]
[all …]
H A Dmve-scalar-shift-unpredictable.txt4 [0x5e 0xea 0x6d 0xcf]
5 # CHECK: sqrshr lr, r12 @ encoding: [0x5e,0xea,0x2d,0xcf]
8 [0x5e 0xea 0xad 0xcf]
9 # CHECK: sqrshr lr, r12 @ encoding: [0x5e,0xea,0x2d,0xcf]
12 [0x5e 0xea 0xed 0xcf]
13 # CHECK: sqrshr lr, r12 @ encoding: [0x5e,0xea,0x2d,0xcf]
16 [0x5e 0xea 0x2d 0xce]
17 # CHECK: sqrshr lr, r12 @ encoding: [0x5e,0xea,0x2d,0xcf]
20 [0x51 0xea 0x2d 0x1f]
21 # CHECK: sqrshr r1, r1 @ encoding: [0x51,0xea,0x2d,0x1f]
[all …]
/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx12_dasm_vop1_dpp8.txt7 0xe9,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05
8 # GFX12: v_bfrev_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe
[all...]
H A Dgfx11_dasm_vopcx_dpp8.txt7 0xe9,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05
8 # GFX11-REAL16: v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe
[all...]
H A Dgfx10_vop1_dpp8.txt4 # GFX10: v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0x02,0x0a,0x7e,0x01,0x88,0xc6,0xfa]
5 0xe
[all...]
H A Dgfx12_dasm_vopcx_dpp8.txt7 0xe9,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05
8 # GFX12-REAL16: v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe
[all...]
H A Dgfx11_dasm_vop2_dpp8.txt7 0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05
8 # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe
[all...]
H A Dgfx10_vop2_dpp8.txt4 # GFX10: v_add_f32_dpp v5, v1, v2 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0x04,0x0a,0x06,0x01,0x88,0xc6,0xfa]
5 0xe
[all...]
H A Dgfx11_dasm_vopc_dpp8.txt7 0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05
8 # W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe
[all...]
H A Dgfx12_dasm_vop2_dpp8.txt7 0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05
8 # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe
[all...]
H A Dgfx12_dasm_vopc_dpp8.txt7 0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05
8 # W32-REAL16: v_cmp_class_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe
[all...]
H A Dgfx11_dasm_vop1_dpp8.txt6 0xe9,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05
7 # GFX11: v_bfrev_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe
[all...]
H A Dgfx11_dasm_vop3_dpp8_from_vopcx.txt7 0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x7
[all...]
H A Dgfx11_dasm_vop3_dpp8_from_vop2.txt4 # W32: v_add_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x20,0xd5,0xe9,0x04,0x1a,0x00,0x0
[all...]
H A Dgfx11_dasm_vop3_dpp8_from_vop1.txt5 0x05,0x00,0xb8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x7
[all...]
H A Dgfx12_dasm_vop3_from_vop1_dpp8.txt5 0x05,0x00,0xb8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x7
[all...]
/llvm-project/llvm/test/MC/ARM/
H A Dmve-scalar-shift.s11 # CHECK: asrl r0, r1, #23 @ encoding: [0x50,0xea,0xef,0x51]
12 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
15 # CHECK: asrl lr, r1, #27 @ encoding: [0x5e,0xea,0xef,0x61]
16 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
19 # CHECK: it eq @ encoding: [0x08,0xbf]
20 # CHECK-NEXT: asrleq lr, r1, #27 @ encoding: [0x5e,0xea,0xef,0x61]
24 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid instruction
25 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
28 # ERROR: [[@LINE+3]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
29 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r…
[all …]
H A Dthumb2-narrow-dp.ll16 // CHECK: adds r0, r0, #5 @ encoding: [0x40,0x1d]
18 // CHECK: adds r1, #8 @ encoding: [0x08,0x31]
20 // CHECK: adds.w r1, r1, #8 @ encoding: [0x11,0xf1,0x08,0x01]
22 // CHECK: adds.w r8, r8, #8 @ encoding: [0x18,0xf1,0x08,0x08]
25 // CHECK: it eq @ encoding: [0x08,0xbf]
27 // CHECK: addeq r0, r0, #5 @ encoding: [0x40,0x1d]
29 // CHECK: it eq @ encoding: [0x08,0xbf]
31 // CHECK: addeq r1, #8 @ encoding: [0x08,0x31]
34 // CHECK: it eq @ encoding: [0x08,0xbf]
36 // CHECK: addseq.w r0, r0, #5 @ encoding: [0x10,0xf1,0x05,0x00]
[all …]
/llvm-project/llvm/test/MC/AMDGPU/
H A Dgfx12_asm_vop3cx_dpp8.s5 v_cmpx_class_f16_e64_dpp v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
6 // GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x0
[all...]
H A Dgfx10_asm_dpp8.s6 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7]
7 // GFX10: encoding: [0xe9,0x02,0x0a,0x7e,0x01,0x88,0xc6,0xfa]
9 v_cvt_f32_i32_dpp v5, v1 dpp8:[0,
[all...]
H A Dgfx12_asm_vopcx_dpp8.s5 v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
6 // GFX12: v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7d,0x01,0x77,0x39,0x0
[all...]
/llvm-project/llvm/test/MC/X86/
H A DLWP-64.s4 // CHECK: encoding: [0x8f,0xc9,0x78,0x12,0xc5]
8 // CHECK: encoding: [0x8f,0xc9,0xf8,0x12,0xc5]
11 // CHECK: lwpins $0, 485498096, %r15d
12 // CHECK: encoding: [0x8f,0xea,0x00,0x12,0x04,0x25,0xf0,0x1c,0xf0,0x1c,0x00,0x00,0x00,0x00]
13 lwpins $0, 485498096, %r15d
15 // CHECK: lwpins $0, 485498096, %r15
16 // CHECK: encoding: [0x8f,0xea,0x80,0x12,0x04,0x25,0xf0,0x1c,0xf0,0x1c,0x00,0x00,0x00,0x00]
17 lwpins $0, 485498096, %r15
19 // CHECK: lwpins $0, 64(%rdx), %r15d
20 // CHECK: encoding: [0x8f,0xea,0x00,0x12,0x42,0x40,0x00,0x00,0x00,0x00]
[all …]
H A DLWP-32.s4 // CHECK: encoding: [0x8f,0xe9,0x78,0x12,0xc0]
7 // CHECK: lwpins $0, -485498096(%edx,%eax,4), %edx
8 // CHECK: encoding: [0x8f,0xea,0x68,0x12,0x84,0x82,0x10,0xe3,0x0f,0xe3,0x00,0x00,0x00,0x00]
9 lwpins $0, -485498096(%edx,%eax,4), %edx
11 // CHECK: lwpins $0, 485498096(%edx,%eax,4), %edx
12 // CHECK: encoding: [0x8f,0xea,0x68,0x12,0x84,0x82,0xf0,0x1c,0xf0,0x1c,0x00,0x00,0x00,0x00]
13 lwpins $0, 485498096(%edx,%eax,4), %edx
15 // CHECK: lwpins $0, 485498096(%edx), %edx
16 // CHECK: encoding: [0x8f,0xea,0x68,0x12,0x82,0xf0,0x1c,0xf0,0x1c,0x00,0x00,0x00,0x00]
17 lwpins $0, 485498096(%edx), %edx
[all …]

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