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/llvm-project/llvm/test/MC/Disassembler/SystemZ/
H A Dinsns-z16.txt5 # CHECK: lbear 0
6 0xb2 0x00 0x00 0x00
8 # CHECK: lbear 0(%r1)
9 0xb2 0x00 0x10 0x00
11 # CHECK: lbear 0(%r15)
12 0xb2 0x00 0xf0 0x00
15 0xb2 0x00 0x0f 0xff
18 0xb2 0x00 0x1f 0xff
21 0xb2 0x00 0xff 0xff
24 0xeb 0x00 0x00 0x00 0x80 0x71
[all …]
H A Dinsns-z15.txt6 0xb9 0x39 0x20 0x22
9 0xb9 0x39 0xf0 0x28
12 0xb9 0x39 0x20 0xe8
15 0xb9 0x39 0xa0 0x68
18 0xb9 0x3a 0x00 0x02
21 0xb9 0x3a 0x00 0x0e
24 0xb9 0x3a 0x00 0xf2
27 0xb9 0x3a 0x00 0x7a
29 # CHECK: mvcrl 0, 0
30 0xe5 0x0a 0x00 0x00 0x00 0x00
[all …]
H A Dinsns-z14.txt6 0xe3 0x00 0x00 0x00 0x80 0x38
9 0xe3 0x00 0x0f 0xff 0xff 0x38
11 # CHECK: agh %r0, 0
12 0xe3 0x00 0x00 0x00 0x00 0x38
15 0xe3 0x00 0x00 0x01 0x00 0x38
18 0xe3 0x00 0x0f 0xff 0x7f 0x38
20 # CHECK: agh %r0, 0(%r1)
21 0xe3 0x00 0x10 0x00 0x00 0x38
23 # CHECK: agh %r0, 0(%r15)
24 0xe3 0x00 0xf0 0x00 0x00 0x38
[all …]
/llvm-project/llvm/test/MC/SystemZ/
H A Dinsn-good-z16.s5 #CHECK: lbear 0 # encoding: [0xb2,0x00,0x00,0x00]
6 #CHECK: lbear 0(%r1) # encoding: [0xb2,0x00,0x10,0x00]
7 #CHECK: lbear 0(%r15) # encoding: [0xb2,0x00,0xf0,0x00]
8 #CHECK: lbear 4095 # encoding: [0xb2,0x00,0x0f,0xff]
9 #CHECK: lbear 4095(%r1) # encoding: [0xb2,0x00,0x1f,0xff]
10 #CHECK: lbear 4095(%r15) # encoding: [0xb2,0x00,0xff,0xff]
12 lbear 0
13 lbear 0(%r1)
14 lbear 0(%r15)
19 #CHECK: lpswey -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x71]
[all …]
H A Dinsn-good-z15.s7 #CHECK: dfltcc %r2, %r2, %r2 # encoding: [0xb9,0x39,0x20,0x22]
8 #CHECK: dfltcc %r2, %r8, %r15 # encoding: [0xb9,0x39,0xf0,0x28]
9 #CHECK: dfltcc %r14, %r8, %r2 # encoding: [0xb9,0x3
[all...]
H A Dinsn-good-z14.s7 #CHECK: agh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x38]
8 #CHECK: agh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x38]
9 #CHECK: agh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x38]
10 #CHECK: agh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x38]
11 #CHECK: agh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x38]
12 #CHECK: agh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x38]
13 #CHECK: agh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x38]
14 #CHECK: agh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x38]
15 #CHECK: agh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x38]
16 #CHECK: agh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x38]
[all …]
/llvm-project/llvm/test/MC/VE/
H A DVSLA.s7 # CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x94,0x20,0xe6]
11 # CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xe6]
15 # CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xe6]
19 # CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x16,0x60,0xe6]
23 # CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x16,0x60,0xe6]
27 # CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x16,0x60,0xe6]
31 # CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x7f,0x6b,0xe6]
35 # CHECK-ENCODING: encoding: [0x00,0xff,0x16,0x0b,0x00,0x00,0x8b,0xe6]
39 # CHECK-ENCODING: encoding: [0x00,0x14,0x16,0x0c,0x00,0x00,0xcc,0xe6]
/llvm-project/llvm/test/MC/Disassembler/Mips/micromips32r3/
H A Dvalid.txt4 0x4f 0xf9 # CHECK: addiusp -16
5 0x4f 0xff # CHECK: addiusp -1028
6 0x4f 0xfd # CHECK: addiusp -1032
7 0x4c 0x01 # CHECK: addiusp 1024
8 0x4c 0x03 # CHECK: addiusp 1028
9 0x2c 0x29 # CHECK: andi16 $16, $2, 31
10 0x47 0x05 # CHECK: jraddiusp 20
11 0x07 0x42 # CHECK: addu16 $6, $17, $4
12 0x06 0xb1 # CHECK: subu16 $5, $16, $3
13 0x44 0x82 # CHECK: and16 $16, $2
[all …]
H A Dvalid-el.txt4 0xf9 0x4f # CHECK: addiusp -16
5 0xff 0x4f # CHECK: addiusp -1028
6 0xfd 0x4f # CHECK: addiusp -1032
7 0x01 0x4c # CHECK: addiusp 1024
8 0x03 0x4c # CHECK: addiusp 1028
9 0x29 0x2c # CHECK: andi16 $16, $2, 31
10 0x05 0x47 # CHECK: jraddiusp 20
11 0x42 0x07 # CHECK: addu16 $6, $17, $4
12 0xb1 0x06 # CHECK: subu16 $5, $16, $3
13 0x82 0x44 # CHECK: and16 $16, $2
[all …]
/llvm-project/llvm/test/MC/ARM/
H A Darm_addrmode2.s4 @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
6 @ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
7 @ CHECK: ldrt r1, [r0], #0 @ encoding: [0x00,0x10,0xb0,0xe4]
8 @ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6]
9 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
10 @ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4]
11 @ CHECK: ldrbt r1, [r0], #0 @ encoding: [0x00,0x10,0xf0,0xe4]
12 @ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6]
13 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
[all …]
/llvm-project/llvm/test/MC/Disassembler/AArch64/
H A Darmv8.5a-dataproc.txt6 [0x3f,0x40,0x00,0xd5]
7 [0x5f,0x40,0x00,0xd5]
16 [0x20,0x40,0x28,0x1e]
17 [0x20,0x40,0x68,0x1e]
18 [0x62,0x40,0x29,0x1e]
19 [0x62,0x40,0x69,0x1e]
20 [0xa4,0xc0,0x28,0x1e]
21 [0xa4,0xc0,0x68,0x1e]
22 [0xe6,0xc0,0x29,0x1e]
23 [0xe6,0xc0,0x69,0x1e]
[all …]
/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx12_dasm_vsample.txt3 # GFX12: image_sample v64, v32, s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x46,0xe4,0x40,0x08,0x00,0x32,0x2
[all...]
H A Dgfx9_sop1.txt3 # CHECK: s_mov_b32 s5, s1 ; encoding: [0x01,0x00,0x85,0xbe]
4 0x01,0x00,0x85,0xbe
6 # CHECK: s_mov_b32 s101, s1 ; encoding: [0x01,0x00,0xe5,0xbe]
7 0x01,0x00,0xe5,0xbe
9 # CHECK: s_mov_b32 flat_scratch_lo, s1 ; encoding: [0x01,0x00,0xe6,0xbe]
10 0x01,0x00,0xe6,0xbe
12 # CHECK: s_mov_b32 flat_scratch_hi, s1 ; encoding: [0x01,0x00,0xe7,0xbe]
13 0x01,0x00,0xe7,0xbe
15 # CHECK: s_mov_b32 vcc_lo, s1 ; encoding: [0x01,0x00,0xea,0xbe]
16 0x01,0x00,0xea,0xbe
[all …]
/llvm-project/llvm/test/tools/llvm-readobj/COFF/
H A Darm64-unwind-save_any_reg.s6 //CHECK-NEXT: 0xe1 ; mov fp, sp
7 //CHECK-NEXT: 0x83 ; stp x29, x30, [sp, #-32]!
8 //CHECK-NEXT: 0xe6 ; save next
9 //CHECK-NEXT: 0xe6 ; save next
10 //CHECK-NEXT: 0xe6 ; save next
11 //CHECK-NEXT: 0xe6 ; save next
12 //CHECK-NEXT: 0xe76689 ; stp q6, q7, [sp, #-160]!
13 //CHECK-NEXT: 0xe4 ; end
20 //CHECK-NEXT: 0x83 ; ldp x29, x30, [sp], #32
21 //CHECK-NEXT: 0xe74e88 ; ldp q14, q15, [sp, #128]
[all …]
/llvm-project/llvm/test/MC/Sparc/
H A Dsparc-cas-instructions.s6 ! V9: cas [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
11 ! V9: casl [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x11,0x1
[all...]
/llvm-project/llvm/test/MC/Mips/
H A Dmicromips-fpu-instructions.s12 # CHECK-EL: add.s $f4, $f6, $f8 # encoding: [0x06,0x55,0x30,0x20]
13 # CHECK-EL: add.d $f4, $f6, $f8 # encoding: [0x06,0x55,0x30,0x21]
14 # CHECK-EL: div.s $f4, $f6, $f8 # encoding: [0x06,0x55,0xf0,0x20]
15 # CHECK-EL: div.d $f4, $f6, $f8 # encoding: [0x06,0x55,0xf0,0x21]
16 # CHECK-EL: mul.s $f4, $f6, $f8 # encoding: [0x06,0x55,0xb0,0x20]
17 # CHECK-EL: mul.d $f4, $f6, $f8 # encoding: [0x06,0x55,0xb0,0x21]
18 # CHECK-EL: sub.s $f4, $f6, $f8 # encoding: [0x06,0x55,0x70,0x20]
19 # CHECK-EL: sub.d $f4, $f6, $f8 # encoding: [0x06,0x55,0x70,0x21]
20 # CHECK-EL: lwc1 $f2, 4($6) # encoding: [0x46,0x9c,0x04,0x00]
21 # CHECK-EL: ldc1 $f2, 4($6) # encoding: [0x46,0xbc,0x04,0x00]
[all …]
H A Dmicromips-alu-instructions.s10 # CHECK-EL: add $9, $6, $7 # encoding: [0xe6,0x00,0x10,0x49]
11 # CHECK-EL: addi $9, $6, 17767 # encoding: [0x26,0x11,0x67,0x45]
12 # CHECK-EL: addiu $9, $6, -15001 # encoding: [0x26,0x31,0x67,0xc5]
13 # CHECK-EL: addi $9, $6, 17767 # encoding: [0x26,0x11,0x67,0x45]
14 # CHECK-EL: addiu $9, $6, -15001 # encoding: [0x26,0x31,0x67,0xc5]
15 # CHECK-EL: addu $9, $6, $7 # encoding: [0xe6,0x00,0x50,0x49]
16 # CHECK-EL: sub $9, $6, $7 # encoding: [0xe6,0x00,0x90,0x49]
17 # CHECK-EL: subu $4, $3, $5 # encoding: [0xa3,0x00,0xd0,0x21]
18 # CHECK-EL: neg $6, $7 # encoding: [0xe0,0x00,0x90,0x31]
19 # CHECK-EL: negu $6, $7 # encoding: [0xe0,0x00,0xd0,0x31]
[all …]
/llvm-project/llvm/test/MC/Disassembler/ARM/
H A Darm-tests.txt4 0x4c 0x45 0x8f 0x52
6 # CHECK: b #0
7 0x00 0x00 0x00 0xea
10 0x8d 0x07 0x00 0xeb
13 0xff 0xff 0xff 0x0b
15 # CHECK: bfc r8, #0, #16
16 0x1f 0x80 0xcf 0xe7
19 0x10 0x88 0xd0 0xe7
22 0x0e 0xf0 0xa0 0xe1
25 0xff 0xf1 0xa0 0xe3
[all …]
H A Dbasic-arm-instructions.txt22 0x0f 0x10 0xa2 0xe2
23 0xf0 0x10 0xa2 0xe2
24 0x0f 0x1c 0xa2 0xe2
25 0x0f 0x1a 0xa2 0xe2
26 0x0f 0x18 0xa2 0xe2
27 0x0f 0x16 0xa2 0xe2
28 0x0f 0x14 0xa2 0xe2
29 0x0f 0x12 0xa2 0xe2
30 0xff 0x12 0xa2 0xe2
31 0x2a 0x71 0xa8 0xe2
[all …]
/llvm-project/llvm/test/MC/Disassembler/Sparc/
H A Dsparc-atomics.txt4 0xd5,0xe6,0x10,0x16
7 0xd5,0xe6,0x11,0x16
10 0xd5,0xe6,0x1f,0xf6
13 0xd5,0xe6,0x20,0x16
16 0xd5,0xf6,0x10,0x16
19 0xd5,0xf6,0x11,0x16
22 0xd5,0xf6,0x1f,0xf6
25 0xd5,0xf6,0x20,0x16
/llvm-project/llvm/test/MC/AMDGPU/
H A Dgfx12_asm_vsample.s3 image_sample v64, v32, s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_1D
4 // GFX12: encoding: [0x00,0xc0,0x46,0xe4,0x40,0x08,0x00,0x32,0x20,0x00,0x00,0x00]
6 image_sample v64, [v32, v33], s[4:11], s[100:103] dmask:0x8 dim:SQ_RSRC_IMG_2D
7 // GFX12: encoding: [0x01,0xc0,0x06,0xe6,0x40,0x08,0x00,0x32,0x20,0x21,0x00,0x00]
9 image_sample v[64:65], [v32, v33, v34], s[4:11], s[100:103] dmask:0x3 dim:SQ_RSRC_IMG_3D
10 // GFX12: encoding: [0x02,0xc0,0xc6,0xe4,0x40,0x08,0x00,0x32,0x20,0x21,0x22,0x00]
12 image_sample v[64:65], [v32, v33, v34], s[4:11], s[100:103] dmask:0xc dim:SQ_RSRC_IMG_CUBE
13 // GFX12: encoding: [0x03,0xc0,0x06,0xe7,0x40,0x08,0x00,0x32,0x20,0x21,0x22,0x00]
15 image_sample v[64:66], [v32, v33], s[4:11], s[100:103] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
16 // GFX12: encoding: [0x04,0xc0,0xc6,0xe6,0x40,0x08,0x00,0x32,0x20,0x21,0x00,0x00]
[all …]
/llvm-project/llvm/test/MC/Disassembler/Hexagon/
H A Dxtype_mpy.txt5 0xb1 0xdf 0x35 0xd7
7 0xbf 0xd1 0x35 0xd8
9 0xb5 0xd1 0x3f 0xdf
11 0xf5 0xf1 0xb5 0xdf
13 0x15 0xd1 0x1f 0xe3
15 0xf1 0xc3 0x15 0xe0
17 0xf1 0xc3 0x95 0xe0
19 0xf1 0xc3 0x15 0xe1
21 0xf1 0xc3 0x95 0xe1
23 0x11 0xdf 0x15 0xed
[all …]
/llvm-project/llvm/test/MC/Disassembler/X86/
H A Davx-vnni-int8-64.txt6 0xc4,0x42,0x17,0x50,0xe6
10 0xc4,0x42,0x13,0x50,0xe6
14 0xc4,0x22,0x17,0x50,0xa4,0xf5,0x00,0x00,0x00,0x10
18 0xc4,0x42,0x17,0x50,0xa4,0x80,0x23,0x01,0x00,0x00
22 0xc4,0x62,0x17,0x50,0x25,0x00,0x00,0x00,0x00
26 0xc4,0x62,0x17,0x50,0x24,0x6d,0x00,0xfc,0xff,0xff
30 0xc4,0x22,0x13,0x50,0xa4,0xf5,0x00,0x00,0x00,0x10
34 0xc4,0x42,0x13,0x50,0xa4,0x80,0x23,0x01,0x00,0x00
38 0xc4,0x62,0x13,0x50,0x25,0x00,0x00,0x00,0x00
42 0xc4,0x62,0x13,0x50,0x24,0x6d,0x00,0xfe,0xff,0xff
[all …]
/llvm-project/llvm/test/MC/RISCV/
H A Drv32zdinx-valid.s
/llvm-project/llvm/test/MC/X86/
H A Davx_vnni_int8-64-intel.s4 // CHECK: encoding: [0xc4,0x42,0x17,0x50,0xe6]
8 // CHECK: encoding: [0xc4,0x42,0x13,0x50,0xe6]
12 // CHECK: encoding: [0xc4,0x22,0x17,0x50,0xa4,0xf5,0x00,0x00,0x00,0x10]
16 // CHECK: encoding: [0xc4,0x42,0x17,0x50,0xa4,0x80,0x23,0x01,0x00,0x00]
20 // CHECK: encoding: [0xc4,0x62,0x17,0x50,0x25,0x00,0x00,0x00,0x00]
24 // CHECK: encoding: [0xc4,0x62,0x17,0x50,0x24,0x6d,0x00,0xfc,0xff,0xff]
28 // CHECK: encoding: [0xc4,0x22,0x13,0x50,0xa4,0xf5,0x00,0x00,0x00,0x10]
32 // CHECK: encoding: [0xc4,0x42,0x13,0x50,0xa4,0x80,0x23,0x01,0x00,0x00]
36 // CHECK: encoding: [0xc4,0x62,0x13,0x50,0x25,0x00,0x00,0x00,0x00]
40 // CHECK: encoding: [0xc4,0x62,0x13,0x50,0x24,0x6d,0x00,0xfe,0xff,0xff]
[all …]

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