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/llvm-project/llvm/test/MC/Disassembler/Hexagon/
H A Dnv_j.txt5 0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x20
8 0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x20
11 0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x20
14 0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x20
17 0x11 0x40 0x71 0x70 0x92 0xd5 0x82 0x20
20 0x11 0x40 0x71 0x70 0x92 0xf5 0x82 0x20
23 0x11 0x40 0x71 0x70 0x92 0xd5 0xc2 0x20
26 0x11 0x40 0x71 0x70 0x92 0xf5 0xc2 0x20
29 0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x21
32 0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x21
[all …]
/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx11_dasm_vop3p_dpp8.txt4 # GFX11: v_dot2_f32_f16_e64_dpp v0, v1, v2, v3 neg_lo:[0,1,1] neg_hi:[1,0,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x00,0x45,0x13,0xcc,0xe9,0x04,0x0
[all...]
H A Dgfx12_dasm_vop3p_dpp8.txt4 # GFX12: v_dot2_f32_f16_e64_dpp v0, v1, v2, v3 neg_lo:[0,1,1] neg_hi:[1,0,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x00,0x45,0x13,0xcc,0xe9,0x04,0x0
[all...]
/llvm-project/llvm/test/MC/Disassembler/AArch64/
H A Darmv8a-fpmul-err.txt8 [0x20,0xec,0x22,0x0e]
9 [0x20,0xec,0xa2,0x0e]
10 [0x20,0xec,0x22,0x4e]
11 [0x20,0xec,0xa2,0x4e]
12 [0x20,0xcc,0x22,0x2e]
13 [0x20,0xcc,0xa2,0x2e]
14 [0x20,0xcc,0x22,0x6e]
15 [0x20,0xcc,0xa2,0x6e]
19 [0x20,0x08,0xb2,0x0f]
20 [0x20,0x48,0xb2,0x0f]
[all …]
H A Darmv8a-fpmul.txt5 [0x41,0x08,0xe3,0x1e]
7 [0x20,0xec,0x22,0x0e]
8 [0x20,0xec,0xa2,0x0e]
9 [0x20,0xec,0x22,0x4e]
10 [0x20,0xec,0xa2,0x4e]
11 [0x20,0xcc,0x22,0x2e]
12 [0x20,0xcc,0xa2,0x2e]
13 [0x20,0xcc,0x22,0x6e]
14 [0x20,0xcc,0xa2,0x6e]
18 [0x20,0x08,0xb2,0x0f]
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dstack-probing-sve.ll14 define void @sve_1_vector(ptr %out) #0 {
16 ; CHECK: // %bb.0: // %entry
21 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00…
25 ; CHECK-NEXT: .cfi_def_cfa_offset 0
34 define void @sve_4_vector(ptr %out) #0 {
36 ; CHECK: // %bb.0: // %entry
41 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00…
45 ; CHECK-NEXT: .cfi_def_cfa_offset 0
59 define void @sve_16_vector(ptr %out) #0 {
61 ; CHECK: // %bb.0: // %entry
[all …]
H A Dframelayout-sve.mir50 # | %stack.0 | // scalable SVE object of n * 18 bytes, aligned to 16 bytes,
59 # CHECK: bb.0.entry:
64 # CHECK-NEXT: $sp = frame-setup SUBXri $sp, 16, 0
67 # CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x20, 0x2
[all...]
H A Dsve-callee-save-restore-pairs.ll15 ; NOPAIR: // %bb.0:
46 ; NOPAIR-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x9
[all...]
/llvm-project/llvm/test/MC/Disassembler/ARM/
H A Dload-store-acquire-release-v8.txt2 0x9f 0x0e 0xd8 0xe1
3 0x9f 0x1e 0xfc 0xe1
4 0x9f 0x1e 0x90 0xe1
5 0x9f 0x8e 0xbd 0xe1
6 # CHECK: ldaexb r0, [r8] @ encoding: [0x9f,0x0e,0xd8,0xe1]
7 # CHECK: ldaexh r1, [r12] @ encoding: [0x9f,0x1e,0xfc,0xe1]
8 # CHECK: ldaex r1, [r0] @ encoding: [0x9f,0x1e,0x90,0xe1]
9 # CHECK: ldaexd r8, r9, [sp] @ encoding: [0x9f,0x8e,0xbd,0xe1]
11 0x93 0x1e 0xc4 0xe1
12 0x92 0x4e 0xe5 0xe1
[all …]
H A Dunpredictable-MUL-arm.txt4 # CHECK: 0x93 0x12 0x01 0x00
5 0x93 0x12 0x01 0x00
8 # CHECK: 0x92 0x0f 0x01 0x00
9 0x92 0x0f 0x01 0x00
12 # CHECK: 0x9f 0x02 0x01 0x00
13 0x9f 0x02 0x01 0x00
16 # CHECK: 0x92 0x01 0x0f 0x00
17 0x92 0x01 0x0f 0x00
H A Darm-STREXD-reencoding.txt3 0x92 0x1f 0xa0 0xe1
4 0x90 0x4f 0xa3 0xe1
5 0x92 0xdf 0xa4 0xe1
6 0x90 0xaf 0xa6 0xe1
7 0x9c 0x5f 0xa8 0xe1
9 # CHECK: strexd r1, r2, r3, [r0] @ encoding: [0x92,0x1f,0xa0,0xe1]
10 # CHECK: strexd r4, r0, r1, [r3] @ encoding: [0x90,0x4f,0xa3,0xe1]
11 # CHECK: strexd sp, r2, r3, [r4] @ encoding: [0x92,0xdf,0xa4,0xe1]
12 # CHECK: strexd r10, r0, r1, [r6] @ encoding: [0x90,0xaf,0xa6,0xe1]
13 # CHECK: strexd r5, r12, sp, [r8] @ encoding: [0x9c,0x5f,0xa8,0xe1]
/llvm-project/llvm/test/MC/AMDGPU/
H A Dgfx11_asm_vop3p_dpp8.s5 // GFX11: encoding: [0x00,0x00,0x20,0xcc,0xe9,0x04,0x0e,0x04,0x01,0x9
[all...]
H A Dgfx12_asm_vop3p_dpp8.s5 // GFX12: encoding: [0x00,0x00,0x20,0xcc,0xe9,0x04,0x0e,0x04,0x01,0x9
[all...]
/llvm-project/llvm/test/MC/AVR/
H A Dinst-st.s41 ; CHECK: st X, r10 ; encoding: [0xac,0x92]
42 ; CHECK: st X, r17 ; encoding: [0x1c,0x93]
44 ; CHECK: st Y, r30 ; encoding: [0xe8,0x83]
45 ; CHECK: st Y, r19 ; encoding: [0x38,0x83]
47 ; CHECK: st Z, r10 ; encoding: [0xa
[all...]
/llvm-project/llvm/test/CodeGen/X86/
H A Davx512vl-intrinsics-canonical.ll9 ; X86: # %bb.0: # %entry
10 ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
11 ; X86-NEXT: kmovw %eax, %k1 # encoding: [0xc5,0xf8,0x92,0xc8]
12 ; X86-NEXT: vfmadd132pd %xmm1, %xmm2, %xmm0 {%k1} # encoding: [0x62,0xf2,0xed,0x09,0x98,0xc1]
14 ; X86-NEXT: retl # encoding: [0xc3]
17 ; X64: # %bb.0: # %entry
18 ; X64-NEXT: kmovw %edi, %k1 # encoding: [0xc5,0xf8,0x92,0xcf]
19 ; X64-NEXT: vfmadd132pd %xmm1, %xmm2, %xmm0 {%k1} # encoding: [0x62,0xf2,0xed,0x09,0x98,0xc1]
21 ; X64-NEXT: retq # encoding: [0xc3]
23 …%0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %__A, <2 x double> %__B, <2 x double> %__…
[all …]
H A Davx512vl-intrinsics.ll7 ; X86: # %bb.0:
8 ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
9 ; X86-NEXT: kmovw %eax, %k1 # encoding: [0xc5,0xf8,0x9
[all...]
H A Davx512vl-intrinsics-upgrade.ll9 ; X86: # %bb.0:
10 ; X86-NEXT: vpbroadcastd {{[0-9]+}}(%esp), %xmm3 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x58,0x5c,0x24,0x04]
11 ; X86-NEXT: movzbl {{[0
[all...]
H A Davx512ifmavl-intrinsics-upgrade.ll9 ; CHECK: # %bb.0:
10 ; CHECK-NEXT: vpmadd52huq %xmm2, %xmm1, %xmm0 # encoding: [0x62,0xf2,0xf5,0x08,0xb5,0xc2]
11 ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
19 ; X86: # %bb.0:
20 ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
21 ; X86-NEXT: kmovw %eax, %k1 # encoding: [0xc5,0xf8,0x92,0xc8]
22 ; X86-NEXT: vpmadd52huq %xmm2, %xmm1, %xmm0 {%k1} # encoding: [0x62,0xf2,0xf5,0x09,0xb5,0xc2]
23 ; X86-NEXT: retl # encoding: [0xc3]
26 ; X64: # %bb.0:
27 ; X64-NEXT: kmovw %edi, %k1 # encoding: [0xc5,0xf8,0x92,0xcf]
[all …]
H A Davx512ifma-intrinsics-upgrade.ll9 ; CHECK: # %bb.0:
10 ; CHECK-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 # encoding: [0x62,0xf2,0xf5,0x48,0xb5,0xc2]
11 ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
19 ; X86: # %bb.0:
20 ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
21 ; X86-NEXT: kmovw %eax, %k1 # encoding: [0xc5,0xf8,0x92,0xc8]
22 ; X86-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 {%k1} # encoding: [0x62,0xf2,0xf5,0x49,0xb5,0xc2]
23 ; X86-NEXT: retl # encoding: [0xc3]
26 ; X64: # %bb.0:
27 ; X64-NEXT: kmovw %edi, %k1 # encoding: [0xc5,0xf8,0x92,0xcf]
[all …]
H A Davx512bwvl-intrinsics-canonical.ll13 ; CHECK: ## %bb.0:
14 ; CHECK-NEXT: vpaddsw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xed,0…
15 ; CHECK-NEXT: retq ## encoding: [0xc3]
23 ; CHECK: ## %bb.0:
24 ; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
25 ; CHECK-NEXT: vpaddsw %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xed,0xd1]
26 ; CHECK-NEXT: vmovdqa %xmm2, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
27 ; CHECK-NEXT: retq ## encoding: [0xc3]
36 ; CHECK: ## %bb.0:
37 ; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
[all …]
H A Davx512-intrinsics-canonical.ll9 ; CHECK: ## %bb.0: ## %entry
10 ; CHECK-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x18,0xa8,0…
11 ; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
13 …%0 = tail call <8 x double> @llvm.x86.avx512.vfmadd.pd.512(<8 x double> %__A, <8 x double> %__B, <…
14 ret <8 x double> %0
21 ; X86: ## %bb.0: ## %entry
22 ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ## encoding: [0x0f,0xb6,0x44,0x24,0x04]
23 ; X86-NEXT: kmovw %eax, %k1 ## encoding: [0xc5,0xf8,0x92,0xc8]
24 …XT: vfmadd132pd {rn-sae}, %zmm1, %zmm2, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xed,0x19,0x98,0xc1]
25 ; X86-NEXT: retl ## encoding: [0xc3]
[all …]
H A Davx512bf16-vl-intrinsics-upgrade.ll7 define <2 x i64> @test_mm_cvtne2ps2bf16_128(<4 x float> %A, <4 x float> %B) local_unnamed_addr #0 {
9 ; CHECK: # %bb.0: # %entry
10 ; CHECK-NEXT: vcvtne2ps2bf16 %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf2,0x7f,0x08,0x72,0xc1]
11 ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
13 %0 = tail call <8 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.128(<4 x float> %A, <4 x float> %B) #2
14 %1 = bitcast <8 x i16> %0 to <2 x i64>
18 …t_mm_maskz_cvtne2ps2bf16_128(<4 x float> %A, <4 x float> %B, i8 zeroext %U) local_unnamed_addr #0 {
20 ; X86: # %bb.0: # %entry
21 ; X86-NEXT: vcvtne2ps2bf16 %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf2,0x7f,0x08,0x72,0xc1]
22 ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
[all …]
H A Davx512ifma-intrinsics.ll9 ; CHECK: # %bb.0:
10 ; CHECK-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 # encoding: [0x62,0xf2,0xf5,0x48,0xb5,0xc2]
11 ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
19 ; X86: # %bb.0:
20 ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
21 ; X86-NEXT: kmovw %eax, %k1 # encoding: [0xc5,0xf8,0x92,0xc8]
22 ; X86-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 {%k1} # encoding: [0x62,0xf2,0xf5,0x49,0xb5,0xc2]
23 ; X86-NEXT: retl # encoding: [0xc3]
26 ; X64: # %bb.0:
27 ; X64-NEXT: kmovw %edi, %k1 # encoding: [0xc5,0xf8,0x92,0xcf]
[all …]
H A Davx512ifmavl-intrinsics.ll9 ; CHECK: # %bb.0:
10 ; CHECK-NEXT: vpmadd52huq %xmm2, %xmm1, %xmm0 # encoding: [0x62,0xf2,0xf5,0x08,0xb5,0xc2]
11 ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
19 ; X86: # %bb.0:
20 ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
21 ; X86-NEXT: kmovw %eax, %k1 # encoding: [0xc5,0xf8,0x92,0xc8]
22 ; X86-NEXT: vpmadd52huq %xmm2, %xmm1, %xmm0 {%k1} # encoding: [0x62,0xf2,0xf5,0x09,0xb5,0xc2]
23 ; X86-NEXT: retl # encoding: [0xc3]
26 ; X64: # %bb.0:
27 ; X64-NEXT: kmovw %edi, %k1 # encoding: [0xc5,0xf8,0x92,0xcf]
[all …]
/llvm-project/llvm/test/MC/ARM/
H A Darm-arithmetic-aliases.s11 @ CHECK: sub r2, r2, #6 @ encoding: [0x06,0x20,0x42,0xe2]
12 @ CHECK: sub r2, r2, #6 @ encoding: [0x06,0x20,0x42,0xe2]
13 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
14 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
21 @ CHECK: add r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe2]
22 @ CHECK: add r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe2]
23 @ CHECK: add r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe0]
24 @ CHECK: add r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe0]
31 @ CHECK: and r2, r2, #6 @ encoding: [0x06,0x20,0x02,0xe2]
32 @ CHECK: and r2, r2, #6 @ encoding: [0x06,0x20,0x02,0xe2]
[all …]

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