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/freebsd-src/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am62p-wakeup.dtsi10 reg = <0x00 0x43000000 0x00 0x20000>;
13 ranges = <0x00 0x00 0x43000000 0x20000>;
18 reg = <0x14 0x
[all...]
H A Dk3-am62a.dtsi54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x0042000
[all...]
H A Dk3-am62p.dtsi53 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
54 <0x00 0x00420000 0x00 0x0042000
[all...]
H A Dk3-am64.dtsi54 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
55 <0x00 0x00420000 0x00 0x0042000
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/pci/
H A Dmicrochip,pcie-host.yaml41 0-3
45 pattern: '^fic[0-3]$'
64 reg = <0x0 0x70000000 0x0 0x08000000>,
65 <0x0 0x43000000 0x0 0x0001000
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a77965-ulcb.dts20 reg = <0x0 0x48000000 0x0 0x78000000>;
31 clock-names = "du.0", "du.1", "du.3",
32 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77965-salvator-x.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
30 clock-names = "du.0", "du.1", "du.3",
31 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77965-salvator-xs.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
30 clock-names = "du.0", "du.1", "du.3",
31 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a774a1-hihope-rzg2m-rev2.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a774a1-hihope-rzg2m.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a774e1-hihope-rzg2h.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x5 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77960-salvator-xs.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a77960-salvator-x.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a779m5-salvator-xs.dts23 reg = <0x0 0x48000000 0x0 0x78000000>;
34 clock-names = "du.0", "du.1", "du.3",
35 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77961-ulcb.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x4 0x80000000 0x0 0x80000000>;
29 reg = <0x6 0x00000000 0x1 0x00000000>;
40 clock-names = "du.0", "du.1", "du.2",
41 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a774b1-hihope-rzg2n-rev2.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x4 0x80000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a774b1-hihope-rzg2n.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x4 0x80000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77961-salvator-xs.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x4 0x80000000 0x0 0x80000000>;
29 reg = <0x6 0x00000000 0x1 0x00000000>;
40 clock-names = "du.0", "du.1", "du.2",
41 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a779m3-ulcb.dts22 reg = <0x0 0x48000000 0x0 0x78000000>;
27 reg = <0x4 0x80000000 0x0 0x80000000>;
32 reg = <0x6 0x00000000 0x1 0x00000000>;
43 clock-names = "du.0", "du.1", "du.2",
44 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a779m3-salvator-xs.dts23 reg = <0x0 0x48000000 0x0 0x78000000>;
28 reg = <0x4 0x80000000 0x0 0x80000000>;
33 reg = <0x6 0x00000000 0x1 0x00000000>;
44 clock-names = "du.0", "du.1", "du.2",
45 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a779f0-spider-cpu.dtsi54 reg = <0x0 0x48000000 0x0 0x78000000>;
59 reg = <0x4 0x80000000 0x0 0x80000000>;
65 #clock-cells = <0>;
[all...]
H A Dr8a77980-v3hsk.dts49 #size-cells = <0>;
51 port@0 {
52 reg = <0>;
70 reg = <0 0x48000000 0 0x78000000>;
75 #clock-cells = <0>;
79 vcc1v8_d4: regulator-0 {
101 clock-names = "du.0", "dclkin.0";
114 pinctrl-0 = <&gether_pins>;
122 phy0: ethernet-phy@0 {
126 reg = <0>;
[all …]
H A Dr8a77970-v3msk.dts47 #size-cells = <0>;
49 port@0 {
50 reg = <0>;
68 reg = <0x0 0x48000000 0x0 0x78000000>;
73 #clock-cells = <0>;
77 vcc_d1_8v: regulator-0 {
106 pinctrl-0 = <&avb_pins>;
115 phy0: ethernet-phy@0 {
119 reg = <0>;
129 clock-names = "du.0", "dclkin.0";
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/reserved-memory/
H A Dshared-dma-pool.yaml82 size = <0x4000000>;
83 alignment = <0x2000>;
88 reg = <0x78000000 0x800000>;
93 reg = <0x50000000 0x4000000>;
/freebsd-src/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_hexagon.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
24 PO_JUMPI_14 = 0x5800c00a, // jump #0x014 (PC + 0x014)
25 PO_CALLR_R6 = 0x50a6c000, // indirect call: callr r6
26 PO_TFR_IMM = 0x78000000, // transfer immed
27 // ICLASS 0x7 - S2-type A-type
28 PO_IMMEXT = 0x00000000, // constant extender
32 PP_DUPLEX = 0x00 << 14,
33 PP_NOT_END = 0x01 << 14,
34 PP_PACKET_END = 0x03 << 14,
38 RN_R6 = 0x6,
[all …]

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