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/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dmachine-backward-cp.mir12 bb.0.entry:
29 ; CHECK: bb.0.entry:
36 bb.0.entry:
56 bb.0.entry:
73 bb.0.entry:
75 ; CHECK: renamable $x4 = LI8 0
79 renamable $x4 = LI8 0
92 bb.0.entry:
97 ; CHECK: renamable $x4 = LI8 0
101 renamable $x4 = LI8 0
[all …]
H A Dldst-16-byte.mir10 bb.0.entry:
16 ; CHECK-NEXT: $x5 = OR8 $x7, $x7
19 %0:g8prc = LQ 128, $x4
20 $x5 = COPY %0.sub_gp8_x1:g8prc
21 STQ %0, 160, $x5
30 bb.0.entry:
37 ; CHECK-NEXT: $x3 = OR8 $x7, killed $x7
39 %0
[all...]
/llvm-project/llvm/test/MC/AMDGPU/
H A Dgfx11_asm_mimg_err.s3 image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D
4 // NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
6 image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1, v0, v20, v21], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D
7 // NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
9 image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1, v5], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_CUBE
10 // NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
12 image_sample_d v[64:66], [v32, v16, v8, v4, v0, v20, v21], s[4:11], s[100:103] dmask:0x
[all...]
H A Dgfx11_asm_mimg_features.s3 image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
4 // GFX11: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x80,0x0f,0…
6 image_load v[1:4], [v2, v3], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
7 …], [v2, v3], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm ; encoding: [0x85,0x0f,0x00,0xf0,0x02,0x01…
9 image_load v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_3D unorm
10 …ge_load v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_3D unorm ; encoding: [0x89,0x0f,0x…
12 image_load v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm
13 …e_load v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm ; encoding: [0x8d,0x0f,0…
15 image_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm
16 …e_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm ; encoding: [0x91,0x0f,0…
[all …]
H A Dgfx10_asm_mimg.s3 image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
4 ; GFX10: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x1f,0x…
6 image_load v[1:4], [v2, v3], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
7 …], [v2, v3], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm ; encoding: [0x0a,0x1f,0x00,0xf0,0x02,0x01…
9 image_load v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_3D unorm
10 …ge_load v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_3D unorm ; encoding: [0x12,0x1f,0x…
12 image_load v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm
13 …e_load v[0:3], [v4, v5, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm ; encoding: [0x1a,0x1f,0…
15 image_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm
16 …e_load v[0:3], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm ; encoding: [0x22,0x1f,0…
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Daarch64-fastcc-stackup.ll6 ; CHECK: // %bb.0:
11 define fastcc i64 @foo(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i64 %6, i64 %7, i64 %8) {
13 ; CHECK: // %bb.0:
16 ret i64 %0
22 ; CHECK: // %bb.0: // %entry
28 ; CHECK-NEXT: mov x7, xzr
30 ; CHECK-NEXT: mov x0, x7
31 ; CHECK-NEXT: mov x1, x7
32 ; CHECK-NEXT: mov x2, x7
33 ; CHECK-NEXT: mov x3, x7
[all …]
H A Darm64-atomic-128.ll6 @var = global i128 0
10 ; NOOUTLINE: // %bb.0:
30 ; OUTLINE: // %bb.0:
45 ; LSE: // %bb.0:
55 %val = extractvalue { i128, i1 } %pair, 0
61 ; NOOUTLINE: // %bb.0:
81 ; OUTLINE: // %bb.0:
96 ; LSE: // %bb.0:
106 %val = extractvalue { i128, i1 } %pair, 0
112 ; NOOUTLINE: // %bb.0:
[all …]
H A Di256-math.ll18 ; CHECK: // %bb.0:
22 ; CHECK-NEXT: adc x3, x3, x7
30 ; CHECK: // %bb.0:
34 ; CHECK-NEXT: adcs x3, x3, x7
36 ; CHECK-NEXT: eor w4, w8, #0x1
39 %2 = extractvalue { i256, i1 } %1, 0
43 %6 = insertvalue { i256, i8 } undef, i256 %2, 0
50 ; CHECK: // %bb.0:
54 ; CHECK-NEXT: adcs x3, x3, x7
58 %2 = extractvalue { i256, i1 } %1, 0
[all …]
H A Dmachine-outliner-all-stack.mir12 define void @reg-save-possible() #0 { ret void }
13 define void @stack-save1() #0 { ret void }
14 define void @stack-save2() #0 { ret void }
15 define void @stack-save3() #0 { ret void }
16 attributes #0 = { minsize noinline noredzone "frame-pointer"="all" }
23 bb.0:
32 ; CHECK-NEXT: BL [[FN:@OUTLINED_FUNCTION_[0-9]+]]
48 bb.0:
49 …liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15…
52 …liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15…
[all …]
H A Dmachine-outliner-2fixup-blr-terminator.mir7 define void @f1() #0 { ret void }
8 define void @f2() #0 { ret void }
9 define void @f3() #0 { ret void }
10 define void @f4() #0 { ret void }
11 attributes #0 = { minsize noredzone "branch-target-enforcement" }
17 bb.0:
18 liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
29 liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
36 bb.0:
37 liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7,
[all...]
/llvm-project/lld/test/ELF/
H A Daarch64-cortex-a53-843419-nopatch.s10 // ADRP (0xff8 or 0xffc)
23 // erratum sequence but adrp (address & 0xfff) is not 0xff8 or 0xffc
30 ldr x1, [x1, #0]
41 ldr x1, [x1, #0]
57 ldp x1,x2, [x3, #0]
104 adrp x7, dat
105 ldnp x1,x2, [x3, #0]
[all...]
/llvm-project/llvm/test/MC/AArch64/
H A Darm64-elf-relocs.s14 // CHECK-OBJ-LP64: 0 R_AARCH64_ADD_ABS_LO12_NC sym
15 // CHECK-OBJ-LP64: 4 R_AARCH64_ADD_ABS_LO12_NC sym+0xc
16 // CHECK-OBJ-LP64: 8 R_AARCH64_ADD_ABS_LO12_NC sym-0x3
18 add x5, x7, #:dtprel_lo12:sym
19 // CHECK: add x5, x7, :dtprel_lo12:sym
40 // CHECK-OBJ-LP64: 20 R_AARCH64_ADD_ABS_LO12_NC sym+0x8
42 add x5, x7, #:dtprel_lo12:sym+1
43 // CHECK: add x5, x7, :dtprel_lo12:sym+1
44 // CHECK-OBJ-LP64: 24 R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym+0x1
48 // CHECK-OBJ-LP64: 28 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+0x
[all...]
H A Darm32-elf-relocs.s10 // CHECK-OBJ-ILP32: 0 R_AARCH64_P32_ADD_ABS_LO12_NC sym
12 add x5, x7, #:dtprel_lo12:sym
13 // CHECK: add x5, x7, :dtprel_lo12:sym
34 // CHECK-OBJ-ILP32: 18 R_AARCH64_P32_ADD_ABS_LO12_NC sym+0x8
36 add x5, x7, #:dtprel_lo12:sym+1
37 // CHECK: add x5, x7, :dtprel_lo12:sym+1
38 // CHECK-OBJ-ILP32: 1c R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 sym+0x1
42 // CHECK-OBJ-ILP32:20 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC sym+0x2
46 // CHECK-OBJ-ILP32: 24 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 sym+0xc
50 // CHECK-OBJ-ILP32: 28 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC sym+0x36
[all …]
H A Darmv8.5a-specrestrict.s7 // CHECK: mrs x9, {{id_pfr2_el1|ID_PFR2_EL1}} // encoding: [0x89,0x03,0x38,0xd5]
12 mrs x7, SCXTNUM_EL1
17 // CHECK: mrs x8, {{scxtnum_el0|SCXTNUM_EL0}} // encoding: [0xe8,0xd0,0x3b,0xd5]
18 // CHECK: mrs x7, {{scxtnum_el1|SCXTNUM_EL1}} // encoding: [0xe7,0xd0,0x38,0xd5]
19 // CHECK: mrs x6, {{scxtnum_el2|SCXTNUM_EL2}} // encoding: [0xe6,0xd0,0x3c,0xd5]
20 // CHECK: mrs x5, {{scxtnum_el3|SCXTNUM_EL3}} // encoding: [0xe5,0xd0,0x3e,0xd5]
21 // CHECK: mrs x4, {{scxtnum_el12|SCXTNUM_EL12}} // encoding: [0xe4,0xd0,0x3d,0xd5]
25 // NOSPECID-NEXT: mrs x7, {{scxtnum_el1|SCXTNUM_EL1}}
34 msr SCXTNUM_EL1, x7
39 // CHECK: msr {{scxtnum_el0|SCXTNUM_EL0}}, x8 // encoding: [0xe8,0xd0,0x1b,0xd5]
[all …]
H A Ddirective-arch_extension.s52 dc cvadp, x7
53 // CHECK: dc cvadp, x7
76 dc cvap, x7
77 // CHECK: dc cvap, x7
115 sysp #0, c2, c0, #0, x0, x1
116 rcwcasp x0, x1, x6, x7, [x4]
117 // CHECK: sysp #0, c2, c0, #0, x0, x1
118 // CHECK: rcwcasp x0, x1, x6, x7, [x
[all...]
H A Darm64-memory.s43 ; CHECK: ldr w5, [x4, #20] ; encoding: [0x85,0x14,0x40,0xb9]
44 ; CHECK: ldr x4, [x3] ; encoding: [0x64,0x00,0x40,0xf9]
45 ; CHECK: ldr x2, [sp, #32] ; encoding: [0xe2,0x13,0x40,0xf9]
46 ; CHECK: ldr b5, [sp, #1] ; encoding: [0xe5,0x07,0x40,0x3d]
47 ; CHECK: ldr h6, [sp, #2] ; encoding: [0xe6,0x07,0x40,0x7d]
48 ; CHECK: ldr s7, [sp, #4] ; encoding: [0xe7,0x07,0x40,0xbd]
49 ; CHECK: ldr d8, [sp, #8] ; encoding: [0xe8,0x07,0x40,0xfd]
50 ; CHECK: ldr q9, [sp, #16] ; encoding: [0xe9,0x07,0xc0,0x3d]
51 ; CHECK: ldrb w4, [x3] ; encoding: [0x64,0x00,0x40,0x39]
52 ; CHECK: ldrb w5, [x4, #20] ; encoding: [0x85,0x50,0x40,0x39]
[all …]
H A Darmv8.9a-the.s16 // CHECK: mrs x3, RCWMASK_EL1 // encoding: [0xc3,0xd0,0x38,0xd5]
19 // CHECK: msr RCWMASK_EL1, x1 // encoding: [0xc1,0xd0,0x18,0xd5]
22 // CHECK: mrs x3, RCWSMASK_EL1 // encoding: [0x63,0xd0,0x38,0xd5]
25 // CHECK: msr RCWSMASK_EL1, x1 // encoding: [0x61,0xd0,0x18,0xd5]
29 // CHECK: rcwcas x0, x1, [x4] // encoding: [0x81,0x08,0x20,0x19]
32 // CHECK: rcwcasa x0, x1, [x4] // encoding: [0x81,0x08,0xa0,0x19]
35 // CHECK: rcwcasal x0, x1, [x4] // encoding: [0x81,0x08,0xe0,0x19]
38 // CHECK: rcwcasl x0, x1, [x4] // encoding: [0x81,0x08,0x60,0x19]
41 // CHECK: rcwcas x3, x5, [sp] // encoding: [0xe5,0x0b,0x23,0x19]
44 // CHECK: rcwcasa x3, x5, [sp] // encoding: [0xe5,0x0b,0xa3,0x19]
[all …]
H A Ddirective-arch_extension-negative.s100 dc cvadp, x7
103 dc cvadp, x7
105 // CHECK-NEXT: dc cvadp, x7
128 dc cvap, x7
131 dc cvap, x7
133 // CHECK-NEXT: dc cvap, x7
184 sysp #0, c2, c0, #0, x0, x1
185 rcwcasp x0, x1, x6, x7, [x4]
189 sysp #0, c
[all...]
/llvm-project/llvm/test/MC/COFF/
H A Dcv-inline-linetable.s8 .type 0;
17 .p2align 4, 0x90
21 .cv_func_id 0
22 .cv_inline_site_id 1 within 0 inlined_at 1 15 3
24 .cv_loc 0 1 13 0 is_stmt 0 # t.cpp:13:0
25 # %bb.0: # %entry
27 .cv_loc 0 1 14 5 # t.cpp:14:5
42 .cv_loc 0 1 16 5 # t.cpp:16:5
44 .cv_loc 0 1 17 1 # t.cpp:17:1
51 # ASM-NEXT: 0: {{.*}} pushl %eax
[all …]
/llvm-project/llvm/test/CodeGen/PowerPC/GlobalISel/
H A Dirtranslator-args-lowering.ll8 ; CHECK: bb.1 (%ir-block.0):
15 ; CHECK: bb.1 (%ir-block.0):
17 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x3
18 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
25 ; CHECK: bb.1 (%ir-block.0):
27 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x3
34 ; CHECK: bb.1 (%ir-block.0):
35 ; CHECK: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9
36 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x3
37 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.image.d16.dim.ll9 ; GFX89: image_load v0, v[0:1], s[0:7] dmask:0x1 unorm d16{{$}}
10 ; GFX10: image_load v0, v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm d16{{$}}
11 ; GFX12: image_load v0, [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D d16
14 … call half @llvm.amdgcn.image.load.2d.f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
19 ; UNPACKED: image_load v[0:1], v[0:1], s[0:7] dmask:0x3 unorm d16{{$}}
20 ; PACKED: image_load v0, v[0:1], s[0:7] dmask:0x3 unorm d16{{$}}
21 ; GFX81: image_load v0, v[0:1], s[0:7] dmask:0x3 unorm d16{{$}}
22 ; GFX10: image_load v0, v[0:1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm d16{{$}}
23 ; GFX12: image_load v0, [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D d16
26 … x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
[all …]
/llvm-project/llvm/test/MC/Disassembler/AArch64/
H A Darmv8.5a-specrestrict.txt6 [0x81 0x03 0x38 0xd5]
11 [0xe8 0xd0 0x3b 0xd5]
12 [0xe7 0xd0 0x38 0xd5]
13 [0xe6 0xd0 0x3c 0xd5]
14 [0xe5 0xd0 0x3e 0xd5]
15 [0xe4 0xd0 0x3d 0xd5]
18 # CHECK: mrs x7, {{scxtnum_el1|SCXTNUM_EL1}}
23 # NOSPECID: mrs x7, S3_0_C13_C0_7
28 [0xe8 0xd0 0x1b 0xd5]
29 [0xe7 0xd0 0x18 0xd5]
[all …]
/llvm-project/llvm/include/llvm/IR/
H A DPseudoProbe.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
27 enum class PseudoProbeReservedId { Invalid = 0, Last = Invalid };
29 enum class PseudoProbeType { Block = 0, IndirectCall, DirectCall };
32 Reserved = 0x1,
33 Sentinel = 0x2, // A place holder for split function entry address.
34 HasDiscriminator = 0x4, // for probes with a discriminator
45 // [2:0] - 0x7, this is reserved for regular discriminator,
58 assert(Index <= 0xFFFF && "Probe index too big to encode, exceeding 2^16"); in packProbeData()
59 assert(Type <= 0x3 && "Probe type too big to encode, exceeding 3"); in packProbeData()
60 assert(Flags <= 0x7); in packProbeData()
[all …]
/llvm-project/clang/test/CodeGen/
H A Dattr-mode-enums.c30 // CHECK: [[X7:%.+]] = alloca i128 in main()
31 enum { A7, B7 } __attribute__((mode(TI))) x7 = A7; in main() local
36 // CHECK: store i8 0, ptr [[X1]] in main()
38 // CHECK: store i32 0, ptr [[X3]] in main()
40 // CHECK: store i8 0, ptr [[X5]] in main()
41 // CHECK: store i128 0, ptr [[X7]] in main()
44 return x1 + x2 + x3 + x4 + x5 + x6 + x7 + x8; in main()
/llvm-project/llvm/test/CodeGen/AArch64/Atomics/
H A Daarch64_be-atomicrmw-v8_1a.ll150 ; -O0: ccmp x8, x10, #0, eq
156 ; -O1: ccmp x5, x7, #0, eq
165 ; -O0: ccmp x8, x10, #0, eq
171 ; -O1: ccmp x5, x7, #0, eq
180 ; -O0: ccmp x8, x10, #0, eq
186 ; -O1: ccmp x5, x7, #0, eq
195 ; -O0: ccmp x8, x10, #0, eq
201 ; -O1: ccmp x5, x7, #0, eq
210 ; -O0: ccmp x8, x10, #0, eq
216 ; -O1: ccmp x5, x7, #0, eq
[all …]

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