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/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dfold-frame-offset-using-rr.mir18 bb.0.entry:
19 liveins: $x3, $x1, $x4, $x6
24 $x6 = LD 4, killed $x4
25 ; CHECK: $x6 = LDX killed $x4, killed $x3
34 bb.0.entry:
35 liveins: $x3, $x1, $x4, $x6
40 $x6 = LD 4, killed $x3
41 ; CHECK: $x6 = LDX killed $x4, killed $x3
50 bb.0.entry:
51 liveins: $x3, $x1, $x4, $x6
[all …]
H A Dmachine-backward-cp.mir12 bb.0.entry:
29 ; CHECK: bb.0.entry:
36 bb.0.entry:
56 bb.0.entry:
73 bb.0.entry:
75 ; CHECK: renamable $x4 = LI8 0
79 renamable $x4 = LI8 0
92 bb.0.entry:
97 ; CHECK: renamable $x4 = LI8 0
101 renamable $x4 = LI8 0
[all …]
H A Dlivephysregs.mir7 # CHECK-NEXT: liveins: $x30, $x29, $x3, $x6
8 # CHECK: $x4 = RLDICR killed $x6, 16, 47
15 - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$x30' }
19 bb.0:
22 $x6 = RLWINM8 $x3, 16, 16, 31
23 $x3 = RLDICL killed $x3, 0, 48
27 liveins: $x3, $x6, $x29, $x30
29 $x4 = RLDICR killed $x6, 16, 47
34 liveins: $x3, $x5, $x6, $x29, $x30
36 dead $x5 = ADD8 $x5, $x6
[all …]
H A Dexpand-isel-liveness.mir
/llvm-project/llvm/test/MC/AMDGPU/
H A Dsopk.s17 s_movk_i32 s2, 0x6
18 // GCN: s_movk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb0]
20 s_cmovk_i32 s2, 0x6
[all...]
/llvm-project/llvm/test/MC/RISCV/
H A Drv64zba-aliases-valid.s20 zext.w x5, x6
26 li x6, 0xfffffffe
34 li x5, 0xbbbbb0007bb
40 li x5, 0xbbbbb0000
48 li x6, -5372288229
56 li x6, 8953813715
64 li x6, -8953813715
72 li x6, 16116864687
80 li x6,
[all...]
/llvm-project/llvm/test/FileCheck/
H A Dcheck-dag-xfails.txt6 ; RUN: not FileCheck -check-prefix=X6 -input-file %s %s
15 ; X1-DAG: add [[REG1:r[0-9]+]], r1, r2
16 ; X1-DAG: add [[REG2:r[0-9]+]], r3, r4
27 ; X2-DAG: mul [[REG1:r[0-9]+]], r1, r2
28 ; X2-DAG: mul [[REG2:r[0-9]+]], r3, r4
39 ; X3-DAG: add [[REG1:r[0-9]+]], r1, r2
40 ; X3-DAG: add [[REG2:r[0-9]+]], r3, r4
52 ; X4-DAG: add [[REG1:r[0-9]+]], r1, r2
53 ; X4-DAG: add [[REG2:r[0-9]+]], r3, r4
66 ; X5-DAG: add [[REG1:r[0-9]+]], r1, r2
[all …]
/llvm-project/llvm/test/MC/AArch64/SVE/
H A Deon.s12 eon z5.b, z5.b, #0xf9
13 // CHECK-INST: eor z5.b, z5.b, #0x6
14 // CHECK-ENCODING: [0x25,0x3e,0x40,0x05]
18 eon z23.h, z23.h, #0xfff9
19 // CHECK-INST: eor z23.h, z23.h, #0x6
20 // CHECK-ENCODING: [0x37,0x7c,0x40,0x05]
24 eon z0.s, z0.s, #0xfffffff9
25 // CHECK-INST: eor z0.s, z0.s, #0x6
26 // CHECK-ENCODING: [0x20,0xf8,0x40,0x05]
30 eon z0.d, z0.d, #0xfffffffffffffff9
[all …]
H A Dorn.s12 orn z5.b, z5.b, #0xf9
13 // CHECK-INST: orr z5.b, z5.b, #0x6
14 // CHECK-ENCODING: [0x25,0x3e,0x00,0x05]
18 orn z23.h, z23.h, #0xfff9
19 // CHECK-INST: orr z23.h, z23.h, #0x6
20 // CHECK-ENCODING: [0x37,0x7c,0x00,0x05]
24 orn z0.s, z0.s, #0xfffffff9
25 // CHECK-INST: orr z0.s, z0.s, #0x6
26 // CHECK-ENCODING: [0x20,0xf8,0x00,0x05]
30 orn z0.d, z0.d, #0xfffffffffffffff9
[all …]
H A Dand.s12 and z5.b, z5.b, #0xf9
13 // CHECK-INST: and z5.b, z5.b, #0xf9
14 // CHECK-ENCODING: [0xa5,0x2e,0x80,0x05]
18 and z23.h, z23.h, #0xfff9
19 // CHECK-INST: and z23.h, z23.h, #0xfff9
20 // CHECK-ENCODING: [0xb7,0x6d,0x80,0x05]
24 and z0.s, z0.s, #0xfffffff9
25 // CHECK-INST: and z0.s, z0.s, #0xfffffff9
26 // CHECK-ENCODING: [0xa0,0xeb,0x80,0x05]
30 and z0.d, z0.d, #0xfffffffffffffff9
[all …]
H A Deor.s12 eor z5.b, z5.b, #0xf9
13 // CHECK-INST: eor z5.b, z5.b, #0xf9
14 // CHECK-ENCODING: [0xa5,0x2e,0x40,0x05]
18 eor z23.h, z23.h, #0xfff9
19 // CHECK-INST: eor z23.h, z23.h, #0xfff9
20 // CHECK-ENCODING: [0xb7,0x6d,0x40,0x05]
24 eor z0.s, z0.s, #0xfffffff9
25 // CHECK-INST: eor z0.s, z0.s, #0xfffffff9
26 // CHECK-ENCODING: [0xa0,0xeb,0x40,0x05]
30 eor z0.d, z0.d, #0xfffffffffffffff9
[all …]
H A Dorr.s14 orr z5.b, z5.b, #0xf9
15 // CHECK-INST: orr z5.b, z5.b, #0xf9
16 // CHECK-ENCODING: [0xa5,0x2e,0x00,0x05]
20 orr z23.h, z23.h, #0xfff9
21 // CHECK-INST: orr z23.h, z23.h, #0xfff9
22 // CHECK-ENCODING: [0xb7,0x6d,0x00,0x05]
26 orr z0.s, z0.s, #0xfffffff9
27 // CHECK-INST: orr z0.s, z0.s, #0xfffffff9
28 // CHECK-ENCODING: [0xa0,0xeb,0x00,0x05]
32 orr z0.d, z0.d, #0xfffffffffffffff9
[all …]
H A Dbic.s12 bic z5.b, z5.b, #0xf9
13 // CHECK-INST: and z5.b, z5.b, #0x6
14 // CHECK-ENCODING: [0x25,0x3e,0x80,0x05]
18 bic z23.h, z23.h, #0xfff9
19 // CHECK-INST: and z23.h, z23.h, #0x6
20 // CHECK-ENCODING: [0x37,0x7c,0x80,0x05]
24 bic z0.s, z0.s, #0xfffffff9
25 // CHECK-INST: and z0.s, z0.s, #0x6
26 // CHECK-ENCODING: [0x20,0xf8,0x80,0x05]
30 bic z0.d, z0.d, #0xfffffffffffffff9
[all …]
/llvm-project/bolt/test/AArch64/
H A Dtest-indirect-branch.s15 // adr x6, 0x219fb0 <sigall_set+0x88>
16 // add x6, x6, x14, lsl #2
17 // ldr w7, [x6]
18 // add x6, x6, w7, sxtw => no shift amount
19 // br x6
25 // adr x13, 0x215a1
[all...]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Di256-math.ll18 ; CHECK: // %bb.0:
21 ; CHECK-NEXT: adcs x2, x2, x6
30 ; CHECK: // %bb.0:
33 ; CHECK-NEXT: adcs x2, x2, x6
36 ; CHECK-NEXT: eor w4, w8, #0x1
39 %2 = extractvalue { i256, i1 } %1, 0
43 %6 = insertvalue { i256, i8 } undef, i256 %2, 0
50 ; CHECK: // %bb.0:
53 ; CHECK-NEXT: adcs x2, x2, x6
58 %2 = extractvalue { i256, i1 } %1, 0
[all …]
H A Ddump-schedule-trace.mir23 bb.0:
24 liveins: $x0, $x1, $x2, $x6, $q0
29 $x7 = ADDXrr $x6, $x6
31 # TOP-LABEL: *** Final schedule for %bb.0 ***
35 # TOP-NEXT: Cycle | 0 | 1 | 2 |
36 # TOP-NEXT: SU(0) | i | | |
46 # TOP-NEXT: SU(0) [TopReadyCycle = 0, BottomReadyCycle = 3]: dead %0
[all...]
H A Dandorbrcompare.ll9 ; SDISEL: // %bb.0: // %entry
11 ; SDISEL-NEXT: ccmp w0, w1, #0, ne
20 ; SDISEL-NEXT: mov w0, #1 // =0x1
21 ; SDISEL-NEXT: str w0, [x6]
25 ; GISEL: // %bb.0: // %entry
31 ; GISEL-NEXT: tbnz w8, #0, .LBB0_3
39 ; GISEL-NEXT: mov w0, #1 // =0x1
40 ; GISEL-NEXT: str w0, [x6]
55 ret i32 0
60 ; SDISEL: // %bb.0: // %entry
[all …]
H A Darm64-atomic-128.ll6 @var = global i128 0
10 ; NOOUTLINE: // %bb.0:
30 ; OUTLINE: // %bb.0:
45 ; LSE: // %bb.0:
55 %val = extractvalue { i128, i1 } %pair, 0
61 ; NOOUTLINE: // %bb.0:
81 ; OUTLINE: // %bb.0:
96 ; LSE: // %bb.0:
106 %val = extractvalue { i128, i1 } %pair, 0
112 ; NOOUTLINE: // %bb.0:
[all …]
H A Dmachine-outliner-all-stack.mir12 define void @reg-save-possible() #0 { ret void }
13 define void @stack-save1() #0 { ret void }
14 define void @stack-save2() #0 { ret void }
15 define void @stack-save3() #0 { ret void }
16 attributes #0 = { minsize noinline noredzone "frame-pointer"="all" }
23 bb.0:
32 ; CHECK-NEXT: BL [[FN:@OUTLINED_FUNCTION_[0-9]+]]
48 bb.0:
49 …liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15…
52 …liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15…
[all …]
/llvm-project/llvm/test/MC/RISCV/corev/
H A DXCVelw-invalid.s4 cv.elw t0, 0(0)
7 cv.elw 0, 0(x6)
10 cv.elw x12, 2048(x6)
16 cv.elw 0, x12(x6)
19 cv.elw x12, x12(x6)
22 cv.elw 0, 0(x6)
/llvm-project/llvm/test/MC/Disassembler/AArch64/
H A Dtrace-regs.txt4 0x8 0x3 0x31 0xd5
6 0xc9 0x0 0x31 0xd5
8 0xcb 0x1 0x31 0xd5
10 0xd9 0x2 0x31 0xd5
12 0xc7 0x3 0x31 0xd5
14 0xc7 0x4 0x31 0xd5
16 0xc6 0x5 0x31 0xd5
17 # CHECK: mrs x6, {{trcidr13|TRCIDR13}}
18 0xfb 0x8 0x31 0xd5
20 0xfd 0x9 0x31 0xd5
[all …]
/llvm-project/llvm/test/tools/llvm-dwarfdump/X86/
H A Dtombstone.s11 # CHECK: DW_AT_ranges [DW_FORM_sec_offset] (0x00000000
12 # CHECK-NEXT: [0x00000042, 0x00000048))
14 # CHECK: DW_AT_low_pc [DW_FORM_addr] (0xffffffff (dead code))
15 # CHECK: DW_AT_high_pc [DW_FORM_data4] (0x00000006)
17 # CHECK: DW_AT_low_pc [DW_FORM_addr] (0x00000042)
18 # CHECK: DW_AT_high_pc [DW_FORM_data4] (0x00000006)
21 # CHECK: DW_AT_ranges [DW_FORM_sec_offset] (0x0000000c
22 # CHECK-NEXT: [0x00000042, 0x00000048)
23 # CHECK-NEXT: [0x00000042, 0x00000048)
24 # CHECK-NEXT: [0x00000042, 0x00000048)
[all …]
/llvm-project/clang/test/Sema/
H A Dattr-regparm.c5 __attribute((regparm(-1))) int x2(void); // expected-error{{'regparm' parameter must be between 0 a…
6 __attribute((regparm(5))) int x3(void); // expected-error{{'regparm' parameter must be between 0 an…
13 [[gnu::regparm(3)]] void x6(int); // expected-note{{previous declaration is here}}
14 [[gnu::regparm(2)]] void x6(int); // expected-error{{function declared with regparm(2) attribute wa…
15 void x6 [[gnu::regparm(3)]] (int);
16 void [[gnu::regparm(3)]] x6(int); // expected-warning{{'regparm' only applies to function types; ty…
17 void x6(int) [[gnu::regparm(3)]]; // expected-warning{{GCC does not allow the 'regparm' attribute t…
/llvm-project/llvm/test/CodeGen/X86/
H A Davx512-trunc.ll6 attributes #0 = { nounwind }
8 define <16 x i8> @trunc_16x32_to_16x8(<16 x i32> %i) #0 {
10 ; ALL: ## %bb.0:
18 define <8 x i16> @trunc_8x64_to_8x16(<8 x i64> %i) #0 {
20 ; ALL: ## %bb.0:
28 define <16 x i16> @trunc_v16i32_to_v16i16(<16 x i32> %x) #0 {
30 ; ALL: ## %bb.0:
37 define <8 x i8> @trunc_qb_512(<8 x i64> %i) #0 {
39 ; ALL: ## %bb.0:
47 define void @trunc_qb_512_mem(<8 x i64> %i, ptr %res) #0 {
[all …]
/llvm-project/lld/test/ELF/
H A Daarch64-tstbr14-reloc.s20 # CHECK-NEXT: 21013c: tbnz w3, #15, 0x210120 <_foo>
21 # CHECK-NEXT: 210140: tbnz w3, #15, 0x210130 <_bar>
22 # CHECK-NEXT: 210144: tbz x6, #45, 0x210120 <_foo>
23 # CHECK-NEXT: 210148: tbz x6, #45, 0x210130 <_bar>
33 #DSOREL-NEXT: Address: 0x30420
34 #DSOREL-NEXT: Offset: 0x420
36 #DSOREL-NEXT: Link: 0
37 #DSOREL-NEXT: Info: 0
39 #DSOREL-NEXT: EntrySize: 0
43 #DSOREL-NEXT: 0x30438 R_AARCH64_JUMP_SLOT _foo
[all …]

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