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/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx9_flat.txt3 # CHECK: flat_load_ubyte v5, v[1:2] offset:4095 ; encoding: [0xff,0x0f,0x40,0xdc,0x01,0x00,0x00,0x…
4 0xff,0x0f,0x40,0xdc,0x01,0x00,0x00,0x05
6 # CHECK: flat_load_ubyte v255, v[1:2] offset:4095 ; encoding: [0xff,0x0f,0x40,0xdc,0x01,0x00,0x00,0…
7 0xff,0x0f,0x40,0xdc,0x01,0x00,0x00,0xff
9 …K: flat_load_ubyte v5, v[254:255] offset:4095 ; encoding: [0xff,0x0f,0x40,0xdc,0xfe,0x00,0x00,0x05]
10 0xff,0x0f,0x40,0xdc,0xfe,0x00,0x00,0x05
12 # CHECK: flat_load_ubyte v5, v[1:2] ; encoding: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0x…
13 0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0x05
15 # CHECK: flat_load_ubyte v5, v[1:2] offset:7 ; encoding: [0x07,0x00,0x40,0xdc,0x01,0x00,0x00,0x…
16 0x07,0x00,0x40,0xdc,0x01,0x00,0x00,0x05
[all …]
/llvm-project/llvm/unittests/ExecutionEngine/JITLink/
H A DEHFrameSupportTests.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
39 0xcf, 0xfa, 0xed, 0xfe, 0x0c, 0x00, 0x00, 0x01, 0x0
[all...]
/llvm-project/llvm/test/tools/llvm-readtapi/Inputs/
H A Dmixed-swift-objc.yaml3 magic: 0xFEEDFACF
4 cputype: 0x1000007
5 cpusubtype: 0x3
6 filetype: 0x6
9 flags: 0x110085
10 reserved: 0x0
15 vmaddr: 0
17 fileoff: 0
22 flags: 0
26 addr: 0x1B30
[all …]
/llvm-project/llvm/test/MC/AArch64/
H A Dneon-scalar-by-elem-saturating-mul.s10 sqdmull d1, s1, v4.s[0]
12 sqdmull d9, s10, v15.s[0]
15 // CHECK: sqdmull s1, h1, v1.h[1] // encoding: [0x21,0xb0,0x51,0x5f]
16 // CHECK: sqdmull s8, h2, v5.h[2] // encoding: [0x48,0xb0,0x65,0x5f]
17 // CHECK: sqdmull s12, h17, v9.h[3] // encoding: [0x2c,0xb2,0x79,0x5f]
18 // CHECK: sqdmull s31, h31, v15.h[7] // encoding: [0xff,0xbb,0x7f,0x5f]
19 // CHECK: sqdmull d1, s1, v4.s[0] // encoding: [0x21,0xb0,0x84,0x5f]
20 // CHECK: sqdmull d31, s31, v31.s[3] // encoding: [0xff,0xbb,0xbf,0x5f]
21 // CHECK: sqdmull d9, s10, v15.s[0] // encoding: [0x49,0xb1,0x8f,0x5f]
27 sqdmulh h0, h1, v0.h[0]
[all …]
H A Dneon-scalar-by-elem-saturating-mla.s6 sqdmlal s0, h0, v0.h[0]
10 sqdmlal d0, s0, v3.s[0]
14 // CHECK: sqdmlal s0, h0, v0.h[0] // encoding: [0x00,0x30,0x40,0x5f]
15 // CHECK: sqdmlal s7, h1, v4.h[3] // encoding: [0x27,0x30,0x74,0x5f]
16 // CHECK: sqdmlal s11, h16, v8.h[4] // encoding: [0x0b,0x3a,0x48,0x5f]
17 // CHECK: sqdmlal s30, h30, v15.h[7] // encoding: [0xde,0x3b,0x7f,0x5f]
18 // CHECK: sqdmlal d0, s0, v3.s[0] // encoding: [0x00,0x30,0x83,0x5f]
19 // CHECK: sqdmlal d30, s30, v30.s[3] // encoding: [0xde,0x3b,0xbe,0x5f]
20 // CHECK: sqdmlal d8, s9, v14.s[1] // encoding: [0x28,0x31,0xae,0x5f]
25 sqdmlsl s1, h1, v1.h[0]
[all …]
H A Dneon-scalar-by-elem-mla.s7 fmla s0, s1, v1.s[0]
11 fmla d0, d1, v1.d[0]
14 // CHECK: fmla h0, h1, v1.h[5] // encoding: [0x20,0x18,0x11,0x5f]
15 // CHECK: fmla s0, s1, v1.s[0] // encoding: [0x20,0x10,0x81,0x5f]
16 // CHECK: fmla s30, s11, v1.s[1] // encoding: [0x7e,0x11,0xa1,0x5f]
17 // CHECK: fmla s4, s5, v7.s[2] // encoding: [0xa4,0x18,0x87,0x5f]
18 // CHECK: fmla s16, s22, v16.s[3] // encoding: [0xd0,0x1a,0xb0,0x5f]
19 // CHECK: fmla d0, d1, v1.d[0] // encoding: [0x20,0x10,0xc1,0x5f]
20 // CHECK: fmla d30, d11, v1.d[1] // encoding: [0x7e,0x19,0xc1,0x5f]
27 fmls s2, s3, v4.s[0]
[all …]
H A Darmv9.5a-tlbiw.s6 // CHECK-TLBIW: tlbi vmallws2e1 // encoding: [0x5f,0x86,0x0c,0xd5]
10 // CHECK-TLBIW: tlbi vmallws2e1is // encoding: [0x5f,0x82,0x0c,0xd5]
14 // CHECK-TLBIW: tlbi vmallws2e1os // encoding: [0x5f,0x85,0x0c,0xd5]
18 // CHECK-XS: tlbi vmallws2e1nxs // encoding: [0x5f,0x96,0x0c,0xd5]
22 // CHECK-XS: tlbi vmallws2e1isnxs // encoding: [0x5f,0x92,0x0c,0xd5]
26 // CHECK-XS: tlbi vmallws2e1osnxs // encoding: [0x5f,0x95,0x0c,0xd5]
H A Dneon-scalar-by-elem-mul.s7 fmul s0, s1, v1.s[0]
11 fmul d0, d1, v1.d[0]
14 // CHECK: fmul h0, h1, v1.h[5] // encoding: [0x20,0x98,0x11,0x5f]
15 // CHECK: fmul s0, s1, v1.s[0] // encoding: [0x20,0x90,0x81,0x5f]
16 // CHECK: fmul s30, s11, v1.s[1] // encoding: [0x7e,0x91,0xa1,0x5f]
17 // CHECK: fmul s4, s5, v7.s[2] // encoding: [0xa4,0x98,0x87,0x5f]
18 // CHECK: fmul s16, s22, v16.s[3] // encoding: [0xd0,0x9a,0xb0,0x5f]
19 // CHECK: fmul d0, d1, v1.d[0] // encoding: [0x20,0x90,0xc1,0x5f]
20 // CHECK: fmul d30, d11, v1.d[1] // encoding: [0x7e,0x99,0xc1,0x5f]
27 fmulx s6, s2, v8.s[0]
[all …]
H A Dneon-scalar-shift-imm.s10 // CHECK: sshr d15, d16, #12 // encoding: [0x0f,0x06,0x74,0x5f]
17 // CHECK: ushr d10, d17, #18 // encoding: [0x2a,0x06,0x6e,0x7f]
24 // CHECK: srshr d19, d18, #7 // encoding: [0x53,0x26,0x79,0x5f]
31 // CHECK: urshr d20, d23, #31 // encoding: [0xf4,0x26,0x61,0x7f]
38 // CHECK: ssra d18, d12, #21 // encoding: [0x92,0x15,0x6b,0x5f]
45 // CHECK: usra d20, d13, #61 // encoding: [0xb4,0x15,0x43,0x7f]
52 // CHECK: srsra d15, d11, #19 // encoding: [0x6f,0x35,0x6d,0x5f]
59 // CHECK: ursra d18, d10, #13 // encoding: [0x52,0x35,0x73,0x7f]
66 // CHECK: shl d7, d10, #12 // encoding: [0x47,0x55,0x4c,0x5f]
76 // CHECK: sqshl b11, b19, #7 // encoding: [0x6b,0x76,0x0f,0x5f]
[all …]
/llvm-project/llvm/test/MC/Disassembler/ARM/
H A Dmve-scalar-shift.txt5 [0x50 0xea 0xef 0x51]
6 # CHECK: asrl r0, r1, #23 @ encoding: [0x50,0xea,0xef,0x51]
9 [0x5e 0xea 0xef 0x61]
10 # CHECK: asrl lr, r1, #27 @ encoding: [0x5e,0xea,0xef,0x61]
13 [0x50 0xea 0x2d 0x41]
14 # CHECK: asrl r0, r1, r4 @ encoding: [0x50,0xea,0x2d,0x41]
17 [0x5e 0xea 0xcf 0x21]
18 # CHECK: lsll lr, r1, #11 @ encoding: [0x5e,0xea,0xcf,0x21]
21 [0x5e 0xea 0x0d 0x41]
22 # CHECK: lsll lr, r1, r4 @ encoding: [0x5e,0xea,0x0d,0x41]
[all …]
H A Dunpredictable-ADDREXT3-arm.txt4 # CHECK: 0xd1 0xf1 0x5f 0x01
5 0xd1 0xf1 0x5f 0x01
7 # CHECK: 0xf1 0xf1 0x5f 0x01
8 0xf1 0xf1 0x5f 0x01
10 # CHECK: 0xf1 0xf1 0x5f 0x01
11 0xf1 0xf1 0x5f 0x01
13 # CHECK: 0xd1 0xe1 0x4f 0x01
14 0xd1 0xe1 0x4f 0x01
H A Dthumbv8.1m.s4 [0x52 0xea 0x22 0x9e]
5 # CHECK: cinc lr, r2, lo @ encoding: [0x52,0xea,0x22,0x9e]
7 [0x57 0xea 0x47 0x9e]
8 # CHECK: cinc lr, r7, pl @ encoding: [0x57,0xea,0x47,0x9e]
10 [0x5c 0xea 0x3c 0xae]
11 # CHECK: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
13 [0x5a 0xea 0x3a 0xbe]
14 # CHECK: cneg lr, r10, hs @ encoding: [0x5a,0xea,0x3a,0xbe]
16 [0x59 0xea 0x7b 0x89]
17 # CHECK: csel r9, r9, r11, vc @ encoding: [0x59,0xea,0x7b,0x89]
[all …]
H A Dload-store-acquire-release-v8-thumb.txt3 0xd4 0xe8 0xcf 0x3f
4 0xd5 0xe8 0xdf 0x2f
5 0xd7 0xe8 0xef 0x1f
6 0xd8 0xe8 0xff 0x67
7 # CHECK: ldaexb r3, [r4] @ encoding: [0xd4,0xe8,0xcf,0x3f]
8 # CHECK: ldaexh r2, [r5] @ encoding: [0xd5,0xe8,0xdf,0x2f]
9 # CHECK: ldaex r1, [r7] @ encoding: [0xd7,0xe8,0xef,0x1f]
10 # CHECK: ldaexd r6, r7, [r8] @ encoding: [0xd8,0xe8,0xff,0x67]
12 0xc4 0xe8 0xc1 0x3f
13 0xc5 0xe8 0xd4 0x2f
[all …]
/llvm-project/llvm/test/MC/Disassembler/AArch64/
H A Darmv9.5a-tlbiw.txt5 [0x5f,0x86,0x0c,0xd5]
9 [0x5f,0x82,0x0c,0xd5]
13 [0x5f,0x85,0x0c,0xd5]
17 [0x5f,0x96,0x0c,0xd5]
21 [0x5f,0x92,0x0c,0xd5]
25 [0x5f,0x95,0x0c,0xd5]
H A Darmv8.1a-atomic.txt3 0x41,0x7c,0xa0,0x08
4 0x41,0x7c,0xe0,0x08
5 0x41,0xfc,0xa0,0x08
6 0x41,0xfc,0xe0,0x08
7 0x41,0x7c,0xa0,0x48
8 0x41,0x7c,0xe0,0x48
9 0x41,0xfc,0xa0,0x48
10 0x41,0xfc,0xe0,0x48
20 0x41,0x7c,0xa0,0x88
21 0x41,0x7c,0xe0,0x88
[all …]
/llvm-project/llvm/test/MC/AMDGPU/
H A Dgfx9_asm_flat.s4 // CHECK: [0xff,0x0f,0x40,0xdc,0x01,0x00,0x00,0x05]
7 // CHECK: [0xff,0x0f,0x40,0xdc,0x01,0x00,0x00,0xff]
10 // CHECK: [0xff,0x0f,0x40,0xdc,0xfe,0x00,0x00,0x05]
13 // CHECK: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0x05]
15 flat_load_ubyte v5, v[1:2] offset:0
16 // CHECK: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0x05]
19 // CHECK: [0x07,0x00,0x40,0xdc,0x01,0x00,0x00,0x05]
22 // CHECK: [0xff,0x0f,0x41,0xdc,0x01,0x00,0x00,0x05]
25 // CHECK: [0xff,0x0f,0x42,0xdc,0x01,0x00,0x00,0x05]
28 // CHECK: [0xff,0x0f,0x44,0xdc,0x01,0x00,0x00,0x05]
[all …]
/llvm-project/llvm/test/MC/X86/
H A Davx5124fmaps-att.s6 // CHECK: encoding: [0x62,0xe2,0x5f,0x40,0x9a,0x08]
9 // CHECK: encoding: [0x62,0xf2,0x3f,0x49,0x9a,0x18]
12 // CHECK: encoding: [0x62,0xf2,0x5f,0xc9,0x9a,0x28]
16 // CHECK: encoding: [0x62,0xe2,0x5f,0x00,0x9b,0x08]
19 // CHECK: encoding: [0x62,0xf2,0x3f,0x09,0x9b,0x18]
22 // CHECK: encoding: [0x62,0xf2,0x5f,0x89,0x9b,0x28]
26 // CHECK: encoding: [0x62,0xe2,0x5f,0x40,0xaa,0x08]
29 // CHECK: encoding: [0x62,0xf2,0x3f,0x49,0xaa,0x18]
32 // CHECK: encoding: [0x62,0xf2,0x5f,0xc9,0xaa,0x28]
36 // CHECK: encoding: [0x62,0xe2,0x5f,0x00,0xab,0x08]
[all …]
H A Davx512vp2intersect-32-intel.s4 # CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2]
8 # CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07]
12 # CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07]
16 # CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2]
20 # CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07]
24 # CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07]
28 # CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0xf7]
32 # CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0x36]
36 # CHECK: encoding: [0x62,0xf2,0xdf,0x58,0x68,0x36]
40 # CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0xf7]
[all …]
H A Davx512vp2intersect-32-att.s4 # CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2]
8 # CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07]
12 # CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07]
16 # CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2]
20 # CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07]
24 # CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07]
28 # CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0xf7]
32 # CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0x36]
36 # CHECK: encoding: [0x62,0xf2,0xdf,0x58,0x68,0x36]
40 # CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0xf7]
[all …]
H A Davx5124vnniw-att.s4 // CHECK: encoding: [0x62,0xe2,0x5f,0x40,0x52,0x08]
7 // CHECK: encoding: [0x62,0xf2,0x3f,0x49,0x52,0x18]
10 // CHECK: encoding: [0x62,0xf2,0x5f,0xc9,0x52,0x28]
14 // CHECK: encoding: [0x62,0xe2,0x5f,0x40,0x53,0x08]
17 // CHECK: encoding: [0x62,0xf2,0x3f,0x49,0x53,0x18]
20 // CHECK: encoding: [0x62,0xf2,0x5f,0xc9,0x53,0x28]
/llvm-project/llvm/test/MC/Disassembler/X86/
H A Davx512vp2intersect-32.txt6 0x62,0xf2,0xf7,0x48,0x68,0xc2
10 0x62,0xf2,0xf7,0x48,0x68,0x07
14 0x62,0xf2,0xf7,0x58,0x68,0x07
18 0x62,0xf2,0xf7,0x48,0x68,0xc2
22 0x62,0xf2,0xf7,0x48,0x68,0x07
26 0x62,0xf2,0xf7,0x58,0x68,0x07
30 0x62,0xf2,0xdf,0x48,0x68,0xf7
34 0x62,0xf2,0xdf,0x48,0x68,0x36
38 0x62,0xf2,0xdf,0x58,0x68,0x36
42 0x62,0xf2,0xdf,0x48,0x68,0xf7
[all …]
/llvm-project/llvm/test/CodeGen/X86/
H A Davx512fp16-fmaxnum.ll13 ; CHECK: # %bb.0:
14 ; CHECK-NEXT: vmaxsh %xmm0, %xmm1, %xmm2 # encoding: [0x62,0xf5,0x76,0x08,0x5f,0xd0]
15 ; CHECK-NEXT: vcmpunordsh %xmm0, %xmm0, %k1 # encoding: [0x62,0xf3,0x7e,0x08,0xc2,0xc8,0x03]
16 ; CHECK-NEXT: vmovsh %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf5,0x7e,0x09,0x10,0xd1]
17 ; CHECK-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
18 ; CHECK-NEXT: retq # encoding: [0xc3]
25 ; CHECK: # %bb.0:
26 ; CHECK-NEXT: vmaxph %xmm0, %xmm1, %xmm2 # encoding: [0x62,0xf5,0x74,0x08,0x5f,0xd0]
27 ; CHECK-NEXT: vcmpunordph %xmm0, %xmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x08,0xc2,0xc8,0x03]
28 ; CHECK-NEXT: vmovdqu16 %xmm1, %xmm2 {%k1} # encoding: [0x62,0xf1,0xff,0x09,0x6f,0xd1]
[all …]
/llvm-project/llvm/test/MC/VE/
H A DCVTDL.s7 # CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x0b,0x5f]
11 # CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x3f,0x0b,0x5f]
15 # CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x40,0x0b,0x5f]
19 # CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x7f,0x0b,0x5f]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dvertex-fetch-encoding.ll6 …: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]…
7 …: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[GPR]],0x00,0x0[[GPR]…
16 …READ_128 T[[DST:[0-9]]].XYZW, T[[SRC:[0-9]]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[SRC]],0x40,0x0[[…
17 …READ_128 T[[DST:[0-9]]].XYZW, T[[SRC:[0-9]]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[SRC]],0x00,0x0[[…
26 …: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #3 ; encoding: [0x40,0x03,0x0[[GPR]],0x10,0x0[[GPR]…
27 …: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #3 ; encoding: [0x40,0x03,0x0[[GPR]],0x00,0x0[[GPR]…
36 …: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #2 ; encoding: [0x40,0x02,0x0[[GPR]],0x10,0x0[[GPR]…
37 …: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #2 ; encoding: [0x40,0x02,0x0[[GPR]],0x00,0x0[[GPR]…
39 @t = internal addrspace(4) constant [4 x i32] [i32 0, i32 1, i32 2, i32 3]
42 %a = getelementptr inbounds [4 x i32], ptr addrspace(4) @t, i32 0, i32 %in
/llvm-project/llvm/test/MC/ARM/
H A Dmve-scalar-shift.s11 # CHECK: asrl r0, r1, #23 @ encoding: [0x50,0xea,0xef,0x51]
12 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
15 # CHECK: asrl lr, r1, #27 @ encoding: [0x5e,0xea,0xef,0x61]
16 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
19 # CHECK: it eq @ encoding: [0x08,0xbf]
20 # CHECK-NEXT: asrleq lr, r1, #27 @ encoding: [0x5e,0xea,0xef,0x61]
24 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid instruction
25 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
28 # ERROR: [[@LINE+3]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
29 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r…
[all …]

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