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/llvm-project/llvm/test/MC/Disassembler/Mips/micromips32r3/
H A Dvalid-fp64.txt4 0x54 0x0c 0x0a 0x3b # CHECK: sqrt.s $f0, $f12
5 0x54 0x0c 0x03 0x7b # CHECK: abs.s $f0, $f12
6 0x54 0x0c 0x4a 0x3b # CHECK: sqrt.d $f0, $f12
7 0x54 0x0c 0x23 0x7b # CHECK: abs.d $f0, $f12
8 0x54 0x80 0x38 0x3b # CHECK: mthc1 $4, $f0
9 0x54 0x80 0x30 0x3b # CHECK: mfhc1 $4, $f0
10 0x54 0x82 0x01 0x30 # CHECK: add.d $f0, $f2, $f4
11 0x54 0x82 0x01 0x70 # CHECK: sub.d $f0, $f2, $f4
12 0x54 0x82 0x01 0xb0 # CHECK: mul.d $f0, $f2, $f4
13 0x54 0x82 0x01 0xf0 # CHECK: div.d $f0, $f2, $f4
[all …]
H A Dvalid-fp64-el.txt4 0x0c 0x54 0x3b 0x0a # CHECK: sqrt.s $f0, $f12
5 0x0c 0x54 0x7b 0x03 # CHECK: abs.s $f0, $f12
6 0x0c 0x54 0x3b 0x4a # CHECK: sqrt.d $f0, $f12
7 0x0c 0x54 0x7b 0x23 # CHECK: abs.d $f0, $f12
8 0x80 0x54 0x3b 0x38 # CHECK: mthc1 $4, $f0
9 0x80 0x54 0x3b 0x30 # CHECK: mfhc1 $4, $f0
10 0x82 0x54 0x30 0x01 # CHECK: add.d $f0, $f2, $f4
11 0x82 0x54 0x70 0x01 # CHECK: sub.d $f0, $f2, $f4
12 0x82 0x54 0xb0 0x01 # CHECK: mul.d $f0, $f2, $f4
13 0x82 0x54 0xf0 0x01 # CHECK: div.d $f0, $f2, $f4
[all …]
H A Dvalid.txt4 0x4f 0xf9 # CHECK: addiusp -16
5 0x4f 0xff # CHECK: addiusp -1028
6 0x4f 0xfd # CHECK: addiusp -1032
7 0x4c 0x01 # CHECK: addiusp 1024
8 0x4c 0x03 # CHECK: addiusp 1028
9 0x2c 0x29 # CHECK: andi16 $16, $2, 31
10 0x47 0x05 # CHECK: jraddiusp 20
11 0x07 0x42 # CHECK: addu16 $6, $17, $4
12 0x06 0xb1 # CHECK: subu16 $5, $16, $3
13 0x44 0x82 # CHECK: and16 $16, $2
[all …]
H A Dvalid-el.txt4 0xf9 0x4f # CHECK: addiusp -16
5 0xff 0x4f # CHECK: addiusp -1028
6 0xfd 0x4f # CHECK: addiusp -1032
7 0x01 0x4c # CHECK: addiusp 1024
8 0x03 0x4c # CHECK: addiusp 1028
9 0x29 0x2c # CHECK: andi16 $16, $2, 31
10 0x05 0x47 # CHECK: jraddiusp 20
11 0x42 0x07 # CHECK: addu16 $6, $17, $4
12 0xb1 0x06 # CHECK: subu16 $5, $16, $3
13 0x82 0x44 # CHECK: and16 $16, $2
[all …]
/llvm-project/llvm/test/MC/Disassembler/Mips/micromips32r6/
H A Dvalid.txt3 0x6f 0x83 # CHECK: addiur1sp $7, 4
4 0x6f 0x7e # CHECK: addiur2 $6, $7, -1
5 0x6f 0x76 # CHECK: addiur2 $6, $7, 12
6 0x4c 0xfc # CHECK: addius5 $7, -2
7 0x4f 0xff # CHECK: addiusp -1028
8 0x4f 0xfd # CHECK: addiusp -1032
9 0x4c 0x01 # CHECK: addiusp 1024
10 0x4c 0x03 # CHECK: addiusp 1028
11 0x4f 0xf9 # CHECK: addiusp -16
12 0xcc 0x42 # CHECK: bc16 132
[all …]
/llvm-project/llvm/test/MC/Mips/
H A Dmicromips-fpu-instructions.s12 # CHECK-EL: add.s $f4, $f6, $f8 # encoding: [0x06,0x55,0x30,0x20]
13 # CHECK-EL: add.d $f4, $f6, $f8 # encoding: [0x06,0x55,0x30,0x21]
14 # CHECK-EL: div.s $f4, $f6, $f8 # encoding: [0x06,0x55,0xf0,0x20]
15 # CHECK-EL: div.d $f4, $f6, $f8 # encoding: [0x06,0x55,0xf0,0x21]
16 # CHECK-EL: mul.s $f4, $f6, $f8 # encoding: [0x06,0x55,0xb0,0x20]
17 # CHECK-EL: mul.d $f4, $f6, $f8 # encoding: [0x06,0x55,0xb0,0x21]
18 # CHECK-EL: sub.s $f4, $f6, $f8 # encoding: [0x06,0x55,0x70,0x20]
19 # CHECK-EL: sub.d $f4, $f6, $f8 # encoding: [0x06,0x55,0x70,0x21]
20 # CHECK-EL: lwc1 $f2, 4($6) # encoding: [0x46,0x9c,0x04,0x00]
21 # CHECK-EL: ldc1 $f2, 4($6) # encoding: [0x46,0xbc,0x04,0x00]
[all …]
/llvm-project/llvm/test/MC/X86/
H A Davx512vl_bitalg-att.s4 // CHECK: encoding: [0x62,0xa2,0x7d,0x08,0x54,0xef]
8 // CHECK: encoding: [0x62,0xa2,0xfd,0x08,0x54,0xef]
12 // CHECK: encoding: [0x62,0xf2,0x7d,0x0a,0x54,0xcb]
16 // CHECK: encoding: [0x62,0xf2,0xfd,0x0a,0x54,0xcb]
20 // CHECK: encoding: [0x62,0xf2,0x7d,0x08,0x54,0x09]
24 // CHECK: encoding: [0x62,0xf2,0x7d,0x08,0x54,0x4c,0x24,0xfc]
28 // CHECK: encoding: [0x62,0xf2,0x7d,0x08,0x54,0x4c,0x24,0x04]
32 // CHECK: encoding: [0x62,0xb2,0x7d,0x08,0x54,0x8c,0xf1,0x00,0x00,0x00,0x10]
36 // CHECK: encoding: [0x62,0xb2,0x7d,0x08,0x54,0x8c,0xf1,0x00,0x00,0x00,0xe0]
40 // CHECK: encoding: [0x62,0xb2,0x7d,0x08,0x54,0x8c,0xf1,0x02,0x00,0x00,0xe0]
[all …]
H A Davx512bitalg-intel.s4 # CHECK: encoding: [0x62,0xa2,0x7d,0x48,0x54,0xef]
8 # CHECK: encoding: [0x62,0xa2,0xfd,0x48,0x54,0xef]
12 # CHECK: encoding: [0x62,0xf2,0x7d,0x4a,0x54,0xcb]
16 # CHECK: encoding: [0x62,0xf2,0xfd,0x4a,0x54,0xcb]
20 # CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x09]
24 # CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x4c,0x24,0xfc]
28 # CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x4c,0x24,0x04]
32 # CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0x10]
36 # CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0xe0]
40 # CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x02,0x00,0x00,0xe0]
[all …]
H A Davx512bitalg-att.s4 # CHECK: encoding: [0x62,0xa2,0x7d,0x48,0x54,0xef]
8 # CHECK: encoding: [0x62,0xa2,0xfd,0x48,0x54,0xef]
12 # CHECK: encoding: [0x62,0xf2,0x7d,0x4a,0x54,0xcb]
16 # CHECK: encoding: [0x62,0xf2,0xfd,0x4a,0x54,0xcb]
20 # CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x09]
24 # CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x4c,0x24,0xfc]
28 # CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x4c,0x24,0x04]
32 # CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0x10]
36 # CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0xe0]
40 # CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x02,0x00,0x00,0xe0]
[all …]
/llvm-project/llvm/test/MC/X86/apx/
H A Dcmov-intel.s4 # CHECK: encoding: [0x62,0xf4,0x35,0x18,0x42,0xc2]
7 # CHECK: encoding: [0x62,0xf4,0x2c,0x18,0x42,0xd1]
10 # CHECK: encoding: [0x62,0x54,0xa4,0x18,0x42,0xf9]
13 # CHECK: encoding: [0x62,0xd4,0x7d,0x18,0x42,0x54,0x80,0x7b]
16 # CHECK: encoding: [0x62,0xd4,0x6c,0x18,0x42,0x4c,0x80,0x7b]
19 # CHECK: encoding: [0x62,0x54,0x84,0x18,0x42,0x4c,0x80,0x7b]
22 # CHECK: encoding: [0x62,0xf4,0x35,0x18,0x46,0xc2]
25 # CHECK: encoding: [0x62,0xf4,0x2c,0x18,0x46,0xd1]
28 # CHECK: encoding: [0x62,0x54,0xa4,0x18,0x46,0xf9]
31 # CHECK: encoding: [0x62,0xd4,0x7d,0x18,0x46,0x54,0x80,0x7b]
[all …]
H A Dcmov-att.s7 # CHECK: encoding: [0x62,0xf4,0x35,0x18,0x42,0xc2]
10 # CHECK: encoding: [0x62,0xf4,0x2c,0x18,0x42,0xd1]
13 # CHECK: encoding: [0x62,0x54,0xa4,0x18,0x42,0xf9]
16 # CHECK: encoding: [0x62,0xd4,0x7d,0x18,0x42,0x54,0x80,0x7b]
19 # CHECK: encoding: [0x62,0xd4,0x6c,0x18,0x42,0x4c,0x80,0x7b]
22 # CHECK: encoding: [0x62,0x54,0x84,0x18,0x42,0x4c,0x80,0x7b]
25 # CHECK: encoding: [0x62,0xf4,0x35,0x18,0x46,0xc2]
28 # CHECK: encoding: [0x62,0xf4,0x2c,0x18,0x46,0xd1]
31 # CHECK: encoding: [0x62,0x54,0xa4,0x18,0x46,0xf9]
34 # CHECK: encoding: [0x62,0xd4,0x7d,0x18,0x46,0x54,0x80,0x7b]
[all …]
/llvm-project/llvm/test/MC/Disassembler/X86/apx/
H A Dcmov.txt6 0x62,0xf4,0x35,0x18,0x42,0xc2
10 0x62,0xf4,0x2c,0x18,0x42,0xd1
14 0x62,0x54,0xa4,0x18,0x42,0xf9
18 0x62,0xd4,0x7d,0x18,0x42,0x54,0x80,0x7b
22 0x62,0xd4,0x6c,0x18,0x42,0x4c,0x80,0x7b
26 0x62,0x54,0x84,0x18,0x42,0x4c,0x80,0x7b
30 0x62,0xf4,0x35,0x18,0x46,0xc2
34 0x62,0xf4,0x2c,0x18,0x46,0xd1
38 0x62,0x54,0xa4,0x18,0x46,0xf9
42 0x62,0xd4,0x7d,0x18,0x46,0x54,0x80,0x7b
[all …]
/llvm-project/llvm/test/MC/Mips/micromips/
H A Dvalid-fp64.s5 abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x54,0x0c,0x23,0x7b]
6 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64_MM
7 abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b]
8 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM
9 add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x30]
10 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64_MM
11 cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x54,0x02,0x13,0x7b]
12 # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_S_MM
13 cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x54,0x02,0x33,0x7b]
14 # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_W_MM
[all …]
/llvm-project/llvm/test/MC/Disassembler/X86/
H A Davx512bitalg.txt6 0x62,0xa2,0x7d,0x48,0x54,0xef
10 0x62,0xa2,0xfd,0x48,0x54,0xef
14 0x62,0xf2,0x7d,0x4a,0x54,0xcb
18 0x62,0xf2,0xfd,0x4a,0x54,0xcb
22 0x62,0xf2,0x7d,0x48,0x54,0x09
26 0x62,0xf2,0x7d,0x48,0x54,0x4c,0x24,0xfc
30 0x62,0xf2,0x7d,0x48,0x54,0x4c,0x24,0x04
34 0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0x10
38 0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0xe0
42 0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x02,0x00,0x00,0xe0
[all …]
/llvm-project/llvm/test/MC/Disassembler/AArch64/
H A Darmv8.8a-hbc.txt5 [0x30,0x00,0x00,0x54]
8 [0x51,0x00,0x00,0x54]
11 [0x92,0x00,0x00,0x54]
14 [0x13,0x01,0x00,0x54]
17 [0x14,0x02,0x00,0x54]
20 [0x15,0x04,0x00,0x54]
23 [0x16,0x08,0x00,0x54]
26 [0x17,0x10,0x00,0x54]
29 [0x18,0x20,0x00,0x54]
32 [0x19,0x40,0x00,0x54]
[all …]
/llvm-project/llvm/test/MC/Mips/micromips32r6/
H A Dvalid.s4 add $3, $4, $5 # CHECK: add $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x10]
5 addiu $3, $4, 1234 # CHECK: addiu $3, $4, 1234 # encoding: [0x30,0x64,0x04,0xd2]
6 addu $3, $4, $5 # CHECK: addu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x50]
7 addiupc $4, 100 # CHECK: lapc $4, 100 # encoding: [0x78,0x80,0x00,0x19]
8 addiur1sp $7, 4 # CHECK: addiur1sp $7, 4 # encoding: [0x6f,0x83]
10 addiur2 $6, $7, -1 # CHECK: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
12 addiur2 $6, $7, 12 # CHECK: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
14 addius5 $7, -2 # CHECK: addius5 $7, -2 # encoding: [0x4c,0xfc]
16 addiusp -1028 # CHECK: addiusp -1028 # encoding: [0x4f,0xff]
18 addiusp -1032 # CHECK: addiusp -1032 # encoding: [0x4f,0xfd]
[all …]
/llvm-project/llvm/test/MC/AArch64/
H A Darmv8.8a-hbc.s24 // CHECK: bc.eq lbl // encoding: [0bAAA10000,A,A,0x54]
25 // CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pc…
26 // CHECK: bc.ne lbl // encoding: [0bAAA10001,A,A,0x54]
27 // CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pc…
28 // CHECK: bc.hs lbl // encoding: [0bAAA10010,A,A,0x54]
29 // CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pc…
30 // CHECK: bc.hs lbl // encoding: [0bAAA10010,A,A,0x54]
31 // CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pc…
32 // CHECK: bc.lo lbl // encoding: [0bAAA10011,A,A,0x54]
33 // CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pc…
[all …]
H A Dneon-rounding-shift.s17 // CHECK: srshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x54,0x22,0x0e]
18 // CHECK: srshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x54,0x22,0x4e]
19 // CHECK: srshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x54,0x62,0x0e]
20 // CHECK: srshl v0.8h, v1.8h, v2.8h // encoding: [0x20,0x54,0x62,0x4e]
21 // CHECK: srshl v0.2s, v1.2s, v2.2s // encoding: [0x20,0x54,0xa2,0x0e]
22 // CHECK: srshl v0.4s, v1.4s, v2.4s // encoding: [0x20,0x54,0xa2,0x4e]
23 // CHECK: srshl v0.2d, v1.2d, v2.2d // encoding: [0x20,0x54,0xe2,0x4e]
36 // CHECK: urshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x54,0x22,0x2e]
37 // CHECK: urshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x54,0x22,0x6e]
38 // CHECK: urshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x54,0x62,0x2e]
[all …]
H A Darm64-branch-encoding.s10 ; CHECK: encoding: [0xc0,0x03,0x5f,0xd6]
12 ; CHECK: encoding: [0x20,0x00,0x5f,0xd6]
14 ; CHECK: encoding: [0xe0,0x03,0xbf,0xd6]
16 ; CHECK: encoding: [0xe0,0x03,0x9f,0xd6]
18 ; CHECK: encoding: [0xa0,0x00,0x1f,0xd6]
20 ; CHECK: encoding: [0x20,0x01,0x3f,0xd6]
22 ; CHECK: bl L1 ; encoding: [A,A,A,0b100101AA]
23 ; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_call26
30 ; CHECK: b L1 ; encoding: [A,A,A,0b000101AA]
31 ; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch26
[all …]
/llvm-project/llvm/test/MC/LoongArch/lbt/
H A Dx86-shift.s8 # CHECK-ENCODING: encoding: [0x8c,0x94,0x3f,0x00]
12 # CHECK-ENCODING: encoding: [0x8d,0x94,0x3f,0x00]
16 # CHECK-ENCODING: encoding: [0x8e,0x94,0x3f,0x00]
20 # CHECK-ENCODING: encoding: [0x8f,0x94,0x3f,0x00]
24 # CHECK-ENCODING: encoding: [0x98,0x24,0x54,0x00]
28 # CHECK-ENCODING: encoding: [0x99,0x44,0x54,0x00]
32 # CHECK-ENCODING: encoding: [0x9a,0x84,0x54,0x00]
36 # CHECK-ENCODING: encoding: [0x9b,0x04,0x55,0x00]
40 # CHECK-ENCODING: encoding: [0x88,0x94,0x3f,0x00]
44 # CHECK-ENCODING: encoding: [0x89,0x94,0x3f,0x00]
[all …]
/llvm-project/llvm/test/CodeGen/Mips/
H A Dmicromips-mtc-mfc.ll9 ; MM2: # %bb.0: # %entry
10 ; MM2-NEXT: mov.d $f0, $f12 # encoding: [0x54,0x0c,0x20,0x7b]
11 ; MM2-NEXT: mtc1 $zero, $f2 # encoding: [0x54,0x02,0x28,0x3b]
12 ; MM2-NEXT: mthc1 $zero, $f2 # encoding: [0x54,0x02,0x38,0x3b]
13 ; MM2-NEXT: c.ule.d $f12, $f2 # encoding: [0x54,0x4c,0x05,0xfc]
14 ; MM2-NEXT: bc1t $BB0_2 # encoding: [0x43,0xa0,A,A]
15 ; MM2-NEXT: # fixup A - offset: 0, value: ($BB0_2), kind: fixup_MICROMIPS_PC16_S1
16 ; MM2-NEXT: nop # encoding: [0x00,0x00,0x00,0x00]
18 ; MM2-NEXT: j $BB0_2 # encoding: [0b110101AA,A,A,A]
19 ; MM2-NEXT: # fixup A - offset: 0, value: ($BB0_2), kind: fixup_MICROMIPS_26_S1
[all …]
/llvm-project/llvm/test/MC/ARM/
H A Dmve-minmax.s7 # CHECK: vmaxnm.f32 q0, q1, q4 @ encoding: [0x02,0xff,0x58,0x0f]
8 # CHECK-NOFP-NOT: vmaxnm.f32 q0, q1, q4 @ encoding: [0x02,0xff,0x58,0x0f]
9 # ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
12 # CHECK: vminnm.f16 q3, q0, q1 @ encoding: [0x30,0xff,0x52,0x6f]
13 # CHECK-NOFP-NOT: vminnm.f16 q3, q0, q1 @ encoding: [0x30,0xff,0x52,0x6f]
14 # ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
17 # CHECK: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
18 # CHECK-NOFP: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
21 # CHECK: vmin.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
22 # CHECK-NOFP: vmin.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
[all …]
/llvm-project/llvm/test/MC/Disassembler/ARM/
H A Dmve-minmax.txt5 # CHECK: vmaxnm.f32 q0, q1, q4 @ encoding: [0x02,0xff,0x58,0x0f]
7 [0x02,0xff,0x58,0x0f]
9 # CHECK: vminnm.f16 q3, q0, q1 @ encoding: [0x30,0xff,0x52,0x6f]
11 [0x30,0xff,0x52,0x6f]
13 # CHECK: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
15 [0x00,0xef,0x5e,0x66]
17 # CHECK: vmin.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
19 [0x12,0xef,0x54,0x06]
21 # CHECK: vmin.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x54,0x06]
23 [0x22,0xef,0x54,0x06]
[all …]
/llvm-project/llvm/test/MC/AArch64/SVE/
H A Dcondition-codes.s9 // CHECK: b.eq lbl // encoding: [0bAAA00000,A,A,0x54]
10 // CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
15 // CHECK: b.ne lbl // encoding: [0bAAA00001,A,A,0x54]
16 // CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
21 // CHECK: b.hs lbl // encoding: [0bAAA00010,A,A,0x54]
22 // CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
27 // CHECK: b.lo lbl // encoding: [0bAAA00011,A,A,0x54]
28 // CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
33 // CHECK: b.mi lbl // encoding: [0bAAA00100,A,A,0x54]
34 // CHECK-NEXT: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19
[all …]
/llvm-project/llvm/test/MC/Disassembler/Hexagon/
H A Dxtype_shift.txt5 0x10 0xdf 0x14 0x80
7 0x30 0xdf 0x14 0x80
9 0x50 0xdf 0x14 0x80
11 0x11 0xdf 0x15 0x8c
13 0x31 0xdf 0x15 0x8c
15 0x51 0xdf 0x15 0x8c
19 0x10 0xdf 0x14 0x82
21 0x30 0xdf 0x14 0x82
23 0x50 0xdf 0x14 0x82
25 0x90 0xdf 0x14 0x82
[all …]

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