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/freebsd-src/sys/dev/rtwn/rtl8812a/
H A Dr12a_calib.c72 if ((txmode & 0x07) != 0) { in r12a_lc_calib()
84 rtwn_rf_setbits(sc, 0, R12A_RF_LCK, 0, R12A_RF_LCK_MODE); in r12a_lc_calib()
87 chnlbw = rtwn_rf_read(sc, 0, R92C_RF_CHNLBW); in r12a_lc_calib()
88 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, chnlbw | R92C_RF_CHNLBW_LCSTART); in r12a_lc_calib()
94 rtwn_rf_setbits(sc, 0, R12A_RF_LCK, R12A_RF_LCK_MODE, 0); in r12a_lc_calib()
97 if ((txmode & 0x07) != 0) { in r12a_lc_calib()
105 rtwn_write_1(sc, R92C_TXPAUSE, 0); in r12a_lc_calib()
109 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, chnlbw); in r12a_lc_calib()
119 if (sc->fwver == 0x19) in r12a_iq_calib_fw_supported()
122 return (0); in r12a_iq_calib_fw_supported()
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/soc/ti/
H A Dk3-ringacc.txt39 reg = <0x0 0x3c000000 0x0 0x400000>,
40 <0x0 0x38000000 0x0 0x400000>,
41 <0x0 0x31120000 0x0 0x100>,
42 <0x0 0x33000000 0x0 0x40000>;
46 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
H A Dk3-ringacc.yaml84 reg = <0x0 0x3c000000 0x0 0x400000>,
85 <0x0 0x38000000 0x0 0x400000>,
86 <0x0 0x31120000 0x0 0x100>,
87 <0x0 0x33000000 0x0 0x40000>,
88 <0x0 0x31080000 0x0 0x40000>;
91 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
/freebsd-src/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm958522er.dts48 reg = <0x60000000 0x80000000>;
78 nand@0 {
80 reg = <0>;
91 partition@0 {
93 reg = <0x00000000 0x00200000>;
98 reg = <0x00200000 0x00400000>;
102 reg = <0x00600000 0x00a00000>;
106 reg = <0x01000000 0x03000000>;
110 reg = <0x04000000 0x3c000000>;
129 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958525er.dts48 reg = <0x60000000 0x80000000>;
78 nand@0 {
80 reg = <0>;
91 partition@0 {
93 reg = <0x00000000 0x00200000>;
98 reg = <0x00200000 0x00400000>;
102 reg = <0x00600000 0x00a00000>;
106 reg = <0x01000000 0x03000000>;
110 reg = <0x04000000 0x3c000000>;
129 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958525xmc.dts48 reg = <0x60000000 0x40000000>;
78 reg = <0x4c>;
83 reg = <0x52>;
89 reg = <0x68>;
94 nand@0 {
96 reg = <0>;
107 partition@0 {
109 reg = <0x00000000 0x00200000>;
114 reg = <0x00200000 0x00400000>;
118 reg = <0x00600000 0x00a00000>;
[all …]
H A Dbcm958622hr.dts48 reg = <0x60000000 0x80000000>;
82 nand@0 {
84 reg = <0>;
95 partition@0 {
97 reg = <0x00000000 0x00200000>;
102 reg = <0x00200000 0x00400000>;
106 reg = <0x00600000 0x00a00000>;
110 reg = <0x01000000 0x03000000>;
114 reg = <0x04000000 0x3c000000>;
133 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958625hr.dts48 reg = <0x60000000 0x20000000>;
93 nand@0 {
95 reg = <0>;
106 partition@0 {
108 reg = <0x00000000 0x00200000>;
113 reg = <0x00200000 0x00400000>;
117 reg = <0x00600000 0x00a00000>;
121 reg = <0x01000000 0x03000000>;
125 reg = <0x04000000 0x3c000000>;
144 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958623hr.dts48 reg = <0x60000000 0x80000000>;
82 nand@0 {
84 reg = <0>;
95 partition@0 {
97 reg = <0x00000000 0x00200000>;
102 reg = <0x00200000 0x00400000>;
106 reg = <0x00600000 0x00a00000>;
110 reg = <0x01000000 0x03000000>;
114 reg = <0x04000000 0x3c000000>;
133 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm988312hr.dts48 reg = <0x60000000 0x80000000>;
82 nand@0 {
84 reg = <0>;
95 partition@0 {
97 reg = <0x00000000 0x00200000>;
102 reg = <0x00200000 0x00400000>;
106 reg = <0x00600000 0x00a00000>;
110 reg = <0x01000000 0x03000000>;
114 reg = <0x04000000 0x3c000000>;
133 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958625k.dts47 reg = <0x60000000 0x80000000>;
72 nand@0 {
74 reg = <0>;
85 partition@0 {
87 reg = <0x00000000 0x00200000>;
92 reg = <0x00200000 0x00400000>;
96 reg = <0x00600000 0x00a00000>;
100 reg = <0x01000000 0x03000000>;
104 reg = <0x04000000 0x3c000000>;
127 pinctrl-0 = <&nand_sel>, <&gpiobs>, <&pwmc>;
[all …]
/freebsd-src/sys/dev/rtwn/rtl8821a/
H A Dr21a_calib.c66 if (sc->fwver == 0x16) in r21a_iq_calib_fw_supported()
69 return (0); in r21a_iq_calib_fw_supported()
108 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0, 0x80000000); in r21a_iq_calib_sw()
110 rtwn_bb_write(sc, R12A_SLEEP_NAV(0), 0); in r21a_iq_calib_sw()
111 rtwn_bb_write(sc, R12A_PMPD(0), 0); in r21a_iq_calib_sw()
112 rtwn_bb_write(sc, 0xc88, 0); in r21a_iq_calib_sw()
113 rtwn_bb_write(sc, 0xc8c, 0x3c000000); in r21a_iq_calib_sw()
114 rtwn_bb_write(sc, 0xc90, 0x80); in r21a_iq_calib_sw()
115 rtwn_bb_write(sc, 0xc94, 0); in r21a_iq_calib_sw()
116 rtwn_bb_write(sc, 0xcc4, 0x20040000); in r21a_iq_calib_sw()
[all …]
/freebsd-src/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_mips.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
23 PO_ADDIU = 0x24000000, // addiu rt, rs, imm
24 PO_SW = 0xAC000000, // sw rt, offset(sp)
25 PO_LUI = 0x3C000000, // lui rs, %hi(address)
26 PO_ORI = 0x34000000, // ori rt, rs, %lo(address)
27 PO_JALR = 0x0000F809, // jalr rs
28 PO_LW = 0x8C000000, // lw rt, offset(address)
29 PO_B44 = 0x1000000b, // b #44
30 PO_NOP = 0x0, // nop
34 RN_T0 = 0x8,
[all …]
H A Dxray_mips64.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
23 PO_DADDIU = 0x64000000, // daddiu rt, rs, imm
24 PO_SD = 0xFC000000, // sd rt, base(offset)
25 PO_LUI = 0x3C000000, // lui rt, imm
26 PO_ORI = 0x34000000, // ori rt, rs, imm
27 PO_DSLL = 0x00000038, // dsll rd, rt, sa
28 PO_JALR = 0x00000009, // jalr rs
29 PO_LD = 0xDC000000, // ld rt, base(offset)
30 PO_B60 = 0x1000000f, // b #60
31 PO_NOP = 0x0, // nop
[all …]
/freebsd-src/sys/contrib/dev/rtw89/
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x
[all...]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
/freebsd-src/contrib/llvm-project/lld/ELF/Arch/
H A DHexagon.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
56 defaultMaxPageSize = 0x10000; in Hexagon()
71 return ret.value_or(/* Default Arch Rev: */ 0x60); in calcEFlags()
75 uint32_t result = 0;
76 size_t off = 0; in applyMask()
78 for (size_t bit = 0; bit != 32; ++bit) { in applyMask()
170 {0x38000000, 0x0000201f}, {0x39000000, 0x0000201
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8-apalis-v1.1.dtsi17 pinctrl-0 = <&pinctrl_gpio_bkl_on>;
18 brightness-levels = <0 45 63 88 119 158 203 255>;
28 pinctrl-0 = <&pinctrl_gpio8>;
30 gpio-fan,speed-map = < 0 0
82 pinctrl-0 = <&pinctrl_wifi_pdn>;
93 pinctrl-0 = <&pinctrl_gpio7>;
105 pinctrl-0 = <&pinctrl_usbh_en>;
135 reg = <0 0x8400000
[all...]
/freebsd-src/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp5020si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
52 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
67 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
68 pcie@0 {
69 reg = <0 0 0 0 0>;
75 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/arm/
H A Darm-realview-pb1176.dts45 /* 128 MiB memory @ 0x0 */
46 reg = <0x00000000 0x08000000>;
67 #clock-cells = <0>;
73 #clock-cells = <0>;
82 #clock-cells = <0>;
84 clock-frequency = <0>;
89 reg = <0x30000000 0x4000000>;
98 reg = <0x3800000
[all...]
/freebsd-src/sys/arm/broadcom/bcm2835/
H A Dbcm2838_pci.c55 #define PCI_ID_VAL3 0x43c
56 #define CLASS_SHIFT 0x10
57 #define SUBCLASS_SHIFT 0x8
59 #define REG_CONTROLLER_HW_REV 0x406c
60 #define REG_BRIDGE_CTRL 0x9210
61 #define BRIDGE_DISABLE_FLAG 0x1
62 #define BRIDGE_RESET_FLAG 0x2
63 #define REG_PCIE_HARD_DEBUG 0x4204
64 #define REG_DMA_CONFIG 0x4008
65 #define REG_DMA_WINDOW_LOW 0x403
[all...]
/freebsd-src/sys/dev/mpt/mpilib/
H A Dmpi_init.h114 U8 LUN[8]; /* 0Ch */
125 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01)
126 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00)
127 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01)
129 #define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02)
130 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00)
131 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02)
133 #define MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04)
137 #define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
138 #define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
[all …]
/freebsd-src/sys/contrib/openzfs/module/icp/asm-x86_64/aes/
H A Daestab2.h49 0x00000001, 0x00000002, 0x00000004, 0x00000008,
50 0x00000010, 0x00000020, 0x00000040, 0x00000080,
51 0x0000001b, 0x00000036
57 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
58 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
59 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
60 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
61 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
62 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
63 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]
/freebsd-src/sys/dev/vge/
H A Dif_vgereg.h48 #define VIA_VENDORID 0x1106
49 #define VIA_DEVICEID_61XX 0x3119
51 #define VGE_PAR0 0x00 /* physical address register */
52 #define VGE_PAR1 0x02
53 #define VGE_PAR2 0x04
54 #define VGE_RXCTL 0x06 /* RX control register */
55 #define VGE_TXCTL 0x07 /* TX control register */
56 #define VGE_CRS0 0x08 /* Global cmd register 0 (w to set) */
57 #define VGE_CRS1 0x09 /* Global cmd register 1 (w to set) */
58 #define VGE_CRS2 0x0A /* Global cmd register 2 (w to set) */
[all …]

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