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/llvm-project/llvm/test/MC/AArch64/
H A Darm64-system-encoding.s18 ; CHECK: nop ; encoding: [0x1f,0x20,0x03,0xd5]
19 ; CHECK: sev ; encoding: [0x9f,0x20,0x03,0xd5]
20 ; CHECK: sevl ; encoding: [0xbf,0x2
[all...]
H A Darmv8.9a-debug-pmu.s14 mrs x3, MDSELR_EL1
15 // CHECK: mrs x3, MDSELR_EL1 // encoding: [0x43,0x04,0x30,0xd5]
17 // CHECK: msr MDSELR_EL1, x1 // encoding: [0x41,0x04,0x10,0xd5]
20 mrs x3, PMUACR_EL1
21 // CHECK: mrs x3, PMUACR_EL1 // encoding: [0x83,0x9e,0x38,0xd5]
23 // CHECK: msr PMUACR_EL1, x1 // encoding: [0x81,0x9e,0x18,0xd5]
26 mrs x3, PMCCNTSVR_EL1
27 // CHECK: mrs x3, PMCCNTSVR_EL1 // encoding: [0xe3,0xeb,0x30,0xd5]
28 mrs x3, PMICNTSVR_EL1
29 // CHECK: mrs x3, PMICNTSVR_EL1 // encoding: [0x03,0xec,0x30,0xd5]
[all …]
H A Darmv8.4a-tlb.s14 tlbi vale1os, x3
27 //CHECK: tlbi vmalle1os // encoding: [0x1f,0x81,0x08,0xd5]
28 //CHECK-NEXT: tlbi vae1os, xzr // encoding: [0x3f,0x81,0x08,0xd5]
29 //CHECK-NEXT: tlbi vae1os, x0 // encoding: [0x20,0x81,0x08,0xd5]
30 //CHECK-NEXT: tlbi aside1os, x1 // encoding: [0x41,0x81,0x08,0xd5]
31 //CHECK-NEXT: tlbi vaae1os, x2 // encoding: [0x62,0x81,0x08,0xd5]
32 //CHECK-NEXT: tlbi vale1os, x3 // encoding: [0xa3,0x81,0x08,0xd5]
33 //CHECK-NEXT: tlbi vaale1os, x4 // encoding: [0xe4,0x81,0x08,0xd5]
34 //CHECK-NEXT: tlbi ipas2e1os, x5 // encoding: [0x05,0x84,0x0c,0xd5]
35 //CHECK-NEXT: tlbi ipas2le1os, x6 // encoding: [0x86,0x84,0x0c,0xd5]
[all …]
H A Dalias-addsubimm.s23 // CHECK: sub x1, x3, #2, lsl #12
24 // CHECK: sub x1, x3, #2, lsl #12
26 sub x1, x3, #2, lsl 12
27 add x1, x3, #-2, lsl 12
28 // CHECK: sub x1, x3, #4
29 // CHECK: sub x1, x3, #4
31 sub x1, x3, #4
32 add x1, x3, #-4
33 // CHECK: sub x1, x3, #4095
34 // CHECK: sub x1, x3, #4095
[all …]
H A Darm64-logical-encoding.s18 ; CHECK: and w0, w0, #0x1 ; encoding: [0x00,0x00,0x00,0x12]
19 ; CHECK: and x0, x0, #0x1 ; encoding: [0x00,0x00,0x40,0x92]
20 ; CHECK: and w1, w2, #0xf ; encoding: [0x41,0x0c,0x00,0x12]
21 ; CHECK: and x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0x92]
22 ; CHECK: and sp, x5, #0xfffffffffffffff0 ; encoding: [0xbf,0xec,0x7c,0x92]
23 ; CHECK: ands w0, w0, #0x1 ; encoding: [0x00,0x00,0x00,0x72]
24 ; CHECK: ands x0, x0, #0x1 ; encoding: [0x00,0x00,0x40,0xf2]
25 ; CHECK: ands w1, w2, #0xf ; encoding: [0x41,0x0c,0x00,0x72]
26 ; CHECK: ands x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0xf2]
28 eor w1, w2, #0x4000
[all …]
H A Darmv8.9a-prfm-slc.s6 prfm pldslckeep, [x3]
7 // CHECK: prfm pldslckeep, [x3] // encoding: [0x66,0x00,0x80,0xf9]
8 // NO-SLC: prfm #6, [x3]
9 prfm pldslcstrm, [x3]
10 // CHECK: prfm pldslcstrm, [x3] // encoding: [0x67,0x00,0x80,0xf9]
11 // NO-SLC: prfm #7, [x3]
12 prfm plislckeep, [x3]
13 // CHECK: prfm plislckeep, [x3] // encoding: [0x6e,0x00,0x80,0xf9]
14 // NO-SLC: prfm #14, [x3]
15 prfm plislcstrm, [x3]
[all …]
H A Darmv8r-unsupported-sysreg.s5 // CHECK: msr TTBR0_EL2, x3 // encoding: [0x03,0x20,0x1c,0xd5]
6 // CHECK-NEXT: mrs x3, TTBR0_EL2 // encoding: [0x03,0x20,0x3c,0xd5]
7 // CHECK-NEXT: msr VTTBR_EL2, x3 // encoding: [0x03,0x21,0x1c,0xd5]
8 // CHECK-NEXT: mrs x3, VTTBR_EL2 // encoding: [0x03,0x21,0x3c,0xd5]
9 // CHECK-NEXT: msr VSTTBR_EL2, x3 // encoding: [0x03,0x26,0x1c,0xd5]
10 // CHECK-NEXT: mrs x3, VSTTBR_EL2 // encoding: [0x03,0x26,0x3c,0xd5]
12 msr TTBR0_EL2, x3
13 mrs x3, TTBR0_EL2
14 msr VTTBR_EL2, x3
15 mrs x3, VTTBR_EL2
[all …]
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dopt-cmp-rec-postra.mir8 bb.0.entry:
9 successors: %bb.1(0x30000000), %bb.2(0x50000000)
10 liveins: $x3, $x4
11 renamable $x3 = OR8 killed renamable $x3, killed renamable $x4
12 renamable $cr0 = CMPDI renamable $x3, 0, implicit killed $x3
14 ; CHECK: renamable $x3 = OR8_rec killed renamable $x3, killed renamable $x4, implicit-def $cr0
19 $x3 = LI8 102
20 BLR8 implicit $lr8, implicit $rm, implicit $x3
23 $x3 = LI8 116
24 BLR8 implicit $lr8, implicit $rm, implicit $x3
[all …]
H A Daix-prefixed-instruction-boundary.mir10 - { reg: '$x3', virtual-reg: '' }
12 bb.0.entry:
13 liveins: $x3
14 renamable $x3 = LI8 2
15 renamable $x3 = PADDI8 $x3, 13
16 renamable $x3 = PADDI8 $x3, 13
17 renamable $x3 = PADDI8 $x3, 13
18 renamable $x3 = PADDI8 $x3, 13
19 renamable $x3 = PADDI8 $x3, 13
20 renamable $x3 = PADDI8 $x3, 13
[all …]
H A Dremove-redundant-load-imm.mir10 bb.0.entry:
15 ; CHECK: renamable $x3 = LI8 0
16 ; CHECK: STD renamable $x3, 16, $x1
17 ; CHECK: STD killed renamable $x3, 8, $x1
19 renamable $x3 = LI8 0
20 STD killed renamable $x3, 16, $x1
21 renamable $x3 = LI8 0
22 STD killed renamable $x3, 8, $x1
32 bb.0.entry:
37 ; CHECK: renamable $x3 = LI8 0
[all …]
H A Dmachine-backward-cp.mir12 bb.0.entry:
14 ; CHECK: $x3 = LI8 1024
15 ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
17 $x3 = COPY renamable killed $x4
18 BLR8 implicit $lr8, implicit undef $rm, implicit $x3
29 ; CHECK: bb.0.entry:
34 ; CHECK: $x3 = COPY killed renamable $x4
35 ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
36 bb.0.entry:
45 $x3 = COPY renamable killed $x4
[all …]
H A Dfold-rot-and-peephole.mir9 bb.0.entry:
10 liveins: $x3
12 ; CHECK: liveins: $x3
14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
15 ; CHECK-NEXT: dead [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[COPY]], 0, 32
16 ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec killed [[COPY]], 1, implicit-def dead $cr0
17 ; CHECK-NEXT: $x3 = COPY killed [[ANDI8_rec]]
18 ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
19 %1:g8rc = COPY $x3
20 %2:g8rc = RLDICL %1:g8rc, 0, 32
[all …]
H A Dconvert-rr-to-ri-instrs-kill-flag.mir9 bb.0.entry:
10 liveins: $x3, $f1, $x5
11 $x3 = LI8 100
12 STFSX killed $f1, $x3, $x5
14 STD killed $x3, killed $x5, 100
15 ; CHECK: STD killed $x3, killed $x5, 100
20 # LI + XFORM -> DFORM, fixup killed/dead flag for $x3, find no use, set def as
26 bb.0.entry:
27 liveins: $x3, $f1, $x5
28 $x3 = LI8 100
[all …]
H A Dfold-frame-offset-using-rr.mir18 bb.0.entry:
19 liveins: $x3, $x1, $x4, $x6
20 $x3 = ADDI8 $x1, -80
21 ; CHECK: $x3 = ADDI8 $x1, -76
22 $x4 = ADD8 killed $x3, killed $x4
25 ; CHECK: $x6 = LDX killed $x4, killed $x3
34 bb.0.entry:
35 liveins: $x3, $x1, $x4, $x6
36 $x3 = ADDI8 $x1, -80
37 ; CHECK: $x3 = ADDI8 $x1, -76
[all …]
H A Dmacro-fusion.mir7 # CHECK: add_mulld:%bb.0
8 # CHECK: Macro fuse: SU(0) - SU(1) / MULLD - ADD8
13 bb.0.entry:
14 liveins: $x3, $x4, $x5
15 renamable $x4 = MULLD $x3, $x4
16 renamable $x3 = ADD8 killed renamable $x4, $x5
17 BLR8 implicit $lr8, implicit $rm, implicit $x3
20 # CHECK: add_and:%bb.0
21 # CHECK: Macro fuse: SU(0) - SU(1) / ADD8 - AND8
26 bb.0.entry:
[all …]
/llvm-project/llvm/test/MC/Disassembler/AArch64/
H A Darmv8.9a-debug-pmu.txt13 [0x83,0x00,0x30,0xd5]
14 # CHECK: mrs x3, DBGBVR0_EL1
15 [0x81,0x00,0x10,0xd5]
17 [0x83,0x01,0x30,0xd5]
18 # CHECK: mrs x3, DBGBVR1_EL1
19 [0x81,0x01,0x10,0xd5]
21 [0x83,0x02,0x30,0xd5]
22 # CHECK: mrs x3, DBGBVR2_EL1
23 [0x81,0x02,0x10,0xd5]
25 [0x83,0x03,0x30,0xd5]
[all …]
H A Darmv8.4a-tlb.txt7 0x1f,0x81,0x08,0xd5
8 0x20,0x81,0x08,0xd5
9 0x40,0x81,0x08,0xd5
10 0x60,0x81,0x08,0xd5
11 0xa0,0x81,0x08,0xd5
12 0xe0,0x81,0x08,0xd5
13 0x00,0x84,0x0c,0xd5
14 0x80,0x84,0x0c,0xd5
15 0x20,0x81,0x0c,0xd5
16 0xa0,0x81,0x0c,0xd5
[all …]
H A Darm64-logical.txt7 0x00 0x00 0x00 0x12
8 0x00 0x00 0x40 0x92
9 0x41 0x0c 0x00 0x12
10 0x41 0x0c 0x40 0x92
11 0xbf 0xec 0x7c 0x92
12 0x00 0x00 0x00 0x72
13 0x00 0x00 0x40 0xf2
14 0x41 0x0c 0x00 0x72
15 0x41 0x0c 0x40 0xf2
16 0x5f 0x0c 0x40 0xf2
[all …]
H A Darmv8.6a-fgt.txt4 [0x80,0x11,0x1c,0xd5]
5 [0xa0,0x11,0x1c,0xd5]
6 [0xc0,0x11,0x1c,0xd5]
7 [0x80,0x31,0x1c,0xd5]
8 [0xa0,0x31,0x1c,0xd5]
9 [0xc0,0x31,0x1c,0xd5]
24 [0x80,0x11,0x3c,0xd5]
25 [0xa0,0x11,0x3c,0xd5]
26 [0xc0,0x11,0x3c,0xd5]
27 [0x80,0x31,0x3c,0xd5]
[all …]
/llvm-project/llvm/test/MC/AArch64/SME/
H A Dsystem-regs.s13 mrs x3, ID_AA64SMFR0_EL1
14 // CHECK-INST: mrs x3, ID_AA64SMFR0_EL1
15 // CHECK-ENCODING: [0xa3,0x04,0x38,0xd5]
17 // CHECK-UNKNOWN: d53804a3 mrs x3, S3_0_C0_C4_5
19 mrs x3, SMCR_EL1
20 // CHECK-INST: mrs x3, SMCR_EL1
21 // CHECK-ENCODING: [0xc3,0x12,0x38,0xd5]
23 // CHECK-UNKNOWN: d53812c3 mrs x3, S3_0_C1_C2_6
25 mrs x3, SMCR_EL2
26 // CHECK-INST: mrs x3, SMCR_EL2
[all …]
/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/
H A DA55-store-readadv.s6 add x2, x3, #1
8 add x2, x3, #1
10 add x2, x3, #1
12 add x2, x3, #1
14 add x2, x3, #1
16 add x2, x3, #1
18 add x2, x3, #1
20 add x2, x3, #1
22 add x2, x3, #1
24 add x2, x3, #1
[all …]
H A DA55-load-readadv.s6 add x2, x3, #1
8 add x2, x3, #1
10 add x2, x3, #1
12 add x2, x3, #1
14 add x2, x3, #1
16 add x2, x3, #1
18 add x2, x3, #1
20 add x2, x3, #1
22 add x2, x3, #1
24 add x2, x3, #1
[all …]
/llvm-project/llvm/test/MC/AArch64/SVE/
H A Dsystem-regs.s10 mrs x3, ID_AA64ZFR0_EL1
11 // CHECK-INST: mrs x3, ID_AA64ZFR0_EL1
12 // CHECK-ENCODING: [0x83,0x04,0x38,0xd5]
14 // CHECK-UNKNOWN: d5380483 mrs x3, S3_0_C0_C4_4
16 mrs x3, ZCR_EL1
17 // CHECK-INST: mrs x3, ZCR_EL1
18 // CHECK-ENCODING: [0x03,0x12,0x38,0xd5]
20 // CHECK-UNKNOWN: d5381203 mrs x3, S3_0_C1_C2_0
22 mrs x3, ZCR_EL2
23 // CHECK-INST: mrs x3, ZCR_EL2
[all …]
/llvm-project/llvm/test/Analysis/ValueTracking/
H A Dknownbits-bmi-pattern.ll12 %x3 = xor i32 %x1, %x2
13 %z = icmp eq i32 %x3, 8
23 %x3 = xor <2 x i32> %x2, %x1
24 %z = icmp ne <2 x i32> %x3, <i32 8, i32 8>
34 %x3 = xor <2 x i32> %x2, %x1
35 %z = icmp ne <2 x i32> %x3, <i32 8, i32 8>
45 %x3 = xor i32 %x1, %x2
46 %z = icmp uge i32 %x3, 8
56 %x3 = xor <2 x i32> %x2, %x1
57 %z = icmp ugt <2 x i32> %x3, <i3
[all...]
/llvm-project/llvm/test/MC/AMDGPU/
H A Dgfx11_asm_mimg.s3 image_atomic_add v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
4 // GFX11: [0x80,0x03,0x30,0xf0,0x02,0x01,0x03,0x00]
6 image_atomic_add v[1:2], v255, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
7 // GFX11: [0x80,0x03,0x30,0xf0,0xff,0x01,0x03,0x00]
9 image_atomic_add v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm a16
10 // GFX11: [0x80,0x03,0x31,0xf0,0x02,0x01,0x03,0x00]
12 image_atomic_add v[1:2], v255, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm a16
13 // GFX11: [0x80,0x03,0x31,0xf0,0xff,0x01,0x03,0x00]
15 image_atomic_add v[1:2], v[2:4], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm
16 // GFX11: [0x88,0x03,0x30,0xf0,0x02,0x01,0x03,0x00]
[all …]

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