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/llvm-project/llvm/test/CodeGen/AArch64/
H A Djump-table-compress.mir26 stackSize: 0
27 offsetAdjustment: 0
28 maxAlignment: 0
31 maxCallFrameSize: 0
38 - id: 0
51 bb.0 (%ir-block.0):
54 bb.1 (%ir-block.0):
59 …r $x10, dead early-clobber $x11 = JumpTableDest32 undef killed $x9, undef killed $x8, %jump-table.0
126 maxCallFrameSize: 0
132 - id: 0
[all …]
H A Dmachine-outliner-2fixup-blr-terminator.mir7 define void @f1() #0 { ret void }
8 define void @f2() #0 { ret void }
9 define void @f3() #0 { ret void }
10 define void @f4() #0 { ret void }
11 attributes #0 = { minsize noredzone "branch-target-enforcement" }
17 bb.0:
18 liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
19 $x20, $x19 = LDPXi $sp, 11
20 $x20,
[all...]
H A Dmachine-outliner-all-stack.mir12 define void @reg-save-possible() #0 { ret void }
13 define void @stack-save1() #0 { ret void }
14 define void @stack-save2() #0 { ret void }
15 define void @stack-save3() #0 { ret void }
16 attributes #0 = { minsize noinline noredzone "frame-pointer"="all" }
23 bb.0:
27 $x20 = ORRXri $xzr, 1
32 ; CHECK-NEXT: BL [[FN:@OUTLINED_FUNCTION_[0-9]+]]
34 $x20, $x19 = LDPXi $sp, 10
35 $x20, $x19 = LDPXi $sp, 10
[all …]
/llvm-project/llvm/test/MC/Disassembler/AArch64/
H A Darmv8.1a-rdma.txt3 [0x20,0x84,0x02,0x2e] # sqrdmlah v0.8b, v1.8b, v2.8b
4 [0x20,0x8c,0x02,0x2e] # sqrdmlsh v0.8b, v1.8b, v2.8b
5 [0x20,0x84,0xc2,0x2e] # sqrdmlah v0.1d, v1.1d, v2.1d
6 [0x20,0x8c,0xc2,0x2e] # sqrdmlsh v0.1d, v1.1d, v2.1d
7 [0x20,0x84,0x02,0x6e] # sqrdmlah v0.16b, v1.16b, v2.16b
8 [0x20,0x8c,0x02,0x6e] # sqrdmlsh v0.16b, v1.16b, v2.16b
9 [0x20,0x84,0xc2,0x6e] # sqrdmlah v0.2d, v1.2d, v2.2d
10 [0x20,0x8c,0xc2,0x6e] # sqrdmlsh v0.2d, v1.2d, v2.2d
12 # CHECK: [0x20,0x84,0x02,0x2e]
14 # CHECK: [0x20,0x8c,0x02,0x2e]
[all …]
H A Darmv8a-fpmul-err.txt8 [0x20,0xec,0x22,0x0e]
9 [0x20,0xec,0xa2,0x0e]
10 [0x20,0xec,0x22,0x4e]
11 [0x20,0xec,0xa2,0x4e]
12 [0x20,0xcc,0x22,0x2e]
13 [0x20,0xcc,0xa2,0x2e]
14 [0x20,0xcc,0x22,0x6e]
15 [0x20,0xcc,0xa2,0x6e]
19 [0x20,0x08,0xb2,0x0f]
20 [0x20,0x48,0xb2,0x0f]
[all …]
H A Darmv8a-fpmul.txt5 [0x41,0x08,0xe3,0x1e]
7 [0x20,0xec,0x22,0x0e]
8 [0x20,0xec,0xa2,0x0e]
9 [0x20,0xec,0x22,0x4e]
10 [0x20,0xec,0xa2,0x4e]
11 [0x20,0xcc,0x22,0x2e]
12 [0x20,0xcc,0xa2,0x2e]
13 [0x20,0xcc,0x22,0x6e]
14 [0x20,0xcc,0xa2,0x6e]
18 [0x20,0x08,0xb2,0x0f]
[all …]
H A Darmv9-sysp.txt6 0x00 0x20 0x48 0xd5
7 0x20 0x20 0x48 0xd5
8 0x00 0x74 0x48 0xd5
9 0x60 0xd0 0x48 0xd5
10 0xc0 0xd0 0x48 0xd5
11 0x00 0x20 0x4c 0xd5
12 0x20 0x20 0x4c 0xd5
13 0x00 0x21 0x4c 0xd5
14 0x00 0x20 0x48 0xd5
15 0x20 0x20 0x48 0xd5
[all …]
H A Darmv8.3a-signed-pointer.txt6 # CHECK-NEXT: [0x00,0x0c,0x20,0xf8]
8 # CHECK-NEXT: [0x00,0x0c,0xa0,0xf8]
9 # CHECK: ldraa x0, [x0, #0]!
10 # CHECK: ldrab x0, [x0, #0]!
11 [0x00,0x0c,0x20,0xf8]
12 [0x00,0x0c,0xa0,0xf8]
27 [0x3f,0x23,0x03,0xd5]
28 [0xbf,0x23,0x03,0xd5]
29 [0x1f,0x23,0x03,0xd5]
30 [0x9f,0x23,0x03,0xd5]
[all …]
H A Darmv9-sysreg128.txt6 0x00,0x20,0x78,0xd5
7 0x20,0x20,0x78,0xd5
8 0x00,0x74,0x78,0xd5
9 0x60,0xd0,0x78,0xd5
10 0xc0,0xd0,0x78,0xd5
11 0x00,0x20,0x7c,0xd5
12 0x20,0x20,0x7c,0xd5
13 0x00,0x21,0x7c,0xd5
14 0x00,0x21,0x7c,0xd5
15 0x02,0x21,0x7c,0xd5
[all …]
/llvm-project/llvm/test/MC/Disassembler/PowerPC/
H A Dppc64-encoding-ext.txt6 # FIXME: decode as beqlr 0
8 0x4d 0x82 0x00 0x20
12 0x4d 0x86 0x00 0x20
16 0x4d 0x8a 0x00 0x20
20 0x4d 0x8e 0x00 0x20
24 0x4d 0x92 0x00 0x20
28 0x4d 0x96 0x00 0x20
32 0x4d 0x9a 0x00 0x20
36 0x4d 0x9e 0x00 0x20
38 # CHECK: bclr 12, 0
[all …]
/llvm-project/llvm/test/MC/ARM/
H A Darm-arithmetic-aliases.s11 @ CHECK: sub r2, r2, #6 @ encoding: [0x06,0x20,0x42,0xe2]
12 @ CHECK: sub r2, r2, #6 @ encoding: [0x06,0x20,0x42,0xe2]
13 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
14 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
21 @ CHECK: add r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe2]
22 @ CHECK: add r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe2]
23 @ CHECK: add r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe0]
24 @ CHECK: add r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe0]
31 @ CHECK: and r2, r2, #6 @ encoding: [0x06,0x20,0x02,0xe2]
32 @ CHECK: and r2, r2, #6 @ encoding: [0x06,0x20,0x02,0xe2]
[all …]
/llvm-project/llvm/test/MC/AArch64/
H A Dneon-3vdiff.s21 // CHECK: saddl v0.8h, v1.8b, v2.8b // encoding: [0x20,0x00,0x22,0x0e]
22 // CHECK: saddl v0.4s, v1.4h, v2.4h // encoding: [0x20,0x00,0x62,0x0e]
23 // CHECK: saddl v0.2d, v1.2s, v2.2s // encoding: [0x20,0x00,0xa2,0x0e]
29 // CHECK: saddl2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0x00,0x62,0x4e]
30 // CHECK: saddl2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0x00,0x22,0x4e]
31 // CHECK: saddl2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0x00,0xa2,0x4e]
37 // CHECK: uaddl v0.8h, v1.8b, v2.8b // encoding: [0x20,0x00,0x22,0x2e]
38 // CHECK: uaddl v0.4s, v1.4h, v2.4h // encoding: [0x20,0x00,0x62,0x2e]
39 // CHECK: uaddl v0.2d, v1.2s, v2.2s // encoding: [0x20,0x00,0xa2,0x2e]
45 // CHECK: uaddl2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0x00,0x22,0x6e]
[all …]
H A Dneon-across.s15 // CHECK: saddlv h0, v1.8b // encoding: [0x20,0x38,0x30,0x0e]
16 // CHECK: saddlv h0, v1.16b // encoding: [0x20,0x38,0x30,0x4e]
17 // CHECK: saddlv s0, v1.4h // encoding: [0x20,0x38,0x70,0x0e]
18 // CHECK: saddlv s0, v1.8h // encoding: [0x20,0x38,0x70,0x4e]
19 // CHECK: saddlv d0, v1.4s // encoding: [0x20,0x38,0xb0,0x4e]
27 // CHECK: uaddlv h0, v1.8b // encoding: [0x20,0x38,0x30,0x2e]
28 // CHECK: uaddlv h0, v1.16b // encoding: [0x20,0x38,0x30,0x6e]
29 // CHECK: uaddlv s0, v1.4h // encoding: [0x20,0x38,0x70,0x2e]
30 // CHECK: uaddlv s0, v1.8h // encoding: [0x20,0x38,0x70,0x6e]
31 // CHECK: uaddlv d0, v1.4s // encoding: [0x20,0x38,0xb0,0x6e]
[all …]
H A Dneon-2velem.s14 // CHECK: mla v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x08,0x82,0x2f]
15 // CHECK: mla v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x08,0x96,0x2f]
16 // CHECK: mla v3.4s, v8.4s, v2.s[1] // encoding: [0x03,0x01,0xa2,0x6f]
17 // CHECK: mla v3.4s, v8.4s, v22.s[3] // encoding: [0x03,0x09,0xb6,0x6f]
24 // CHECK: mla v0.4h, v1.4h, v2.h[2] // encoding: [0x20,0x00,0x62,0x2f]
25 // CHECK: mla v0.4h, v1.4h, v15.h[2] // encoding: [0x20,0x00,0x6f,0x2f]
26 // CHECK: mla v0.8h, v1.8h, v2.h[7] // encoding: [0x20,0x08,0x72,0x6f]
27 // CHECK: mla v0.8h, v1.8h, v14.h[6] // encoding: [0x20,0x08,0x6e,0x6f]
34 // CHECK: mls v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x48,0x82,0x2f]
35 // CHECK: mls v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x48,0x96,0x2f]
[all …]
H A Dneon-simd-shift.s15 // CHECK: sshr v0.8b, v1.8b, #3 // encoding: [0x20,0x04,0x0d,0x0f]
16 // CHECK: sshr v0.4h, v1.4h, #3 // encoding: [0x20,0x04,0x1d,0x0f]
17 // CHECK: sshr v0.2s, v1.2s, #3 // encoding: [0x20,0x04,0x3d,0x0f]
18 // CHECK: sshr v0.16b, v1.16b, #3 // encoding: [0x20,0x04,0x0d,0x4f]
19 // CHECK: sshr v0.8h, v1.8h, #3 // encoding: [0x20,0x04,0x1d,0x4f]
20 // CHECK: sshr v0.4s, v1.4s, #3 // encoding: [0x20,0x04,0x3d,0x4f]
21 // CHECK: sshr v0.2d, v1.2d, #3 // encoding: [0x20,0x04,0x7d,0x4f]
34 // CHECK: ushr v0.8b, v1.8b, #3 // encoding: [0x20,0x04,0x0d,0x2f]
35 // CHECK: ushr v0.4h, v1.4h, #3 // encoding: [0x20,0x04,0x1d,0x2f]
36 // CHECK: ushr v0.2s, v1.2s, #3 // encoding: [0x20,0x04,0x3d,0x2f]
[all …]
H A Dneon-perm.s17 // CHECK: uzp1 v0.8b, v1.8b, v2.8b // encoding: [0x20,0x18,0x02,0x0e]
18 // CHECK: uzp1 v0.16b, v1.16b, v2.16b // encoding: [0x20,0x18,0x02,0x4e]
19 // CHECK: uzp1 v0.4h, v1.4h, v2.4h // encoding: [0x20,0x18,0x42,0x0e]
20 // CHECK: uzp1 v0.8h, v1.8h, v2.8h // encoding: [0x20,0x18,0x42,0x4e]
21 // CHECK: uzp1 v0.2s, v1.2s, v2.2s // encoding: [0x20,0x18,0x82,0x0e]
22 // CHECK: uzp1 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x18,0x82,0x4e]
23 // CHECK: uzp1 v0.2d, v1.2d, v2.2d // encoding: [0x20,0x18,0xc2,0x4e]
33 // CHECK: trn1 v0.8b, v1.8b, v2.8b // encoding: [0x20,0x28,0x02,0x0e]
34 // CHECK: trn1 v0.16b, v1.16b, v2.16b // encoding: [0x20,0x28,0x02,0x4e]
35 // CHECK: trn1 v0.4h, v1.4h, v2.4h // encoding: [0x20,0x28,0x42,0x0e]
[all …]
/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx12_dasm_vsample.txt3 # GFX12: image_sample v64, v32, s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0x46,0xe4,0x40,0x08,0x00,0x32,0x2
[all...]
H A Dgfx11_dasm_mimg_features.txt3 # GFX11: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x80,0x0f,0x00,0xf0,0x00,0x00,0x0
[all...]
/llvm-project/llvm/test/MC/Disassembler/Sparc/
H A Dsparc-mem.txt4 0xd4 0x4e 0x00 0x16
7 0xd4 0x4e 0x20 0x20
10 0xd8 0x48 0x60 0x00
13 0xd8 0x48 0x40 0x00
16 0xd4 0xce 0x10 0x76
19 0xd4 0x56 0x00 0x16
22 0xd4 0x56 0x20 0x20
25 0xd8 0x50 0x60 0x00
28 0xd8 0x50 0x40 0x00
31 0xd4 0xd6 0x10 0x76
[all …]
/llvm-project/llvm/test/MC/Mips/
H A Drotations64.s10 # CHECK-64: subu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x23]
11 # CHECK-64: srlv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x06]
12 # CHECK-64: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
13 # CHECK-64: or $4, $4, $1 # encoding: [0x00,0x81,0x20,0x25]
14 # CHECK-64R: subu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x23]
15 # CHECK-64R: rotrv $4, $4, $1 # encoding: [0x00,0x24,0x20,0x46]
17 # CHECK-64: subu $1, $zero, $6 # encoding: [0x00,0x06,0x08,0x23]
18 # CHECK-64: srlv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x06]
19 # CHECK-64: sllv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x04]
20 # CHECK-64: or $4, $4, $1 # encoding: [0x00,0x81,0x20,0x25]
[all …]
H A Drotations32.s10 # CHECK-32: negu $1, $5 # encoding: [0x00,0x05,0x08,0x23]
11 # CHECK-32: srlv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x06]
12 # CHECK-32: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
13 # CHECK-32: or $4, $4, $1 # encoding: [0x00,0x81,0x20,0x25]
14 # CHECK-32R: negu $1, $5 # encoding: [0x00,0x05,0x08,0x23]
15 # CHECK-32R: rotrv $4, $4, $1 # encoding: [0x00,0x24,0x20,0x46]
17 # CHECK-32: negu $1, $6 # encoding: [0x00,0x06,0x08,0x23]
18 # CHECK-32: srlv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x06]
19 # CHECK-32: sllv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x04]
20 # CHECK-32: or $4, $4, $1 # encoding: [0x00,0x81,0x20,0x25]
[all …]
H A Dmips64-instalias-imm-expanding.s6 add $4, -0x80000000
7 # CHECK-NEXT: lui $1, 0x8000 # encoding: [0x00,0x80,0x01,0x3c]
8 # CHECK-NEXT: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00]
9 add $4, -0x8001
10 # CHECK-NEXT: lui $1, 0xffff # encoding: [0xff,0xff,0x01,0x3c]
11 # CHECK-NEXT: ori $1, $1, 0x7fff # encoding: [0xff,0x7f,0x21,0x34]
12 # CHECK-NEXT: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00]
13 add $4, -0x8000
14 # CHECK-NEXT: addi $4, $4, -0x8000 # encoding: [0x00,0x80,0x84,0x20]
15 add $4, 0
[all …]
/llvm-project/llvm/test/MC/Disassembler/ARC/
H A Dalu.txt4 0x00 0x20 0x00 0x00
7 0x00 0x20 0x04 0x00
10 0x00 0x20 0x04 0x80
13 0x00 0x20 0xc2 0x00
16 0x00 0x20 0x02 0x01
19 0x00 0x27 0x02 0x01
22 0xc0 0x20 0x61 0x00
25 0xc0 0x26 0x2b 0x04
28 0xc0 0x27 0xec 0x17
31 0xc0 0x20 0x69 0x00
[all …]
/llvm-project/llvm/test/MC/Disassembler/ARM/
H A Dmove-banked-regs-thumb.txt3 [0xe0,0xf3,0x20,0x82]
4 [0xe1,0xf3,0x20,0x83]
5 [0xe2,0xf3,0x20,0x85]
6 [0xe3,0xf3,0x20,0x87]
7 [0xe4,0xf3,0x20,0x8b]
8 [0xe5,0xf3,0x20,0x81]
9 [0xe6,0xf3,0x20,0x82]
18 [0xe8,0xf3,0x20,0x82]
19 [0xe9,0xf3,0x20,0x83]
20 [0xea,0xf3,0x20,0x85]
[all …]
/llvm-project/llvm/test/MC/AMDGPU/
H A Dgfx12_asm_vsample.s3 image_sample v64, v32, s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_1D
4 // GFX12: encoding: [0x00,0xc0,0x46,0xe4,0x40,0x08,0x00,0x32,0x20,0x00,0x00,0x00]
6 image_sample v64, [v32, v33], s[4:11], s[100:103] dmask:0x8 dim:SQ_RSRC_IMG_2D
7 // GFX12: encoding: [0x01,0xc0,0x06,0xe6,0x40,0x08,0x00,0x32,0x20,0x21,0x00,0x00]
9 image_sample v[64:65], [v32, v33, v34], s[4:11], s[100:103] dmask:0x3 dim:SQ_RSRC_IMG_3D
10 // GFX12: encoding: [0x02,0xc0,0xc6,0xe4,0x40,0x08,0x00,0x32,0x20,0x21,0x22,0x00]
12 image_sample v[64:65], [v32, v33, v34], s[4:11], s[100:103] dmask:0xc dim:SQ_RSRC_IMG_CUBE
13 // GFX12: encoding: [0x03,0xc0,0x06,0xe7,0x40,0x08,0x00,0x32,0x20,0x21,0x22,0x00]
15 image_sample v[64:66], [v32, v33], s[4:11], s[100:103] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY
16 // GFX12: encoding: [0x04,0xc0,0xc6,0xe6,0x40,0x08,0x00,0x32,0x20,0x21,0x00,0x00]
[all …]

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