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/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/
H A DA55-store-readadv.s6 add x2, x3, #1
7 str b0, [x2, #16]
8 add x2, x3, #1
9 str b0, [x2, #16]!
10 add x2, x3, #1
11 str b0, [x2], #16
12 add x2, x3, #1
13 str d0, [x2], #16
14 add x2, x3, #1
15 str d0, [x2, #16]!
[all …]
H A DA55-load-readadv.s6 add x2, x3, #1
7 ldr b0, [x2, #16]
8 add x2, x3, #1
9 ldr b0, [x2, #16]!
10 add x2, x3, #1
11 ldr b0, [x2], #16
12 add x2, x3, #1
13 ldr d0, [x2], #16
14 add x2, x3, #1
15 ldr d0, [x2, #16]!
[all …]
/llvm-project/llvm/test/MC/AArch64/
H A Darmv8.1a-atomic.s6 casb w0, w1, [x2]
7 casab w0, w1, [x2]
8 caslb w0, w1, [x2]
9 casalb w0, w1, [x2]
11 //CHECK: casb w0, w1, [x2] // encoding: [0x41,0x7c,0xa0,0x08]
12 //CHECK: casab w0, w1, [x2] // encoding: [0x41,0x7c,0xe0,0x08]
13 //CHECK: caslb w0, w1, [x2] // encoding: [0x41,0xfc,0xa0,0x08]
14 //CHECK: casalb w0, w1, [x2] // encoding: [0x41,0xfc,0xe0,0x08]
17 casalb x0, x1, [x2]
22 //CHECK-ERROR: casalb x0, x1, [x2]
[all …]
H A Darmv8.1a-lse.s13 cas w0, w1, [x2]
15 casa w0, w1, [x2]
17 casl w0, w1, [x2]
19 casal w0, w1, [x2]
21 // CHECK: cas w0, w1, [x2] // encoding: [0x41,0x7c,0xa0,0x88]
22 // CHECK: cas w2, w3, [sp] // encoding: [0xe3,0x7f,0xa2,0x88]
23 // CHECK: casa w0, w1, [x2] // encoding: [0x41,0x7c,0xe0,0x88]
24 // CHECK: casa w2, w3, [sp] // encoding: [0xe3,0x7f,0xe2,0x88]
25 // CHECK: casl w0, w1, [x2] // encoding: [0x41,0xfc,0xa0,0x88]
26 // CHECK: casl w2, w3, [sp] // encoding: [0xe3,0xff,0xa2,0x88]
[all …]
H A Darmv8.8a-mops.s12 // CHECK: [0x40,0x04,0x01,0x19]
13 // CHECK-NEXT: [0x40,0x44,0x01,0x19]
14 // CHECK-NEXT: [0x40,0x84,0x01,0x19]
15 // CHECK-NEXT: [0x40,0xc4,0x01,0x19]
16 // CHECK-NEXT: [0x40,0x14,0x01,0x19]
17 // CHECK-NEXT: [0x40,0x54,0x01,0x19]
18 // CHECK-NEXT: [0x40,0x94,0x01,0x19]
19 // CHECK-NEXT: [0x40,0xd4,0x01,0x19]
20 // CHECK-NEXT: [0x40,0x24,0x01,0x19]
21 // CHECK-NEXT: [0x40,0x64,0x01,0x19]
[all …]
H A Darm64-logical-encoding.s11 and x1, x2, #15
16 ands x1, x2, #15
18 ; CHECK: and w0, w0, #0x1 ; encoding: [0x00,0x00,0x00,0x12]
19 ; CHECK: and x0, x0, #0x1 ; encoding: [0x00,0x00,0x40,0x92]
20 ; CHECK: and w1, w2, #0xf ; encoding: [0x41,0x0c,0x00,0x12]
21 ; CHECK: and x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0x92]
22 ; CHECK: and sp, x5, #0xfffffffffffffff0 ; encoding: [0xbf,0xec,0x7c,0x92]
23 ; CHECK: ands w0, w0, #0x1 ; encoding: [0x00,0x00,0x00,0x72]
24 ; CHECK: ands x0, x0, #0x1 ; encoding: [0x00,0x00,0x40,0xf2]
25 ; CHECK: ands w1, w2, #0xf ; encoding: [0x41,0x0c,0x00,0x72]
[all …]
H A Darmv9.5a-cpa.s4 addpt x0, x1, x2
5 // CHECK: addpt x0, x1, x2 // encoding: [0x20,0x20,0x02,0x9a]
8 addpt sp, sp, x2
9 // CHECK: addpt sp, sp, x2 // encoding: [0xff,0x23,0x02,0x9a]
12 addpt x0, x1, x2, lsl #0
13 // CHECK: addpt x0, x1, x2 // encoding: [0x20,0x20,0x02,0x9a]
16 addpt x0, x1, x2, lsl #7
17 // CHECK: addpt x0, x1, x2, lsl #7 // encoding: [0x20,0x3c,0x02,0x9a]
20 addpt sp, sp, x2, lsl #7
21 // CHECK: addpt sp, sp, x2, lsl #7 // encoding: [0xff,0x3f,0x02,0x9a]
[all …]
H A Darmv8.5a-mte.s8 irg x0, x1, x2
9 irg sp, x1, x2
11 // CHECK: irg x0, x1 // encoding: [0x20,0x10,0xdf,0x9a]
12 // CHECK: irg sp, x1 // encoding: [0x3f,0x10,0xdf,0x9a]
13 // CHECK: irg x0, sp // encoding: [0xe0,0x13,0xdf,0x9a]
14 // CHECK: irg x0, x1, x2 // encoding: [0x20,0x10,0xc2,0x9a]
15 // CHECK: irg sp, x1, x2 // encoding: [0x3f,0x10,0xc2,0x9a]
24 // NOMTE-NEXT: irg x0, x1, x2
26 // NOMTE-NEXT: irg sp, x1, x2
28 addg x0, x1, #0, #1
[all …]
/llvm-project/llvm/test/CodeGen/RISCV/
H A Dstack-inst-compress.mir39 - { id: 0, size: 2048, alignment: 4, local-offset: -2048 }
41 varArgsFrameIndex: 0
42 varArgsSaveSize: 0
44 bb.0.entry:
48 ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-setup ADDI $x2, -2032
50 ; CHECK-RV32-NO-COM-NEXT: frame-setup SW killed $x1, $x2, 2028 :: (store (s32) into %stack.1)
52 ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-setup ADDI $x2, -32
54 ; CHECK-RV32-NO-COM-NEXT: renamable $x10 = ADDI $x2, 1
[all...]
/llvm-project/llvm/test/MC/Disassembler/AArch64/
H A Darmv8.1a-atomic.txt3 0x41,0x7c,0xa0,0x08
4 0x41,0x7c,0xe0,0x08
5 0x41,0xfc,0xa0,0x08
6 0x41,0xfc,0xe0,0x08
7 0x41,0x7c,0xa0,0x48
8 0x41,0x7c,0xe0,0x48
9 0x41,0xfc,0xa0,0x48
10 0x41,0xfc,0xe0,0x48
11 # CHECK: casb w0, w1, [x2]
12 # CHECK: casab w0, w1, [x2]
[all …]
H A Darmv8.8a-mops.txt13 [0x40,0x04,0x01,0x19]
14 [0x40,0x44,0x01,0x19]
15 [0x40,0x84,0x01,0x19]
16 [0x40,0xc4,0x01,0x19]
17 [0x40,0x14,0x01,0x19]
18 [0x40,0x54,0x01,0x19]
19 [0x40,0x94,0x01,0x19]
20 [0x40,0xd4,0x01,0x19]
21 [0x40,0x24,0x01,0x19]
22 [0x40,0x64,0x01,0x19]
[all …]
H A Darm64-logical.txt7 0x00 0x00 0x00 0x12
8 0x00 0x00 0x40 0x92
9 0x41 0x0c 0x00 0x12
10 0x41 0x0c 0x40 0x92
11 0xbf 0xec 0x7c 0x92
12 0x00 0x00 0x00 0x72
13 0x00 0x00 0x40 0xf2
14 0x41 0x0c 0x00 0x72
15 0x41 0x0c 0x40 0xf2
16 0x5f 0x0c 0x40 0xf2
[all …]
/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/
H A Dcalls.ll13 ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
15 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
20 ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implici
[all...]
/llvm-project/llvm/test/CodeGen/AArch64/Atomics/
H A Daarch64_be-cmpxchg-v8a.ll8 ; -O0: ldaxrb w0, [x2]
10 ; -O0: stlxrb w8, w1, [x2]
13 ; -O1: and w8, w0, #0xff
14 ; -O1: ldxrb w0, [x2]
16 ; -O1: stxrb w9, w1, [x2]
18 %r = extractvalue { i8, i1 } %pair, 0
24 ; -O0: ldaxrb w0, [x2]
26 ; -O0: stlxrb w8, w1, [x2]
29 ; -O1: ldxrb w8, [x2]
31 ; -O1: stxrb wzr, w1, [x2]
[all …]
H A Daarch64_be-cmpxchg-lse2.ll8 ; -O0: ldaxrb w0, [x2]
10 ; -O0: stlxrb w8, w1, [x2]
13 ; -O1: and w8, w0, #0xff
14 ; -O1: ldxrb w0, [x2]
16 ; -O1: stxrb w9, w1, [x2]
18 %r = extractvalue { i8, i1 } %pair, 0
24 ; -O0: ldaxrb w0, [x2]
26 ; -O0: stlxrb w8, w1, [x2]
29 ; -O1: ldxrb w8, [x2]
31 ; -O1: stxrb wzr, w1, [x2]
[all …]
H A Daarch64-cmpxchg-lse2.ll8 ; -O0: ldaxrb w0, [x2]
10 ; -O0: stlxrb w8, w1, [x2]
13 ; -O1: and w8, w0, #0xff
14 ; -O1: ldxrb w0, [x2]
16 ; -O1: stxrb w9, w1, [x2]
18 %r = extractvalue { i8, i1 } %pair, 0
24 ; -O0: ldaxrb w0, [x2]
26 ; -O0: stlxrb w8, w1, [x2]
29 ; -O1: ldxrb w8, [x2]
31 ; -O1: stxrb wzr, w1, [x2]
[all …]
H A Daarch64-cmpxchg-rcpc.ll8 ; -O0: ldaxrb w0, [x2]
10 ; -O0: stlxrb w8, w1, [x2]
13 ; -O1: and w8, w0, #0xff
14 ; -O1: ldxrb w0, [x2]
16 ; -O1: stxrb w9, w1, [x2]
18 %r = extractvalue { i8, i1 } %pair, 0
24 ; -O0: ldaxrb w0, [x2]
26 ; -O0: stlxrb w8, w1, [x2]
29 ; -O1: ldxrb w8, [x2]
31 ; -O1: stxrb wzr, w1, [x2]
[all …]
H A Daarch64-cmpxchg-rcpc3.ll8 ; -O0: ldaxrb w0, [x2]
10 ; -O0: stlxrb w8, w1, [x2]
13 ; -O1: and w8, w0, #0xff
14 ; -O1: ldxrb w0, [x2]
16 ; -O1: stxrb w9, w1, [x2]
18 %r = extractvalue { i8, i1 } %pair, 0
24 ; -O0: ldaxrb w0, [x2]
26 ; -O0: stlxrb w8, w1, [x2]
29 ; -O1: ldxrb w8, [x2]
31 ; -O1: stxrb wzr, w1, [x2]
[all …]
H A Daarch64-cmpxchg-v8a.ll8 ; -O0: ldaxrb w0, [x2]
10 ; -O0: stlxrb w8, w1, [x2]
13 ; -O1: and w8, w0, #0xff
14 ; -O1: ldxrb w0, [x2]
16 ; -O1: stxrb w9, w1, [x2]
18 %r = extractvalue { i8, i1 } %pair, 0
24 ; -O0: ldaxrb w0, [x2]
26 ; -O0: stlxrb w8, w1, [x2]
29 ; -O1: ldxrb w8, [x2]
31 ; -O1: stxrb wzr, w1, [x2]
[all …]
H A Daarch64_be-cmpxchg-rcpc.ll8 ; -O0: ldaxrb w0, [x2]
10 ; -O0: stlxrb w8, w1, [x2]
13 ; -O1: and w8, w0, #0xff
14 ; -O1: ldxrb w0, [x2]
16 ; -O1: stxrb w9, w1, [x2]
18 %r = extractvalue { i8, i1 } %pair, 0
24 ; -O0: ldaxrb w0, [x2]
26 ; -O0: stlxrb w8, w1, [x2]
29 ; -O1: ldxrb w8, [x2]
31 ; -O1: stxrb wzr, w1, [x2]
[all …]
H A Daarch64_be-cmpxchg-rcpc3.ll8 ; -O0: ldaxrb w0, [x2]
10 ; -O0: stlxrb w8, w1, [x2]
13 ; -O1: and w8, w0, #0xff
14 ; -O1: ldxrb w0, [x2]
16 ; -O1: stxrb w9, w1, [x2]
18 %r = extractvalue { i8, i1 } %pair, 0
24 ; -O0: ldaxrb w0, [x2]
26 ; -O0: stlxrb w8, w1, [x2]
29 ; -O1: ldxrb w8, [x2]
31 ; -O1: stxrb wzr, w1, [x2]
[all …]
/llvm-project/llvm/test/Bitcode/
H A DmiscInstructions.3.2.ll13 ret i32 0
18 define void @landingpadInstr1(i1 %cond1, <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2){
29 define void @landingpadInstr2(i1 %cond1, <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2){
40 define void @landingpadInstr3(i1 %cond1, <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2){
53 %x = add i32 0, 0
56 ; CHECK: %indvar = phi i32 [ 0, %LoopHeader ], [ %nextindvar, %Loop ]
57 %indvar = phi i32 [ 0, %LoopHeader ], [ %nextindvar, %Loop ]
63 define void @selectInstr(i1 %cond1, <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2){
65 ; CHECK: %res1 = select i1 %cond1, i8 1, i8 0
66 %res1 = select i1 %cond1, i8 1, i8 0
[all …]
/llvm-project/llvm/test/Analysis/ValueTracking/
H A Dknownbits-bmi-pattern.ll11 %x2 = sub i32 %x1, 1
12 %x3 = xor i32 %x1, %x2
22 %x2 = sub <2 x i32> %x1, <i32 1, i32 1>
23 %x3 = xor <2 x i32> %x2, %x1
33 %x2 = sub <2 x i32> %x1, <i32 1, i32 1>
34 %x3 = xor <2 x i32> %x2, %x1
44 %x2 = sub i32 %x1, 1
45 %x3 = xor i32 %x1, %x2
55 %x2 = sub <2 x i32> %x1, <i32 1, i32 1>
56 %x3 = xor <2 x i32> %x2,
[all...]
/llvm-project/llvm/test/CodeGen/RISCV/rvv/
H A Demergency-slot.mir24 stackSize: 0
25 offsetAdjustment: 0
31 cvBytesOfCalleeSavedRegisters: 0
36 localFrameSize: 0
41 - { id: 0, name: '', type: default, offset: 0, size: 2048, alignment: 128,
44 - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8,
47 - { id: 2, name: '', type: spill-slot, offset: 0, size: 400, alignment: 8,
52 ; CHECK: bb.0:
53 ; CHECK-NEXT: successors: %bb.1(0x4000000
[all...]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dmachine-zero-copy-remove.mir10 bb.0.entry:
11 liveins: $w0, $x1, $x2
14 STRWui killed $w0, killed $x1, 0
19 liveins: $x2
22 STRWui killed $w0, killed $x2, 0
34 bb.0.entry:
35 liveins: $x0, $x1, $x2
38 STRXui killed $x0, killed $x1, 0
43 liveins: $x2
46 STRXui killed $x0, killed $x2, 0
[all …]

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