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/freebsd-src/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1028a-kontron-sl28.dts85 reg = <0x5>;
95 nvmem-cells = <&base_mac_address 0>;
118 flash@0 {
122 reg = <0>;
132 partition@0 {
133 reg = <0x000000 0x010000>;
139 reg = <0x010000 0x1d0000>;
145 reg = <0x200000 0x010000>;
150 reg = <0x210000 0x1d0000>;
155 reg = <0x3e0000 0x020000>;
[all …]
H A Dimx8mq-librem5.dtsi29 #clock-cells = <0>;
41 pinctrl-0 = <&pinctrl_keys>;
66 led-0 {
68 pwms = <&pwm2 0 50000 0>;
73 pwms = <&pwm4 0 50000 0>;
78 pwms = <&pwm3 0 50000 0>;
86 pinctrl-0
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dfsl,imx8-acm.yaml227 reg = <0x59e00000 0x1d0000>;
/freebsd-src/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-motherboard.dtsi13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
34 #clock-cells = <0>;
55 gpios = <&iofpga_gpio0 0 0x4>;
62 gpios = <&iofpga_gpio0 1 0x4>;
69 gpios = <&iofpga_gpio0 2 0x4>;
76 gpios = <&iofpga_gpio0 3 0x4>;
83 gpios = <&iofpga_gpio0 4 0x
[all...]
/freebsd-src/sys/dev/otus/
H A Dif_otusreg.h30 #define AR_FW_DOWNLOAD 0x30
31 #define AR_FW_DOWNLOAD_COMPLETE 0x31
36 #define AR_FW_INIT_ADDR 0x102800
37 #define AR_FW_MAIN_ADDR 0x200000
38 #define AR_USB_MODE_CTRL 0x1e1108
43 #define AR_MAC_REG_BASE 0x1c3000
44 #define AR_MAC_REG_DMA_TRIGGER (AR_MAC_REG_BASE + 0xd30)
45 #define AR_MAC_REG_MAC_ADDR_L (AR_MAC_REG_BASE + 0x610)
46 #define AR_MAC_REG_MAC_ADDR_H (AR_MAC_REG_BASE + 0x614)
47 #define AR_MAC_REG_BSSID_L (AR_MAC_REG_BASE + 0x618)
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a00000
[all...]
/freebsd-src/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]