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/freebsd-src/sys/contrib/device-tree/Bindings/spi/
H A Dbrcm,spi-bcm-qspi.yaml103 reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
105 interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>;
115 #address-cells = <0x1>;
116 #size-cells = <0x0>;
118 flash@0 {
119 #size-cells = <0x2>;
120 #address-cells = <0x2>;
122 reg = <0x0>;
123 spi-max-frequency = <0x2625a00>;
132 reg = <0xf0416000 0x180>;
[all …]
H A Dbrcm,spi-bcm-qspi.txt22 Must be <0>, also as required by generic SPI binding.
89 #address-cells = <0x1>;
90 #size-cells = <0x0>;
92 reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;
94 interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
95 interrupt-parent = <0x1c>;
107 m25p80@0 {
108 #size-cells = <0x2>;
109 #address-cells = <0x2>;
111 reg = <0x0>;
[all …]
/freebsd-src/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dregs.h129 #define MT_MCU_WFDMA0_BASE 0x2000
132 #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)
135 #define MT_MCU_WFDMA1_BASE 0x3000
139 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
145 #define MT_PLE_BASE 0x820c0000
148 #define MT_PLE_HOST_RPT0 MT_PLE(0x030)
153 #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)
154 #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)
164 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
166 #define MT_PSE_BASE 0x820c8000
[all …]