Home
last modified time | relevance | path

Searched +full:0 +full:x104 (Results 1 – 25 of 180) sorted by relevance

12345678

/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dallwinner,sun8i-a83t-emac.yaml80 default: 0
81 minimum: 0
88 default: 0
89 minimum: 0
105 default: 0
106 minimum: 0
144 const: 0
159 "^ethernet-phy@[0-9a-f]$":
199 reg = <0x01c0b000 0x104>;
200 interrupts = <0 82 1>;
[all …]
/freebsd-src/sys/netsmb/
H A Dsmb.h42 SMB_DIALECT_CORE, /* PC NETWORK PROGRAM 1.0, PCLAN1.0 */
44 SMB_DIALECT_LANMAN1_0, /* MICROSOFT NETWORKS 3.0, LANMAN1.0 */
70 #define SMB_FLAGS_CASELESS 0x08
71 #define SMB_FLAGS_SERVER_RESP 0x80 /* indicates a response */
76 #define SMB_FLAGS2_KNOWS_LONG_NAMES 0x0001
77 #define SMB_FLAGS2_KNOWS_EAS 0x0002 /* client know about EAs */
78 #define SMB_FLAGS2_SECURITY_SIGNATURE 0x0004 /* check SMB integrity */
79 #define SMB_FLAGS2_IS_LONG_NAME 0x0040 /* any path name is a long name */
80 #define SMB_FLAGS2_EXT_SEC 0x0800 /* client aware of Extended
82 #define SMB_FLAGS2_DFS 0x1000 /* resolve paths in DFS */
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/phy/
H A Dberlin-usb-phy.txt6 - #phys-cells: should be 0
13 reg = <0xf774000 0x128>;
14 #phy-cells = <0>;
15 resets = <&chip 0x104 14>;
/freebsd-src/sys/contrib/device-tree/src/arm/calxeda/
H A Decx-common.dtsi14 cpu_suspend = <0x84000002>;
15 cpu_off = <0x84000004>;
16 cpu_on = <0x84000006>;
27 reg = <0xffe08000 0x10000>;
28 interrupts = <0 83 4>;
30 calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
35 calxeda,led-order = <4 0 1 2 3>;
40 reg = <0xffe0e000 0x1000>;
41 interrupts = <0 90 4>;
48 reg = <0xfff20000 0x1000>;
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/reset/
H A Dberlin,reset.txt22 resets = <&chip_rst 0x104 12>;
/freebsd-src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/freebsd-src/sys/dev/bhnd/bcma/
H A Dbcma_dmp.h47 (((_value) & _flag) != 0)
54 #define BCMA_OOB_BUSCONFIG 0x020
55 #define BCMA_OOB_STATUSA 0x100
56 #define BCMA_OOB_STATUSB 0x104
57 #define BCMA_OOB_STATUSC 0x108
58 #define BCMA_OOB_STATUSD 0x10c
59 #define BCMA_OOB_ENABLEA0 0x200
60 #define BCMA_OOB_ENABLEA1 0x204
61 #define BCMA_OOB_ENABLEA2 0x208
62 #define BCMA_OOB_ENABLEA3 0x20c
[all …]
/freebsd-src/sys/arm/ti/omap4/
H A Domap4_smc.h33 #define L2CACHE_WRITE_DEBUG_REG 0x100
34 #define L2CACHE_CLEAN_INV_RANG 0x101
35 #define L2CACHE_WRITE_CTRL_REG 0x102
36 #define READ_AUX_CORE_REGS 0x103
37 #define MODIFY_AUX_CORE_0 0x104
38 #define WRITE_AUX_CORE_1 0x105
39 #define READ_WKG_CTRL_REG 0x106
40 #define CLEAR_WKG_CTRL_REG 0x107
41 #define SET_POWER_STATUS_REG 0x108
42 #define WRITE_AUXCTRL_REG 0x109
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dcalxeda.yaml20 const: 0
47 reg = <0x3fffc000 0x1000>;
51 #size-cells = <0>;
54 #clock-cells = <0>;
60 #clock-cells = <0>;
63 reg = <0x108>;
67 #clock-cells = <0>;
70 reg = <0x100>;
74 #clock-cells = <0>;
77 reg = <0x104>;
H A Damlogic,a1-peripherals-clkc.yaml65 reg = <0 0x800 0 0x104>;
/freebsd-src/sys/arm/ti/
H A Dti_mbox.h32 #define TI_MBOX_REVISION 0x00
33 #define TI_MBOX_SYSCONFIG 0x10
34 #define TI_MBOX_SYSCONFIG_SOFTRST 0x01
35 #define TI_MBOX_SYSCONFIG_SMARTIDLE (0x02 << 2)
36 #define TI_MBOX_MESSAGE(n) (0x40 + (n) * 0x4)
37 #define TI_MBOX_FIFOSTATUS(n) (0x80 + (n) * 0x4)
38 #define TI_MBOX_MSGSTATUS(n) (0xc0 + (n) * 0x4)
39 #define TI_MBOX_IRQSTATUS_RAW(n) (0x100 + (n) * 0x10)
40 #define TI_MBOX_IRQSTATUS_CLR(n) (0x104 + (n) * 0x10)
41 #define TI_MBOX_IRQENABLE_SET(n) (0x108 + (n) * 0x10)
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
/freebsd-src/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dscorpion_reg_map.h77 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
79 volatile char pad__1[0x8]; /* 0xc - 0x14 */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
/freebsd-src/contrib/netbsd-tests/lib/libcurses/tests/
H A Dstd_defines8 assign TRUE 0x01
9 assign FALSE 0x00
13 assign COLOR_BLACK 0x00
14 assign COLOR_RED 0x01
15 assign COLOR_GREEN 0x02
16 assign COLOR_YELLOW 0x03
17 assign COLOR_BLUE 0x04
18 assign COLOR_MAGENTA 0x05
19 assign COLOR_CYAN 0x06
20 assign COLOR_WHITE 0x07
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-pcie.dtsi8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */
[all …]
H A Dstingray-pinctrl.dtsi37 reg = <0x00140000 0x250>;
45 reg = <0x0014029c 0x26c>;
47 #size-cells = <0>;
49 pinctrl-single,function-mask = <0xf>;
51 &range 0 91 MODE_GPIO
61 0x038 MODE_NITRO /* tsio_0 */
62 0x03c MODE_NITRO /* tsio_1 */
68 0x0ac MODE_PNOR /* nand_ce1_n */
69 0x0b0 MODE_PNOR /* nand_ce0_n */
70 0x0b4 MODE_PNOR /* nand_we_n */
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/synaptics/
H A Dberlin2q.dtsi22 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
113 #clock-cells = <0>;
122 ranges = <0 0xf7000000 0x1000000>;
127 reg = <0xab0000 0x200>;
136 reg = <0xab0800 0x200>;
145 reg = <0xab1000 0x200>;
154 reg = <0xac0000 0x1000>;
163 reg = <0xad0000 0x58>;
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/arm64/ampere/emag/
H A Dcache.json79 "EventCode": "0x34",
85 "EventCode": "0x35",
91 "EventCode": "0x102",
97 "EventCode": "0x103",
103 "EventCode": "0x104",
109 "EventCode": "0x105",
115 "EventCode": "0x106",
121 "EventCode": "0x107",
127 "EventCode": "0x111",
132 "PublicDescription": "Page walk cache level-0 stage-1 hit",
[all …]
/freebsd-src/sys/contrib/device-tree/include/dt-bindings/pinctrl/
H A Domap.h13 #define MUX_MODE0 0
38 #define PIN_OUTPUT 0
46 #define PIN_OFF_NONE 0
57 #define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
59 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
60 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
61 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
62 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
63 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
64 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
[all …]
/freebsd-src/contrib/file/magic/Magdir/
H A Dconsole11 # - https://wiki.nesdev.com/w/index.php/NES_2.0
14 0 name nes-rom-image-ines
15 >7 byte&0x0C =0x8 (NES 2.0)
18 >6 byte&0x08 =0x8 [4-Scr]
19 >6 byte&0x09 =0x0 [H-mirror]
20 >6 byte&0x09 =0x
[all...]
/freebsd-src/sys/contrib/device-tree/src/powerpc/fsl/
H A Dqoriq-mpic4.3.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
42 clock-frequency = <0x0>;
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
56 reg = <0x41600 0x200 0x44148 4>;
[all …]

12345678