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/freebsd-src/sys/dev/nge/
H A Dif_ngereg.h36 #define NGE_CSR 0x00
37 #define NGE_CFG 0x04
38 #define NGE_MEAR 0x08
39 #define NGE_PCITST 0x0C
40 #define NGE_ISR 0x10
41 #define NGE_IMR 0x14
42 #define NGE_IER 0x18
43 #define NGE_IHR 0x1C
44 #define NGE_TX_LISTPTR_LO 0x20
45 #define NGE_TX_LISTPTR_HI 0x24
[all …]
/freebsd-src/contrib/llvm-project/clang/lib/Headers/
H A Dcpuid.h3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
17 /* Responses identification request with %eax 0 */
19 #define signature_AMD_ebx 0x68747541
20 #define signature_AMD_edx 0x69746e65
21 #define signature_AMD_ecx 0x444d4163
23 #define signature_CENTAUR_ebx 0x746e6543
24 #define signature_CENTAUR_edx 0x48727561
25 #define signature_CENTAUR_ecx 0x736c7561
27 #define signature_CYRIX_ebx 0x69727943
28 #define signature_CYRIX_edx 0x736e497
[all...]
/freebsd-src/sys/dev/sis/
H A Dif_sisreg.h45 #define SIS_CSR 0x00
46 #define SIS_CFG 0x04
47 #define SIS_EECTL 0x08
48 #define SIS_PCICTL 0x0C
49 #define SIS_ISR 0x10
50 #define SIS_IMR 0x14
51 #define SIS_IER 0x18
52 #define SIS_PHYCTL 0x1C
53 #define SIS_TX_LISTPTR 0x20
54 #define SIS_TX_CFG 0x24
[all …]
/freebsd-src/sys/contrib/device-tree/src/powerpc/
H A Duc101.dts75 phy0: ethernet-phy@0 {
77 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
105 ranges = <0 0 0xff800000 0x00800000
106 1 0 0x80000000 0x00800000
107 3 0 0x80000000 0x00800000>;
109 flash@0,0 {
111 reg = <0 0 0x00800000>;
117 partition@0 {
[all …]
H A Dpcm032.dts23 memory@0 {
24 reg = <0x00000000 0x08000000>; // 128MB
30 cell-index = <0>;
61 phy0: ethernet-phy@0 {
62 reg = <0>;
69 reg = <0x51>;
73 reg = <0x52>;
80 interrupt-map-mask = <0xf800 0 0 7>;
81 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
82 0xc000 0 0 2 &mpc5200_pic 1 1 3
[all …]
H A Dmucmc52.dts78 phy0: ethernet-phy@0 {
80 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
101 interrupt-map-mask = <0xf800 0 0 7>;
103 /* IDSEL 0x10 */
104 0x8000 0 0 1 &mpc5200_pic 0 3 3
105 0x8000 0 0 2 &mpc5200_pic 0 3 3
106 0x8000 0 0 3 &mpc5200_pic 0 2 3
107 0x8000 0 0 4 &mpc5200_pic 0 1 3
[all …]
H A Ddigsy_mtc.dts19 memory@0 {
20 reg = <0x00000000 0x02000000>; // 32MB
57 phy0: ethernet-phy@0 {
58 reg = <0>;
65 reg = <0x50>;
70 reg = <0x56>;
75 reg = <0x68>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
87 0xc000 0 0 2 &mpc5200_pic 0 0 3
[all …]
H A Dicon.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
H A Dlite5200b.dts22 gpios = <&gpt2 0 1>;
25 gpios = <&gpt3 0 1>;
34 memory@0 {
35 reg = <0x00000000 0x10000000>; // 256MB
41 cell-index = <0>;
87 phy0: ethernet-phy@0 {
88 reg = <0>;
95 reg = <0x50>;
101 reg = <0x8000 0x4000>;
106 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/mtd/
H A Dibm,ndfc.txt5 - reg : should specify chip select and size used for the chip (0x2000).
8 - ccr : NDFC config and control register value (default 0).
9 - bank-settings : NDFC bank configuration register value (default 0).
16 ndfc@1,0 {
18 reg = <0x00000001 0x00000000 0x00002000>;
19 ccr = <0x00001000>;
20 bank-settings = <0x80002222>;
28 partition@0 {
30 reg = <0x00000000 0x00200000>;
34 reg = <0x00200000 0x03E00000>;
/freebsd-src/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x0060000
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-s4-s805x2-aq222.dts21 memory@0 {
23 reg = <0x0 0x0 0x0 0x40000000>;
33 reg = <0x0 0x05000000 0x0 0x3400000>;
40 #clock-cells = <0>;
[all...]
/freebsd-src/sys/dev/sge/
H A Dif_sgereg.h44 #define SIS_VENDORID 0x1039
49 #define SIS_DEVICEID_190 0x0190
50 #define SIS_DEVICEID_191 0x0191
52 #define TX_CTL 0x00
53 #define TX_DESC 0x04
54 #define Reserved0 0x08
55 #define TX_NEXT 0x0c
57 #define RX_CTL 0x10
58 #define RX_DESC 0x14
59 #define Reserved1 0x18
[all …]
/freebsd-src/sys/dev/ale/
H A Dif_alereg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR81XX 0x1026
43 #define ALE_SPI_CTRL 0x200
44 #define SPI_VPD_ENB 0x00002000
46 #define ALE_SPI_ADDR 0x204 /* 16bits */
48 #define ALE_SPI_DATA 0x208
50 #define ALE_SPI_CONFIG 0x20C
52 #define ALE_SPI_OP_PROGRAM 0x210 /* 8bits */
54 #define ALE_SPI_OP_SC_ERASE 0x211 /* 8bits */
56 #define ALE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/marvell/
H A Dkirkwood-ts219.dtsi8 reg = <0x00000000 0x20000000>;
23 reg = <0x30>;
34 reg = <0x12100 0x100>;
40 m25p128@0 {
44 reg = <0>;
46 mode = <0>;
48 partition@0 {
49 reg = <0x00000000 0x00080000>;
54 reg = <0x00200000 0x00200000>;
59 reg = <0x00400000 0x00900000>;
[all …]
/freebsd-src/sys/dev/age/
H A Dif_agereg.h36 #define VENDORID_ATTANSIC 0x1969
41 #define DEVICEID_ATTANSIC_L1 0x1048
43 #define AGE_VPD_REG_CONF_START 0x0100
44 #define AGE_VPD_REG_CONF_END 0x01FF
45 #define AGE_VPD_REG_CONF_SIG 0x5A
47 #define AGE_SPI_CTRL 0x200
48 #define SPI_STAT_NOT_READY 0x00000001
49 #define SPI_STAT_WR_ENB 0x00000002
50 #define SPI_STAT_WRP_ENB 0x00000080
51 #define SPI_INST_MASK 0x000000FF
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm953012hr.dts50 reg = <0x80000000 0x10000000>;
55 partition@0 {
57 reg = <0x00000000 0x00200000>;
62 reg = <0x00200000 0x00400000>;
66 reg = <0x00600000 0x00a00000>;
70 reg = <0x01000000 0x07000000>;
82 partition@0 {
84 reg = <0x00000000 0x000d0000>;
88 reg = <0x000d0000 0x00030000>;
92 reg = <0x00100000 0x00600000>;
[all …]
H A Dbcm953012k.dts48 reg = <0x80000000 0x10000000>;
53 nand@0 {
55 reg = <0>;
64 partition@0 {
66 reg = <0x00000000 0x00200000>;
71 reg = <0x00200000 0x00400000>;
75 reg = <0x00600000 0x00a00000>;
79 reg = <0x01000000 0x07000000>;
92 partition@0 {
94 reg = <0x00000000 0x000d0000>;
[all …]
H A Dbcm958522er.dts48 reg = <0x60000000 0x80000000>;
78 nand@0 {
80 reg = <0>;
91 partition@0 {
93 reg = <0x00000000 0x00200000>;
98 reg = <0x00200000 0x00400000>;
102 reg = <0x00600000 0x00a00000>;
106 reg = <0x01000000 0x03000000>;
110 reg = <0x04000000 0x3c000000>;
129 pinctrl-0 = <&nand_sel>;
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/bus/
H A Dsocionext,uniphier-system-bus.yaml45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":
77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
78 // mapped to 0x43f00000 of the parent bus.
79 // - the UART device is connected at the offset 0x00200000 of CS5 and
80 // mapped to 0x46200000 of the parent bus.
84 reg = <0x58c00000 0x400>;
[all …]
/freebsd-src/sys/dev/sound/pci/
H A Demuxkireg.h50 #define EMU_PTR 0x00
51 #define EMU_PTR_CHNO_MASK 0x0000003f
52 #define EMU_PTR_ADDR_MASK 0x07ff0000
53 #define EMU_A_PTR_ADDR_MASK 0x0fff0000
55 #define EMU_DATA 0x04
57 #define EMU_IPR 0x08
58 #define EMU_IPR_RATETRCHANGE 0x01000000
59 #define EMU_IPR_FXDSP 0x00800000
60 #define EMU_IPR_FORCEINT 0x00400000
61 #define EMU_PCIERROR 0x00200000
[all …]
H A Dvia8233.h42 #define VIA_PCI_SPDIF 0x49
43 #define VIA_SPDIF_EN 0x08
45 #define VIA_DXS0_BASE 0x00
46 #define VIA_DXS1_BASE 0x10
47 #define VIA_DXS2_BASE 0x20
48 #define VIA_DXS3_BASE 0x30
49 #define VIA_DXS_BASE(n) (0x10 * (n))
52 #define VIA8233_RP_DXS_LVOL 0x02
53 #define VIA8233_RP_DXS_RVOL 0x03
54 #define VIA8233_DXS_MUTE 0x3f
[all …]
/freebsd-src/contrib/bearssl/src/symcipher/
H A Ddes_tab.c30 * order (rightmost bit is 0).
36 4, 14, 18, 8, 17, 0, 19
46 24, 7, 13, 0, 21, 17, 1
53 0x00808200, 0x00000000, 0x00008000, 0x00808202,
54 0x00808002, 0x00008202, 0x00000002, 0x00008000,
55 0x00000200, 0x00808200, 0x00808202, 0x00000200,
56 0x00800202, 0x00808002, 0x00800000, 0x00000002,
57 0x00000202, 0x00800200, 0x00800200, 0x00008200,
58 0x00008200, 0x00808000, 0x00808000, 0x00800202,
59 0x00008002, 0x00800002, 0x00800002, 0x00008002,
[all …]
/freebsd-src/sys/powerpc/include/
H A Dspr.h35 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val))
38 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \
48 mfmsr %0; \
49 insrdi %0,%5,1,0; \
50 mtmsrd %0; \
58 clrldi %0,%0,1; \
59 mtmsrd %0; \
66 mfmsr %0; \
[all...]
/freebsd-src/sys/dev/alc/
H A Dif_alcreg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */
42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */
43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */
44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
47 #define DEVICEID_ATHEROS_AR8161 0x1091
48 #define DEVICEID_ATHEROS_AR8162 0x1090
49 #define DEVICEID_ATHEROS_AR8171 0x10A1
[all …]

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