1 /* $NetBSD: zs.c,v 1.28 2021/09/11 20:28:04 andvar Exp $ */
2
3 /*-
4 * Copyright (c) 1996 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Gordon W. Ross.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Zilog Z8530 Dual UART driver (machine-dependent part)
34 *
35 * Runs two serial lines per chip using slave drivers.
36 * Plain tty/async lines use the zs_async slave.
37 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves.
38 */
39
40 #include <sys/cdefs.h>
41 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.28 2021/09/11 20:28:04 andvar Exp $");
42
43 #include "opt_ddb.h"
44
45 #include <sys/param.h>
46 #include <sys/device.h>
47 #include <sys/tty.h>
48 #include <sys/systm.h>
49 #include <sys/cpu.h>
50 #include <sys/intr.h>
51
52 #include <machine/adrsmap.h>
53 #include <machine/z8530var.h>
54
55 #include <dev/ic/z8530reg.h>
56
57 #include "ioconf.h"
58
59 void (*zs_delay)(void);
60
61 #define ZS_DELAY() (*zs_delay)()
62
63 /*
64 * Some warts needed by z8530tty.c -
65 * The default parity REALLY needs to be the same as the PROM uses,
66 * or you can not see messages done with printf during boot-up...
67 */
68 int zs_def_cflag = (CREAD | CS8 | HUPCL);
69
70 int
zs_print(void * aux,const char * name)71 zs_print(void *aux, const char *name)
72 {
73 struct zsc_attach_args *args = aux;
74
75 if (name != NULL)
76 aprint_normal("%s: ", name);
77
78 if (args->channel != -1)
79 aprint_normal(" channel %d", args->channel);
80
81 return UNCONF;
82 }
83
84 /*
85 * Our ZS chips all share a common interrupt level,
86 * but we establish zshard handler per each ZS chips
87 * to avoid holding unnecessary locks in interrupt context.
88 */
89 int
zshard(void * arg)90 zshard(void *arg)
91 {
92 struct zsc_softc *zsc = arg;
93 int rval;
94
95 rval = zsc_intr_hard(zsc);
96 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq)
97 softint_schedule(zsc->zsc_si);
98
99 return rval;
100 }
101
102 /*
103 * Compute the current baud rate given a ZS channel.
104 */
105 int
zs_get_speed(struct zs_chanstate * cs)106 zs_get_speed(struct zs_chanstate *cs)
107 {
108 int tconst;
109
110 tconst = zs_read_reg(cs, 12);
111 tconst |= zs_read_reg(cs, 13) << 8;
112 return TCONST_TO_BPS(cs->cs_brg_clk, tconst);
113 }
114
115 /*
116 * MD functions for setting the baud rate and control modes.
117 */
118 int
zs_set_speed(struct zs_chanstate * cs,int bps)119 zs_set_speed(struct zs_chanstate *cs, int bps)
120 {
121 int tconst, real_bps;
122
123 if (bps == 0)
124 return 0;
125
126 #ifdef DIAGNOSTIC
127 if (cs->cs_brg_clk == 0)
128 panic("zs_set_speed");
129 #endif
130
131 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
132 if (tconst < 0)
133 return EINVAL;
134
135 /* Convert back to make sure we can do it. */
136 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
137
138 /* XXX - Allow some tolerance here? */
139 if (real_bps != bps)
140 return EINVAL;
141
142 cs->cs_preg[12] = tconst;
143 cs->cs_preg[13] = tconst >> 8;
144
145 /* Caller will stuff the pending registers. */
146 return 0;
147 }
148
149 int
zs_set_modes(struct zs_chanstate * cs,int cflag)150 zs_set_modes(struct zs_chanstate *cs, int cflag)
151 {
152 int s;
153
154 /*
155 * Output hardware flow control on the chip is horrendous:
156 * if carrier detect drops, the receiver is disabled, and if
157 * CTS drops, the transmitter is stopped IN MID CHARACTER!
158 * Therefore, NEVER set the HFC bit, and instead use the
159 * status interrupt to detect CTS changes.
160 */
161 s = splserial();
162 cs->cs_rr0_pps = 0;
163 if ((cflag & (CLOCAL | MDMBUF)) != 0) {
164 cs->cs_rr0_dcd = 0;
165 if ((cflag & MDMBUF) == 0)
166 cs->cs_rr0_pps = ZSRR0_DCD;
167 } else
168 cs->cs_rr0_dcd = ZSRR0_DCD;
169 if ((cflag & CRTSCTS) != 0) {
170 cs->cs_wr5_dtr = ZSWR5_DTR;
171 cs->cs_wr5_rts = ZSWR5_RTS;
172 cs->cs_rr0_cts = ZSRR0_CTS;
173 } else if ((cflag & MDMBUF) != 0) {
174 cs->cs_wr5_dtr = 0;
175 cs->cs_wr5_rts = ZSWR5_DTR;
176 cs->cs_rr0_cts = ZSRR0_DCD;
177 } else {
178 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
179 cs->cs_wr5_rts = 0;
180 cs->cs_rr0_cts = 0;
181 }
182 splx(s);
183
184 /* Caller will stuff the pending registers. */
185 return 0;
186 }
187
188 /*
189 * Read or write the chip with suitable delays.
190 */
191
192 uint8_t
zs_read_reg(struct zs_chanstate * cs,uint8_t reg)193 zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
194 {
195 uint8_t val;
196
197 *cs->cs_reg_csr = reg;
198 ZS_DELAY();
199 val = *cs->cs_reg_csr;
200 ZS_DELAY();
201 return val;
202 }
203
204 void
zs_write_reg(struct zs_chanstate * cs,uint8_t reg,uint8_t val)205 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
206 {
207
208 *cs->cs_reg_csr = reg;
209 ZS_DELAY();
210 *cs->cs_reg_csr = val;
211 ZS_DELAY();
212 }
213
214 uint8_t
zs_read_csr(struct zs_chanstate * cs)215 zs_read_csr(struct zs_chanstate *cs)
216 {
217 uint8_t val;
218
219 val = *cs->cs_reg_csr;
220 ZS_DELAY();
221 return val;
222 }
223
224 void
zs_write_csr(struct zs_chanstate * cs,uint8_t val)225 zs_write_csr(struct zs_chanstate *cs, uint8_t val)
226 {
227
228 *cs->cs_reg_csr = val;
229 ZS_DELAY();
230 }
231
232 uint8_t
zs_read_data(struct zs_chanstate * cs)233 zs_read_data(struct zs_chanstate *cs)
234 {
235 uint8_t val;
236
237 val = *cs->cs_reg_data;
238 ZS_DELAY();
239 return val;
240 }
241
242 void
zs_write_data(struct zs_chanstate * cs,uint8_t val)243 zs_write_data(struct zs_chanstate *cs, uint8_t val)
244 {
245
246 *cs->cs_reg_data = val;
247 ZS_DELAY();
248 }
249
250 void
zs_abort(struct zs_chanstate * cs)251 zs_abort(struct zs_chanstate *cs)
252 {
253
254 #ifdef DDB
255 Debugger();
256 #endif
257 }
258