1 /* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2020 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 #ifndef GCC_AARCH64_H 23 #define GCC_AARCH64_H 24 25 /* Target CPU builtins. */ 26 #define TARGET_CPU_CPP_BUILTINS() \ 27 aarch64_cpu_cpp_builtins (pfile) 28 29 /* Target CPU versions for D. */ 30 #define TARGET_D_CPU_VERSIONS aarch64_d_target_versions 31 32 33 34 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas () 35 36 /* Target machine storage layout. */ 37 38 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 39 if (GET_MODE_CLASS (MODE) == MODE_INT \ 40 && GET_MODE_SIZE (MODE) < 4) \ 41 { \ 42 if (MODE == QImode || MODE == HImode) \ 43 { \ 44 MODE = SImode; \ 45 } \ 46 } 47 48 /* Bits are always numbered from the LSBit. */ 49 #define BITS_BIG_ENDIAN 0 50 51 /* Big/little-endian flavour. */ 52 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 53 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 54 55 /* AdvSIMD is supported in the default configuration, unless disabled by 56 -mgeneral-regs-only or by the +nosimd extension. */ 57 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) 58 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) 59 60 #define UNITS_PER_WORD 8 61 62 #define UNITS_PER_VREG 16 63 64 #define PARM_BOUNDARY 64 65 66 #define STACK_BOUNDARY 128 67 68 #define FUNCTION_BOUNDARY 32 69 70 #define EMPTY_FIELD_BOUNDARY 32 71 72 #define BIGGEST_ALIGNMENT 128 73 74 #define SHORT_TYPE_SIZE 16 75 76 #define INT_TYPE_SIZE 32 77 78 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) 79 80 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) 81 82 #define LONG_LONG_TYPE_SIZE 64 83 84 #define FLOAT_TYPE_SIZE 32 85 86 #define DOUBLE_TYPE_SIZE 64 87 88 #define LONG_DOUBLE_TYPE_SIZE 128 89 90 /* This value is the amount of bytes a caller is allowed to drop the stack 91 before probing has to be done for stack clash protection. */ 92 #define STACK_CLASH_CALLER_GUARD 1024 93 94 /* This value represents the minimum amount of bytes we expect the function's 95 outgoing arguments to be when stack-clash is enabled. */ 96 #define STACK_CLASH_MIN_BYTES_OUTGOING_ARGS 8 97 98 /* This value controls how many pages we manually unroll the loop for when 99 generating stack clash probes. */ 100 #define STACK_CLASH_MAX_UNROLL_PAGES 4 101 102 /* The architecture reserves all bits of the address for hardware use, 103 so the vbit must go into the delta field of pointers to member 104 functions. This is the same config as that in the AArch32 105 port. */ 106 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 107 108 109 /* Emit calls to libgcc helpers for atomic operations for runtime detection 110 of LSE instructions. */ 111 #define TARGET_OUTLINE_ATOMICS (aarch64_flag_outline_atomics) 112 113 /* Align definitions of arrays, unions and structures so that 114 initializations and copies can be made more efficient. This is not 115 ABI-changing, so it only affects places where we can see the 116 definition. Increasing the alignment tends to introduce padding, 117 so don't do this when optimizing for size/conserving stack space. */ 118 #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 119 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 120 && (TREE_CODE (EXP) == ARRAY_TYPE \ 121 || TREE_CODE (EXP) == UNION_TYPE \ 122 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 123 124 /* Align global data. */ 125 #define DATA_ALIGNMENT(EXP, ALIGN) \ 126 AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN) 127 128 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 129 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 130 AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN) 131 132 #define STRUCTURE_SIZE_BOUNDARY 8 133 134 /* Heap alignment (same as BIGGEST_ALIGNMENT and STACK_BOUNDARY). */ 135 #define MALLOC_ABI_ALIGNMENT 128 136 137 /* Defined by the ABI */ 138 #define WCHAR_TYPE "unsigned int" 139 #define WCHAR_TYPE_SIZE 32 140 141 /* Using long long breaks -ansi and -std=c90, so these will need to be 142 made conditional for an LLP64 ABI. */ 143 144 #define SIZE_TYPE "long unsigned int" 145 146 #define PTRDIFF_TYPE "long int" 147 148 #define PCC_BITFIELD_TYPE_MATTERS 1 149 150 /* Major revision number of the ARM Architecture implemented by the target. */ 151 extern unsigned aarch64_architecture_version; 152 153 /* Instruction tuning/selection flags. */ 154 155 /* Bit values used to identify processor capabilities. */ 156 #define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */ 157 #define AARCH64_FL_FP (1 << 1) /* Has FP. */ 158 #define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ 159 #define AARCH64_FL_CRC (1 << 3) /* Has CRC. */ 160 /* ARMv8.1-A architecture extensions. */ 161 #define AARCH64_FL_LSE (1 << 4) /* Has Large System Extensions. */ 162 #define AARCH64_FL_RDMA (1 << 5) /* Has Round Double Multiply Add. */ 163 #define AARCH64_FL_V8_1 (1 << 6) /* Has ARMv8.1-A extensions. */ 164 /* ARMv8.2-A architecture extensions. */ 165 #define AARCH64_FL_V8_2 (1 << 8) /* Has ARMv8.2-A features. */ 166 #define AARCH64_FL_F16 (1 << 9) /* Has ARMv8.2-A FP16 extensions. */ 167 #define AARCH64_FL_SVE (1 << 10) /* Has Scalable Vector Extensions. */ 168 /* ARMv8.3-A architecture extensions. */ 169 #define AARCH64_FL_V8_3 (1 << 11) /* Has ARMv8.3-A features. */ 170 #define AARCH64_FL_RCPC (1 << 12) /* Has support for RCpc model. */ 171 #define AARCH64_FL_DOTPROD (1 << 13) /* Has ARMv8.2-A Dot Product ins. */ 172 /* New flags to split crypto into aes and sha2. */ 173 #define AARCH64_FL_AES (1 << 14) /* Has Crypto AES. */ 174 #define AARCH64_FL_SHA2 (1 << 15) /* Has Crypto SHA2. */ 175 /* ARMv8.4-A architecture extensions. */ 176 #define AARCH64_FL_V8_4 (1 << 16) /* Has ARMv8.4-A features. */ 177 #define AARCH64_FL_SM4 (1 << 17) /* Has ARMv8.4-A SM3 and SM4. */ 178 #define AARCH64_FL_SHA3 (1 << 18) /* Has ARMv8.4-a SHA3 and SHA512. */ 179 #define AARCH64_FL_F16FML (1 << 19) /* Has ARMv8.4-a FP16 extensions. */ 180 #define AARCH64_FL_RCPC8_4 (1 << 20) /* Has ARMv8.4-a RCPC extensions. */ 181 182 /* Statistical Profiling extensions. */ 183 #define AARCH64_FL_PROFILE (1 << 21) 184 185 /* ARMv8.5-A architecture extensions. */ 186 #define AARCH64_FL_V8_5 (1 << 22) /* Has ARMv8.5-A features. */ 187 #define AARCH64_FL_RNG (1 << 23) /* ARMv8.5-A Random Number Insns. */ 188 #define AARCH64_FL_MEMTAG (1 << 24) /* ARMv8.5-A Memory Tagging 189 Extensions. */ 190 191 /* Speculation Barrier instruction supported. */ 192 #define AARCH64_FL_SB (1 << 25) 193 194 /* Speculative Store Bypass Safe instruction supported. */ 195 #define AARCH64_FL_SSBS (1 << 26) 196 197 /* Execution and Data Prediction Restriction instructions supported. */ 198 #define AARCH64_FL_PREDRES (1 << 27) 199 200 /* SVE2 instruction supported. */ 201 #define AARCH64_FL_SVE2 (1 << 28) 202 #define AARCH64_FL_SVE2_AES (1 << 29) 203 #define AARCH64_FL_SVE2_SM4 (1 << 30) 204 #define AARCH64_FL_SVE2_SHA3 (1ULL << 31) 205 #define AARCH64_FL_SVE2_BITPERM (1ULL << 32) 206 207 /* Transactional Memory Extension. */ 208 #define AARCH64_FL_TME (1ULL << 33) /* Has TME instructions. */ 209 210 /* Armv8.6-A architecture extensions. */ 211 #define AARCH64_FL_V8_6 (1ULL << 34) 212 213 /* 8-bit Integer Matrix Multiply (I8MM) extensions. */ 214 #define AARCH64_FL_I8MM (1ULL << 35) 215 216 /* Brain half-precision floating-point (BFloat16) Extension. */ 217 #define AARCH64_FL_BF16 (1ULL << 36) 218 219 /* 32-bit Floating-point Matrix Multiply (F32MM) extensions. */ 220 #define AARCH64_FL_F32MM (1ULL << 37) 221 222 /* 64-bit Floating-point Matrix Multiply (F64MM) extensions. */ 223 #define AARCH64_FL_F64MM (1ULL << 38) 224 225 /* Has FP and SIMD. */ 226 #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) 227 228 /* Has FP without SIMD. */ 229 #define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD) 230 231 /* Architecture flags that effect instruction selection. */ 232 #define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) 233 #define AARCH64_FL_FOR_ARCH8_1 \ 234 (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC \ 235 | AARCH64_FL_RDMA | AARCH64_FL_V8_1) 236 #define AARCH64_FL_FOR_ARCH8_2 \ 237 (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2) 238 #define AARCH64_FL_FOR_ARCH8_3 \ 239 (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3 | AARCH64_FL_RCPC) 240 #define AARCH64_FL_FOR_ARCH8_4 \ 241 (AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_V8_4 | AARCH64_FL_F16FML \ 242 | AARCH64_FL_DOTPROD | AARCH64_FL_RCPC8_4) 243 #define AARCH64_FL_FOR_ARCH8_5 \ 244 (AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_5 \ 245 | AARCH64_FL_SB | AARCH64_FL_SSBS | AARCH64_FL_PREDRES) 246 #define AARCH64_FL_FOR_ARCH8_6 \ 247 (AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_V8_6 | AARCH64_FL_FPSIMD \ 248 | AARCH64_FL_I8MM | AARCH64_FL_BF16) 249 250 /* Macros to test ISA flags. */ 251 252 #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) 253 #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) 254 #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) 255 #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) 256 #define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE) 257 #define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_RDMA) 258 #define AARCH64_ISA_V8_2 (aarch64_isa_flags & AARCH64_FL_V8_2) 259 #define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16) 260 #define AARCH64_ISA_SVE (aarch64_isa_flags & AARCH64_FL_SVE) 261 #define AARCH64_ISA_SVE2 (aarch64_isa_flags & AARCH64_FL_SVE2) 262 #define AARCH64_ISA_SVE2_AES (aarch64_isa_flags & AARCH64_FL_SVE2_AES) 263 #define AARCH64_ISA_SVE2_BITPERM (aarch64_isa_flags & AARCH64_FL_SVE2_BITPERM) 264 #define AARCH64_ISA_SVE2_SHA3 (aarch64_isa_flags & AARCH64_FL_SVE2_SHA3) 265 #define AARCH64_ISA_SVE2_SM4 (aarch64_isa_flags & AARCH64_FL_SVE2_SM4) 266 #define AARCH64_ISA_V8_3 (aarch64_isa_flags & AARCH64_FL_V8_3) 267 #define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD) 268 #define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES) 269 #define AARCH64_ISA_SHA2 (aarch64_isa_flags & AARCH64_FL_SHA2) 270 #define AARCH64_ISA_V8_4 (aarch64_isa_flags & AARCH64_FL_V8_4) 271 #define AARCH64_ISA_SM4 (aarch64_isa_flags & AARCH64_FL_SM4) 272 #define AARCH64_ISA_SHA3 (aarch64_isa_flags & AARCH64_FL_SHA3) 273 #define AARCH64_ISA_F16FML (aarch64_isa_flags & AARCH64_FL_F16FML) 274 #define AARCH64_ISA_RCPC (aarch64_isa_flags & AARCH64_FL_RCPC) 275 #define AARCH64_ISA_RCPC8_4 (aarch64_isa_flags & AARCH64_FL_RCPC8_4) 276 #define AARCH64_ISA_RNG (aarch64_isa_flags & AARCH64_FL_RNG) 277 #define AARCH64_ISA_V8_5 (aarch64_isa_flags & AARCH64_FL_V8_5) 278 #define AARCH64_ISA_TME (aarch64_isa_flags & AARCH64_FL_TME) 279 #define AARCH64_ISA_MEMTAG (aarch64_isa_flags & AARCH64_FL_MEMTAG) 280 #define AARCH64_ISA_V8_6 (aarch64_isa_flags & AARCH64_FL_V8_6) 281 #define AARCH64_ISA_I8MM (aarch64_isa_flags & AARCH64_FL_I8MM) 282 #define AARCH64_ISA_F32MM (aarch64_isa_flags & AARCH64_FL_F32MM) 283 #define AARCH64_ISA_F64MM (aarch64_isa_flags & AARCH64_FL_F64MM) 284 #define AARCH64_ISA_BF16 (aarch64_isa_flags & AARCH64_FL_BF16) 285 #define AARCH64_ISA_SB (aarch64_isa_flags & AARCH64_FL_SB) 286 287 /* Crypto is an optional extension to AdvSIMD. */ 288 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) 289 290 /* SHA2 is an optional extension to AdvSIMD. */ 291 #define TARGET_SHA2 ((TARGET_SIMD && AARCH64_ISA_SHA2) || TARGET_CRYPTO) 292 293 /* SHA3 is an optional extension to AdvSIMD. */ 294 #define TARGET_SHA3 (TARGET_SIMD && AARCH64_ISA_SHA3) 295 296 /* AES is an optional extension to AdvSIMD. */ 297 #define TARGET_AES ((TARGET_SIMD && AARCH64_ISA_AES) || TARGET_CRYPTO) 298 299 /* SM is an optional extension to AdvSIMD. */ 300 #define TARGET_SM4 (TARGET_SIMD && AARCH64_ISA_SM4) 301 302 /* FP16FML is an optional extension to AdvSIMD. */ 303 #define TARGET_F16FML (TARGET_SIMD && AARCH64_ISA_F16FML && TARGET_FP_F16INST) 304 305 /* CRC instructions that can be enabled through +crc arch extension. */ 306 #define TARGET_CRC32 (AARCH64_ISA_CRC) 307 308 /* Atomic instructions that can be enabled through the +lse extension. */ 309 #define TARGET_LSE (AARCH64_ISA_LSE) 310 311 /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension. */ 312 #define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16) 313 #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16) 314 315 /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod. */ 316 #define TARGET_DOTPROD (TARGET_SIMD && AARCH64_ISA_DOTPROD) 317 318 /* SVE instructions, enabled through +sve. */ 319 #define TARGET_SVE (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SVE) 320 321 /* SVE2 instructions, enabled through +sve2. */ 322 #define TARGET_SVE2 (TARGET_SVE && AARCH64_ISA_SVE2) 323 324 /* SVE2 AES instructions, enabled through +sve2-aes. */ 325 #define TARGET_SVE2_AES (TARGET_SVE2 && AARCH64_ISA_SVE2_AES) 326 327 /* SVE2 BITPERM instructions, enabled through +sve2-bitperm. */ 328 #define TARGET_SVE2_BITPERM (TARGET_SVE2 && AARCH64_ISA_SVE2_BITPERM) 329 330 /* SVE2 SHA3 instructions, enabled through +sve2-sha3. */ 331 #define TARGET_SVE2_SHA3 (TARGET_SVE2 && AARCH64_ISA_SVE2_SHA3) 332 333 /* SVE2 SM4 instructions, enabled through +sve2-sm4. */ 334 #define TARGET_SVE2_SM4 (TARGET_SVE2 && AARCH64_ISA_SVE2_SM4) 335 336 /* ARMv8.3-A features. */ 337 #define TARGET_ARMV8_3 (AARCH64_ISA_V8_3) 338 339 /* Javascript conversion instruction from Armv8.3-a. */ 340 #define TARGET_JSCVT (TARGET_FLOAT && AARCH64_ISA_V8_3) 341 342 /* Armv8.3-a Complex number extension to AdvSIMD extensions. */ 343 #define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3) 344 345 /* Floating-point rounding instructions from Armv8.5-a. */ 346 #define TARGET_FRINT (AARCH64_ISA_V8_5 && TARGET_FLOAT) 347 348 /* TME instructions are enabled. */ 349 #define TARGET_TME (AARCH64_ISA_TME) 350 351 /* Random number instructions from Armv8.5-a. */ 352 #define TARGET_RNG (AARCH64_ISA_RNG) 353 354 /* Memory Tagging instructions optional to Armv8.5 enabled through +memtag. */ 355 #define TARGET_MEMTAG (AARCH64_ISA_V8_5 && AARCH64_ISA_MEMTAG) 356 357 /* I8MM instructions are enabled through +i8mm. */ 358 #define TARGET_I8MM (AARCH64_ISA_I8MM) 359 #define TARGET_SVE_I8MM (TARGET_SVE && AARCH64_ISA_I8MM) 360 361 /* F32MM instructions are enabled through +f32mm. */ 362 #define TARGET_F32MM (AARCH64_ISA_F32MM) 363 #define TARGET_SVE_F32MM (TARGET_SVE && AARCH64_ISA_F32MM) 364 365 /* F64MM instructions are enabled through +f64mm. */ 366 #define TARGET_F64MM (AARCH64_ISA_F64MM) 367 #define TARGET_SVE_F64MM (TARGET_SVE && AARCH64_ISA_F64MM) 368 369 /* BF16 instructions are enabled through +bf16. */ 370 #define TARGET_BF16_FP (AARCH64_ISA_BF16) 371 #define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD) 372 #define TARGET_SVE_BF16 (TARGET_SVE && AARCH64_ISA_BF16) 373 374 /* Make sure this is always defined so we don't have to check for ifdefs 375 but rather use normal ifs. */ 376 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT 377 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0 378 #else 379 #undef TARGET_FIX_ERR_A53_835769_DEFAULT 380 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1 381 #endif 382 383 /* SB instruction is enabled through +sb. */ 384 #define TARGET_SB (AARCH64_ISA_SB) 385 386 /* Apply the workaround for Cortex-A53 erratum 835769. */ 387 #define TARGET_FIX_ERR_A53_835769 \ 388 ((aarch64_fix_a53_err835769 == 2) \ 389 ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769) 390 391 /* Make sure this is always defined so we don't have to check for ifdefs 392 but rather use normal ifs. */ 393 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT 394 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0 395 #else 396 #undef TARGET_FIX_ERR_A53_843419_DEFAULT 397 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1 398 #endif 399 400 /* Apply the workaround for Cortex-A53 erratum 843419. */ 401 #define TARGET_FIX_ERR_A53_843419 \ 402 ((aarch64_fix_a53_err843419 == 2) \ 403 ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419) 404 405 /* ARMv8.1-A Adv.SIMD support. */ 406 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA) 407 408 /* Standard register usage. */ 409 410 /* 31 64-bit general purpose registers R0-R30: 411 R30 LR (link register) 412 R29 FP (frame pointer) 413 R19-R28 Callee-saved registers 414 R18 The platform register; use as temporary register. 415 R17 IP1 The second intra-procedure-call temporary register 416 (can be used by call veneers and PLT code); otherwise use 417 as a temporary register 418 R16 IP0 The first intra-procedure-call temporary register (can 419 be used by call veneers and PLT code); otherwise use as a 420 temporary register 421 R9-R15 Temporary registers 422 R8 Structure value parameter / temporary register 423 R0-R7 Parameter/result registers 424 425 SP stack pointer, encoded as X/R31 where permitted. 426 ZR zero register, encoded as X/R31 elsewhere 427 428 32 x 128-bit floating-point/vector registers 429 V16-V31 Caller-saved (temporary) registers 430 V8-V15 Callee-saved registers 431 V0-V7 Parameter/result registers 432 433 The vector register V0 holds scalar B0, H0, S0 and D0 in its least 434 significant bits. Unlike AArch32 S1 is not packed into D0, etc. 435 436 P0-P7 Predicate low registers: valid in all predicate contexts 437 P8-P15 Predicate high registers: used as scratch space 438 439 FFR First Fault Register, a fixed-use SVE predicate register 440 FFRT FFR token: a fake register used for modelling dependencies 441 442 VG Pseudo "vector granules" register 443 444 VG is the number of 64-bit elements in an SVE vector. We define 445 it as a hard register so that we can easily map it to the DWARF VG 446 register. GCC internally uses the poly_int variable aarch64_sve_vg 447 instead. */ 448 449 #define FIXED_REGISTERS \ 450 { \ 451 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ 452 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ 453 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 454 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ 455 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ 456 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 457 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ 458 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ 459 1, 1, 1, 1, /* SFP, AP, CC, VG */ \ 460 0, 0, 0, 0, 0, 0, 0, 0, /* P0 - P7 */ \ 461 0, 0, 0, 0, 0, 0, 0, 0, /* P8 - P15 */ \ 462 1, 1 /* FFR and FFRT */ \ 463 } 464 465 /* X30 is marked as caller-saved which is in line with regular function call 466 behavior since the call instructions clobber it; AARCH64_EXPAND_CALL does 467 that for regular function calls and avoids it for sibcalls. X30 is 468 considered live for sibcalls; EPILOGUE_USES helps achieve that by returning 469 true but not until function epilogues have been generated. This ensures 470 that X30 is available for use in leaf functions if needed. */ 471 472 #define CALL_USED_REGISTERS \ 473 { \ 474 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ 475 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ 476 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 477 0, 0, 0, 0, 0, 1, 1, 1, /* R24 - R30, SP */ \ 478 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ 479 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 480 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ 481 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ 482 1, 1, 1, 1, /* SFP, AP, CC, VG */ \ 483 1, 1, 1, 1, 1, 1, 1, 1, /* P0 - P7 */ \ 484 1, 1, 1, 1, 1, 1, 1, 1, /* P8 - P15 */ \ 485 1, 1 /* FFR and FFRT */ \ 486 } 487 488 #define REGISTER_NAMES \ 489 { \ 490 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ 491 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ 492 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ 493 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ 494 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ 495 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ 496 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ 497 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ 498 "sfp", "ap", "cc", "vg", \ 499 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", \ 500 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", \ 501 "ffr", "ffrt" \ 502 } 503 504 /* Generate the register aliases for core register N */ 505 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ 506 {"w" # N, R0_REGNUM + (N)} 507 508 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ 509 {"d" # N, V0_REGNUM + (N)}, \ 510 {"s" # N, V0_REGNUM + (N)}, \ 511 {"h" # N, V0_REGNUM + (N)}, \ 512 {"b" # N, V0_REGNUM + (N)}, \ 513 {"z" # N, V0_REGNUM + (N)} 514 515 /* Provide aliases for all of the ISA defined register name forms. 516 These aliases are convenient for use in the clobber lists of inline 517 asm statements. */ 518 519 #define ADDITIONAL_REGISTER_NAMES \ 520 { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ 521 R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ 522 R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ 523 R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ 524 R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ 525 R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ 526 R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ 527 R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \ 528 V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ 529 V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ 530 V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ 531 V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ 532 V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ 533 V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ 534 V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ 535 V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ 536 } 537 538 #define EPILOGUE_USES(REGNO) (aarch64_epilogue_uses (REGNO)) 539 540 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 541 the stack pointer does not matter. This is only true if the function 542 uses alloca. */ 543 #define EXIT_IGNORE_STACK (cfun->calls_alloca) 544 545 #define STATIC_CHAIN_REGNUM R18_REGNUM 546 #define HARD_FRAME_POINTER_REGNUM R29_REGNUM 547 #define FRAME_POINTER_REGNUM SFP_REGNUM 548 #define STACK_POINTER_REGNUM SP_REGNUM 549 #define ARG_POINTER_REGNUM AP_REGNUM 550 #define FIRST_PSEUDO_REGISTER (FFRT_REGNUM + 1) 551 552 /* The number of argument registers available for each class. */ 553 #define NUM_ARG_REGS 8 554 #define NUM_FP_ARG_REGS 8 555 #define NUM_PR_ARG_REGS 4 556 557 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most 558 four members. */ 559 #define HA_MAX_NUM_FLDS 4 560 561 /* External dwarf register number scheme. These number are used to 562 identify registers in dwarf debug information, the values are 563 defined by the AArch64 ABI. The numbering scheme is independent of 564 GCC's internal register numbering scheme. */ 565 566 #define AARCH64_DWARF_R0 0 567 568 /* The number of R registers, note 31! not 32. */ 569 #define AARCH64_DWARF_NUMBER_R 31 570 571 #define AARCH64_DWARF_SP 31 572 #define AARCH64_DWARF_VG 46 573 #define AARCH64_DWARF_P0 48 574 #define AARCH64_DWARF_V0 64 575 576 /* The number of V registers. */ 577 #define AARCH64_DWARF_NUMBER_V 32 578 579 /* For signal frames we need to use an alternative return column. This 580 value must not correspond to a hard register and must be out of the 581 range of DWARF_FRAME_REGNUM(). */ 582 #define DWARF_ALT_FRAME_RETURN_COLUMN \ 583 (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) 584 585 /* We add 1 extra frame register for use as the 586 DWARF_ALT_FRAME_RETURN_COLUMN. */ 587 #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) 588 589 590 #define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO) 591 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders 592 can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same 593 as the default definition in dwarf2out.c. */ 594 #undef DWARF_FRAME_REGNUM 595 #define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO) 596 597 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 598 599 #define DWARF2_UNWIND_INFO 1 600 601 /* Use R0 through R3 to pass exception handling information. */ 602 #define EH_RETURN_DATA_REGNO(N) \ 603 ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) 604 605 /* Select a format to encode pointers in exception handling data. */ 606 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 607 aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) 608 609 /* Output the assembly strings we want to add to a function definition. */ 610 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ 611 aarch64_declare_function_name (STR, NAME, DECL) 612 613 /* Output assembly strings for alias definition. */ 614 #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \ 615 aarch64_asm_output_alias (STR, DECL, TARGET) 616 617 /* Output assembly strings for undefined extern symbols. */ 618 #undef ASM_OUTPUT_EXTERNAL 619 #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \ 620 aarch64_asm_output_external (STR, DECL, NAME) 621 622 /* Output assembly strings after .cfi_startproc is emitted. */ 623 #define ASM_POST_CFI_STARTPROC aarch64_post_cfi_startproc 624 625 /* For EH returns X4 contains the stack adjustment. */ 626 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, R4_REGNUM) 627 #define EH_RETURN_HANDLER_RTX aarch64_eh_return_handler_rtx () 628 629 /* Don't use __builtin_setjmp until we've defined it. */ 630 #undef DONT_USE_BUILTIN_SETJMP 631 #define DONT_USE_BUILTIN_SETJMP 1 632 633 #undef TARGET_COMPUTE_FRAME_LAYOUT 634 #define TARGET_COMPUTE_FRAME_LAYOUT aarch64_layout_frame 635 636 /* Register in which the structure value is to be returned. */ 637 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM 638 639 /* Non-zero if REGNO is part of the Core register set. 640 641 The rather unusual way of expressing this check is to avoid 642 warnings when building the compiler when R0_REGNUM is 0 and REGNO 643 is unsigned. */ 644 #define GP_REGNUM_P(REGNO) \ 645 (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) 646 647 /* Registers known to be preserved over a BL instruction. This consists of the 648 GENERAL_REGS without x16, x17, and x30. The x30 register is changed by the 649 BL instruction itself, while the x16 and x17 registers may be used by 650 veneers which can be inserted by the linker. */ 651 #define STUB_REGNUM_P(REGNO) \ 652 (GP_REGNUM_P (REGNO) \ 653 && (REGNO) != R16_REGNUM \ 654 && (REGNO) != R17_REGNUM \ 655 && (REGNO) != R30_REGNUM) \ 656 657 #define FP_REGNUM_P(REGNO) \ 658 (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) 659 660 #define FP_LO_REGNUM_P(REGNO) \ 661 (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) 662 663 #define FP_LO8_REGNUM_P(REGNO) \ 664 (((unsigned) (REGNO - V0_REGNUM)) <= (V7_REGNUM - V0_REGNUM)) 665 666 #define PR_REGNUM_P(REGNO)\ 667 (((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM)) 668 669 #define PR_LO_REGNUM_P(REGNO)\ 670 (((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM)) 671 672 #define FP_SIMD_SAVED_REGNUM_P(REGNO) \ 673 (((unsigned) (REGNO - V8_REGNUM)) <= (V23_REGNUM - V8_REGNUM)) 674 675 /* Register and constant classes. */ 676 677 enum reg_class 678 { 679 NO_REGS, 680 TAILCALL_ADDR_REGS, 681 STUB_REGS, 682 GENERAL_REGS, 683 STACK_REG, 684 POINTER_REGS, 685 FP_LO8_REGS, 686 FP_LO_REGS, 687 FP_REGS, 688 POINTER_AND_FP_REGS, 689 PR_LO_REGS, 690 PR_HI_REGS, 691 PR_REGS, 692 FFR_REGS, 693 PR_AND_FFR_REGS, 694 ALL_REGS, 695 LIM_REG_CLASSES /* Last */ 696 }; 697 698 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 699 700 #define REG_CLASS_NAMES \ 701 { \ 702 "NO_REGS", \ 703 "TAILCALL_ADDR_REGS", \ 704 "STUB_REGS", \ 705 "GENERAL_REGS", \ 706 "STACK_REG", \ 707 "POINTER_REGS", \ 708 "FP_LO8_REGS", \ 709 "FP_LO_REGS", \ 710 "FP_REGS", \ 711 "POINTER_AND_FP_REGS", \ 712 "PR_LO_REGS", \ 713 "PR_HI_REGS", \ 714 "PR_REGS", \ 715 "FFR_REGS", \ 716 "PR_AND_FFR_REGS", \ 717 "ALL_REGS" \ 718 } 719 720 #define REG_CLASS_CONTENTS \ 721 { \ 722 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 723 { 0x00030000, 0x00000000, 0x00000000 }, /* TAILCALL_ADDR_REGS */\ 724 { 0x3ffcffff, 0x00000000, 0x00000000 }, /* STUB_REGS */ \ 725 { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ 726 { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 727 { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ 728 { 0x00000000, 0x000000ff, 0x00000000 }, /* FP_LO8_REGS */ \ 729 { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ 730 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ 731 { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\ 732 { 0x00000000, 0x00000000, 0x00000ff0 }, /* PR_LO_REGS */ \ 733 { 0x00000000, 0x00000000, 0x000ff000 }, /* PR_HI_REGS */ \ 734 { 0x00000000, 0x00000000, 0x000ffff0 }, /* PR_REGS */ \ 735 { 0x00000000, 0x00000000, 0x00300000 }, /* FFR_REGS */ \ 736 { 0x00000000, 0x00000000, 0x003ffff0 }, /* PR_AND_FFR_REGS */ \ 737 { 0xffffffff, 0xffffffff, 0x000fffff } /* ALL_REGS */ \ 738 } 739 740 #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) 741 742 #define INDEX_REG_CLASS GENERAL_REGS 743 #define BASE_REG_CLASS POINTER_REGS 744 745 /* Register pairs used to eliminate unneeded registers that point into 746 the stack frame. */ 747 #define ELIMINABLE_REGS \ 748 { \ 749 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 750 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 751 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 752 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 753 } 754 755 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 756 (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) 757 758 /* CPU/ARCH option handling. */ 759 #include "config/aarch64/aarch64-opts.h" 760 761 enum target_cpus 762 { 763 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \ 764 TARGET_CPU_##INTERNAL_IDENT, 765 #include "aarch64-cores.def" 766 TARGET_CPU_generic 767 }; 768 769 /* If there is no CPU defined at configure, use generic as default. */ 770 #ifndef TARGET_CPU_DEFAULT 771 #define TARGET_CPU_DEFAULT \ 772 (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) 773 #endif 774 775 /* If inserting NOP before a mult-accumulate insn remember to adjust the 776 length so that conditional branching code is updated appropriately. */ 777 #define ADJUST_INSN_LENGTH(insn, length) \ 778 do \ 779 { \ 780 if (aarch64_madd_needs_nop (insn)) \ 781 length += 4; \ 782 } while (0) 783 784 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 785 aarch64_final_prescan_insn (INSN); \ 786 787 /* The processor for which instructions should be scheduled. */ 788 extern enum aarch64_processor aarch64_tune; 789 790 /* RTL generation support. */ 791 #define INIT_EXPANDERS aarch64_init_expanders () 792 793 794 /* Stack layout; function entry, exit and calling. */ 795 #define STACK_GROWS_DOWNWARD 1 796 797 #define FRAME_GROWS_DOWNWARD 1 798 799 #define ACCUMULATE_OUTGOING_ARGS 1 800 801 #define FIRST_PARM_OFFSET(FNDECL) 0 802 803 /* Fix for VFP */ 804 #define LIBCALL_VALUE(MODE) \ 805 gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) 806 807 #define DEFAULT_PCC_STRUCT_RETURN 0 808 809 #ifdef HAVE_POLY_INT_H 810 struct GTY (()) aarch64_frame 811 { 812 poly_int64 reg_offset[LAST_SAVED_REGNUM + 1]; 813 814 /* The number of extra stack bytes taken up by register varargs. 815 This area is allocated by the callee at the very top of the 816 frame. This value is rounded up to a multiple of 817 STACK_BOUNDARY. */ 818 HOST_WIDE_INT saved_varargs_size; 819 820 /* The size of the callee-save registers with a slot in REG_OFFSET. */ 821 poly_int64 saved_regs_size; 822 823 /* The size of the callee-save registers with a slot in REG_OFFSET that 824 are saved below the hard frame pointer. */ 825 poly_int64 below_hard_fp_saved_regs_size; 826 827 /* Offset from the base of the frame (incomming SP) to the 828 top of the locals area. This value is always a multiple of 829 STACK_BOUNDARY. */ 830 poly_int64 locals_offset; 831 832 /* Offset from the base of the frame (incomming SP) to the 833 hard_frame_pointer. This value is always a multiple of 834 STACK_BOUNDARY. */ 835 poly_int64 hard_fp_offset; 836 837 /* The size of the frame. This value is the offset from base of the 838 frame (incomming SP) to the stack_pointer. This value is always 839 a multiple of STACK_BOUNDARY. */ 840 poly_int64 frame_size; 841 842 /* The size of the initial stack adjustment before saving callee-saves. */ 843 poly_int64 initial_adjust; 844 845 /* The writeback value when pushing callee-save registers. 846 It is zero when no push is used. */ 847 HOST_WIDE_INT callee_adjust; 848 849 /* The offset from SP to the callee-save registers after initial_adjust. 850 It may be non-zero if no push is used (ie. callee_adjust == 0). */ 851 poly_int64 callee_offset; 852 853 /* The size of the stack adjustment before saving or after restoring 854 SVE registers. */ 855 poly_int64 sve_callee_adjust; 856 857 /* The size of the stack adjustment after saving callee-saves. */ 858 poly_int64 final_adjust; 859 860 /* Store FP,LR and setup a frame pointer. */ 861 bool emit_frame_chain; 862 863 unsigned wb_candidate1; 864 unsigned wb_candidate2; 865 866 /* Big-endian SVE frames need a spare predicate register in order 867 to save vector registers in the correct layout for unwinding. 868 This is the register they should use. */ 869 unsigned spare_pred_reg; 870 871 bool laid_out; 872 }; 873 874 typedef struct GTY (()) machine_function 875 { 876 struct aarch64_frame frame; 877 /* One entry for each hard register. */ 878 bool reg_is_wrapped_separately[LAST_SAVED_REGNUM]; 879 /* One entry for each general purpose register. */ 880 rtx call_via[SP_REGNUM]; 881 bool label_is_assembled; 882 } machine_function; 883 #endif 884 885 /* Which ABI to use. */ 886 enum aarch64_abi_type 887 { 888 AARCH64_ABI_LP64 = 0, 889 AARCH64_ABI_ILP32 = 1 890 }; 891 892 #ifndef AARCH64_ABI_DEFAULT 893 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64 894 #endif 895 896 #define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32) 897 898 enum arm_pcs 899 { 900 ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ 901 ARM_PCS_SIMD, /* For aarch64_vector_pcs functions. */ 902 ARM_PCS_SVE, /* For functions that pass or return 903 values in SVE registers. */ 904 ARM_PCS_TLSDESC, /* For targets of tlsdesc calls. */ 905 ARM_PCS_UNKNOWN 906 }; 907 908 909 910 911 /* We can't use machine_mode inside a generator file because it 912 hasn't been created yet; we shouldn't be using any code that 913 needs the real definition though, so this ought to be safe. */ 914 #ifdef GENERATOR_FILE 915 #define MACHMODE int 916 #else 917 #include "insn-modes.h" 918 #define MACHMODE machine_mode 919 #endif 920 921 #ifndef USED_FOR_TARGET 922 /* AAPCS related state tracking. */ 923 typedef struct 924 { 925 enum arm_pcs pcs_variant; 926 int aapcs_arg_processed; /* No need to lay out this argument again. */ 927 int aapcs_ncrn; /* Next Core register number. */ 928 int aapcs_nextncrn; /* Next next core register number. */ 929 int aapcs_nvrn; /* Next Vector register number. */ 930 int aapcs_nextnvrn; /* Next Next Vector register number. */ 931 int aapcs_nprn; /* Next Predicate register number. */ 932 int aapcs_nextnprn; /* Next Next Predicate register number. */ 933 rtx aapcs_reg; /* Register assigned to this argument. This 934 is NULL_RTX if this parameter goes on 935 the stack. */ 936 MACHMODE aapcs_vfp_rmode; 937 int aapcs_stack_words; /* If the argument is passed on the stack, this 938 is the number of words needed, after rounding 939 up. Only meaningful when 940 aapcs_reg == NULL_RTX. */ 941 int aapcs_stack_size; /* The total size (in words, per 8 byte) of the 942 stack arg area so far. */ 943 bool silent_p; /* True if we should act silently, rather than 944 raise an error for invalid calls. */ 945 } CUMULATIVE_ARGS; 946 #endif 947 948 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 949 (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) 950 951 #define PAD_VARARGS_DOWN 0 952 953 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 954 aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) 955 956 #define FUNCTION_ARG_REGNO_P(REGNO) \ 957 aarch64_function_arg_regno_p(REGNO) 958 959 960 /* ISA Features. */ 961 962 /* Addressing modes, etc. */ 963 #define HAVE_POST_INCREMENT 1 964 #define HAVE_PRE_INCREMENT 1 965 #define HAVE_POST_DECREMENT 1 966 #define HAVE_PRE_DECREMENT 1 967 #define HAVE_POST_MODIFY_DISP 1 968 #define HAVE_PRE_MODIFY_DISP 1 969 970 #define MAX_REGS_PER_ADDRESS 2 971 972 #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) 973 974 #define REGNO_OK_FOR_BASE_P(REGNO) \ 975 aarch64_regno_ok_for_base_p (REGNO, true) 976 977 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 978 aarch64_regno_ok_for_index_p (REGNO, true) 979 980 #define LEGITIMATE_PIC_OPERAND_P(X) \ 981 aarch64_legitimate_pic_operand_p (X) 982 983 #define CASE_VECTOR_MODE Pmode 984 985 #define DEFAULT_SIGNED_CHAR 0 986 987 /* An integer expression for the size in bits of the largest integer machine 988 mode that should actually be used. We allow pairs of registers. */ 989 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 990 991 /* Maximum bytes moved by a single instruction (load/store pair). */ 992 #define MOVE_MAX (UNITS_PER_WORD * 2) 993 994 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ 995 #define AARCH64_CALL_RATIO 8 996 997 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure. 998 move_by_pieces will continually copy the largest safe chunks. So a 999 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient 1000 for both size and speed of copy, so we will instead use the "cpymem" 1001 standard name to implement the copy. This logic does not apply when 1002 targeting -mstrict-align, so keep a sensible default in that case. */ 1003 #define MOVE_RATIO(speed) \ 1004 (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)) 1005 1006 /* For CLEAR_RATIO, when optimizing for size, give a better estimate 1007 of the length of a memset call, but use the default otherwise. */ 1008 #define CLEAR_RATIO(speed) \ 1009 ((speed) ? 15 : AARCH64_CALL_RATIO) 1010 1011 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when 1012 optimizing for size adjust the ratio to account for the overhead of loading 1013 the constant. */ 1014 #define SET_RATIO(speed) \ 1015 ((speed) ? 15 : AARCH64_CALL_RATIO - 2) 1016 1017 /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is 1018 rarely a good idea in straight-line code since it adds an extra address 1019 dependency between each instruction. Better to use incrementing offsets. */ 1020 #define USE_LOAD_POST_INCREMENT(MODE) 0 1021 #define USE_LOAD_POST_DECREMENT(MODE) 0 1022 #define USE_LOAD_PRE_INCREMENT(MODE) 0 1023 #define USE_LOAD_PRE_DECREMENT(MODE) 0 1024 #define USE_STORE_POST_INCREMENT(MODE) 0 1025 #define USE_STORE_POST_DECREMENT(MODE) 0 1026 #define USE_STORE_PRE_INCREMENT(MODE) 0 1027 #define USE_STORE_PRE_DECREMENT(MODE) 0 1028 1029 /* WORD_REGISTER_OPERATIONS does not hold for AArch64. 1030 The assigned word_mode is DImode but operations narrower than SImode 1031 behave as 32-bit operations if using the W-form of the registers rather 1032 than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS 1033 expects. */ 1034 #define WORD_REGISTER_OPERATIONS 0 1035 1036 /* Define if loading from memory in MODE, an integral mode narrower than 1037 BITS_PER_WORD will either zero-extend or sign-extend. The value of this 1038 macro should be the code that says which one of the two operations is 1039 implicitly done, or UNKNOWN if none. */ 1040 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1041 1042 /* Define this macro to be non-zero if instructions will fail to work 1043 if given data not on the nominal alignment. */ 1044 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN 1045 1046 /* Enable wide bitfield accesses for more efficient bitfield code. */ 1047 #define SLOW_BYTE_ACCESS 1 1048 1049 #define NO_FUNCTION_CSE 1 1050 1051 /* Specify the machine mode that the hardware addresses have. 1052 After generation of rtl, the compiler makes no further distinction 1053 between pointers and any other objects of this machine mode. */ 1054 #define Pmode DImode 1055 1056 /* A C expression whose value is zero if pointers that need to be extended 1057 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 1058 greater then zero if they are zero-extended and less then zero if the 1059 ptr_extend instruction should be used. */ 1060 #define POINTERS_EXTEND_UNSIGNED 1 1061 1062 /* Mode of a function address in a call instruction (for indexing purposes). */ 1063 #define FUNCTION_MODE Pmode 1064 1065 #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) 1066 1067 /* Having an integer comparison mode guarantees that we can use 1068 reverse_condition, but the usual restrictions apply to floating-point 1069 comparisons. */ 1070 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPmode && (MODE) != CCFPEmode) 1071 1072 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1073 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 1074 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1075 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 1076 1077 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 1078 1079 #define RETURN_ADDR_RTX aarch64_return_addr 1080 1081 /* BTI c + 3 insns 1082 + sls barrier of DSB + ISB. 1083 + 2 pointer-sized entries. */ 1084 #define TRAMPOLINE_SIZE (24 + (TARGET_ILP32 ? 8 : 16)) 1085 1086 /* Trampolines contain dwords, so must be dword aligned. */ 1087 #define TRAMPOLINE_ALIGNMENT 64 1088 1089 /* Put trampolines in the text section so that mapping symbols work 1090 correctly. */ 1091 #define TRAMPOLINE_SECTION text_section 1092 1093 /* To start with. */ 1094 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ 1095 (aarch64_branch_cost (SPEED_P, PREDICTABLE_P)) 1096 1097 1098 /* Assembly output. */ 1099 1100 /* For now we'll make all jump tables pc-relative. */ 1101 #define CASE_VECTOR_PC_RELATIVE 1 1102 1103 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 1104 ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ 1105 : (min < -0x1f0 || max > 0x1f0) ? HImode \ 1106 : QImode) 1107 1108 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 1109 #define ADDR_VEC_ALIGN(JUMPTABLE) 0 1110 1111 #define MCOUNT_NAME "_mcount" 1112 1113 #define NO_PROFILE_COUNTERS 1 1114 1115 /* Emit rtl for profiling. Output assembler code to FILE 1116 to call "_mcount" for profiling a function entry. */ 1117 #define PROFILE_HOOK(LABEL) \ 1118 { \ 1119 rtx fun, lr; \ 1120 lr = aarch64_return_addr_rtx (); \ 1121 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ 1122 emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode); \ 1123 } 1124 1125 /* All the work done in PROFILE_HOOK, but still required. */ 1126 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) 1127 1128 /* For some reason, the Linux headers think they know how to define 1129 these macros. They don't!!! */ 1130 #undef ASM_APP_ON 1131 #undef ASM_APP_OFF 1132 #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" 1133 #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" 1134 1135 #define CONSTANT_POOL_BEFORE_FUNCTION 0 1136 1137 /* This definition should be relocated to aarch64-elf-raw.h. This macro 1138 should be undefined in aarch64-linux.h and a clear_cache pattern 1139 implmented to emit either the call to __aarch64_sync_cache_range() 1140 directly or preferably the appropriate sycall or cache clear 1141 instructions inline. */ 1142 #define CLEAR_INSN_CACHE(beg, end) \ 1143 extern void __aarch64_sync_cache_range (void *, void *); \ 1144 __aarch64_sync_cache_range (beg, end) 1145 1146 #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD) 1147 1148 /* Choose appropriate mode for caller saves, so we do the minimum 1149 required size of load/store. */ 1150 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1151 aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) 1152 1153 #undef SWITCHABLE_TARGET 1154 #define SWITCHABLE_TARGET 1 1155 1156 /* Check TLS Descriptors mechanism is selected. */ 1157 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) 1158 1159 extern enum aarch64_code_model aarch64_cmodel; 1160 1161 /* When using the tiny addressing model conditional and unconditional branches 1162 can span the whole of the available address space (1MB). */ 1163 #define HAS_LONG_COND_BRANCH \ 1164 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 1165 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 1166 1167 #define HAS_LONG_UNCOND_BRANCH \ 1168 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 1169 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 1170 1171 #define TARGET_SUPPORTS_WIDE_INT 1 1172 1173 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */ 1174 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \ 1175 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1176 || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \ 1177 || (MODE) == DFmode || (MODE) == V4BFmode) 1178 1179 /* Modes valid for AdvSIMD Q registers. */ 1180 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ 1181 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1182 || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \ 1183 || (MODE) == V2DFmode || (MODE) == V8BFmode) 1184 1185 #define ENDIAN_LANE_N(NUNITS, N) \ 1186 (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N) 1187 1188 /* Support for configure-time --with-arch, --with-cpu and --with-tune. 1189 --with-arch and --with-cpu are ignored if either -mcpu or -march is used. 1190 --with-tune is ignored if either -mtune or -mcpu is used (but is not 1191 affected by -march). */ 1192 #define OPTION_DEFAULT_SPECS \ 1193 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 1194 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 1195 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}"}, 1196 1197 #define MCPU_TO_MARCH_SPEC \ 1198 " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}" 1199 1200 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv); 1201 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \ 1202 { "rewrite_mcpu", aarch64_rewrite_mcpu }, 1203 1204 #if defined(__aarch64__) && (defined(__linux__) || defined(__NetBSD__)) 1205 extern const char *host_detect_local_cpu (int argc, const char **argv); 1206 #define HAVE_LOCAL_CPU_DETECT 1207 # define EXTRA_SPEC_FUNCTIONS \ 1208 { "local_cpu_detect", host_detect_local_cpu }, \ 1209 MCPU_TO_MARCH_SPEC_FUNCTIONS 1210 1211 # define MCPU_MTUNE_NATIVE_SPECS \ 1212 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 1213 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 1214 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 1215 #else 1216 # define MCPU_MTUNE_NATIVE_SPECS "" 1217 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS 1218 #endif 1219 1220 #define ASM_CPU_SPEC \ 1221 MCPU_TO_MARCH_SPEC 1222 1223 #define EXTRA_SPECS \ 1224 { "asm_cpu_spec", ASM_CPU_SPEC } 1225 1226 #define ASM_OUTPUT_POOL_EPILOGUE aarch64_asm_output_pool_epilogue 1227 1228 /* This type is the user-visible __fp16, and a pointer to that type. We 1229 need it in many places in the backend. Defined in aarch64-builtins.c. */ 1230 extern tree aarch64_fp16_type_node; 1231 extern tree aarch64_fp16_ptr_type_node; 1232 1233 /* This type is the user-visible __bf16, and a pointer to that type. Defined 1234 in aarch64-builtins.c. */ 1235 extern tree aarch64_bf16_type_node; 1236 extern tree aarch64_bf16_ptr_type_node; 1237 1238 /* The generic unwind code in libgcc does not initialize the frame pointer. 1239 So in order to unwind a function using a frame pointer, the very first 1240 function that is unwound must save the frame pointer. That way the frame 1241 pointer is restored and its value is now valid - otherwise _Unwind_GetGR 1242 crashes. Libgcc can now be safely built with -fomit-frame-pointer. */ 1243 #define LIBGCC2_UNWIND_ATTRIBUTE \ 1244 __attribute__((optimize ("no-omit-frame-pointer"))) 1245 1246 #ifndef USED_FOR_TARGET 1247 extern poly_uint16 aarch64_sve_vg; 1248 1249 /* The number of bits and bytes in an SVE vector. */ 1250 #define BITS_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 64)) 1251 #define BYTES_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 8)) 1252 1253 /* The number of bits and bytes in an SVE predicate. */ 1254 #define BITS_PER_SVE_PRED BYTES_PER_SVE_VECTOR 1255 #define BYTES_PER_SVE_PRED aarch64_sve_vg 1256 1257 /* The SVE mode for a vector of bytes. */ 1258 #define SVE_BYTE_MODE VNx16QImode 1259 1260 /* The maximum number of bytes in a fixed-size vector. This is 256 bytes 1261 (for -msve-vector-bits=2048) multiplied by the maximum number of 1262 vectors in a structure mode (4). 1263 1264 This limit must not be used for variable-size vectors, since 1265 VL-agnostic code must work with arbitary vector lengths. */ 1266 #define MAX_COMPILE_TIME_VEC_BYTES (256 * 4) 1267 #endif 1268 1269 #define REGMODE_NATURAL_SIZE(MODE) aarch64_regmode_natural_size (MODE) 1270 1271 /* Allocate a minimum of STACK_CLASH_MIN_BYTES_OUTGOING_ARGS bytes for the 1272 outgoing arguments if stack clash protection is enabled. This is essential 1273 as the extra arg space allows us to skip a check in alloca. */ 1274 #undef STACK_DYNAMIC_OFFSET 1275 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1276 ((flag_stack_clash_protection \ 1277 && cfun->calls_alloca \ 1278 && known_lt (crtl->outgoing_args_size, \ 1279 STACK_CLASH_MIN_BYTES_OUTGOING_ARGS)) \ 1280 ? ROUND_UP (STACK_CLASH_MIN_BYTES_OUTGOING_ARGS, \ 1281 STACK_BOUNDARY / BITS_PER_UNIT) \ 1282 : (crtl->outgoing_args_size + STACK_POINTER_OFFSET)) 1283 1284 #endif /* GCC_AARCH64_H */ 1285