xref: /netbsd-src/sys/dev/pci/machfb.c (revision 13d4bb4cc874de96add7fc4227d38a1d656b03d1)
1 /*	$NetBSD: machfb.c,v 1.107 2022/09/25 17:52:25 thorpej Exp $	*/
2 
3 /*
4  * Copyright (c) 2002 Bang Jun-Young
5  * Copyright (c) 2005, 2006, 2007 Michael Lorenz
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. The name of the author may not be used to endorse or promote products
17  *    derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 /*
32  * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide.
33  */
34 
35 #include <sys/cdefs.h>
36 __KERNEL_RCSID(0,
37 	"$NetBSD: machfb.c,v 1.107 2022/09/25 17:52:25 thorpej Exp $");
38 
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/device.h>
43 #include <sys/callout.h>
44 #include <sys/lwp.h>
45 #include <sys/kauth.h>
46 
47 #include <dev/videomode/videomode.h>
48 #include <dev/videomode/edidvar.h>
49 
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pcidevs.h>
53 #include <dev/pci/pciio.h>
54 #include <dev/pci/machfbreg.h>
55 
56 #include <dev/wscons/wsdisplayvar.h>
57 
58 #include <dev/wscons/wsconsio.h>
59 #include <dev/wsfont/wsfont.h>
60 #include <dev/rasops/rasops.h>
61 #include <dev/pci/wsdisplay_pci.h>
62 
63 #include <dev/wscons/wsdisplay_vconsvar.h>
64 #include <dev/wscons/wsdisplay_glyphcachevar.h>
65 
66 #include "opt_wsemul.h"
67 #include "opt_machfb.h"
68 #include "opt_glyphcache.h"
69 
70 #ifdef MACHFB_DEBUG
71 #define DPRINTF printf
72 #else
73 #define DPRINTF while (0) printf
74 #endif
75 
76 #define MACH64_REG_SIZE		0x800
77 #define MACH64_REG_OFF		0x7ff800
78 
79 #define	NBARS		3	/* number of Mach64 PCI BARs */
80 
81 struct vga_bar {
82 	bus_addr_t vb_base;
83 	bus_size_t vb_size;
84 	pcireg_t vb_type;
85 	int vb_flags;
86 };
87 
88 struct mach64_softc {
89 	device_t sc_dev;
90 	pci_chipset_tag_t sc_pc;
91 	pcitag_t sc_pcitag;
92 
93 	struct vga_bar sc_bars[NBARS];
94 	struct vga_bar sc_rom;
95 
96 #define sc_aperbase 	sc_bars[0].vb_base
97 #define sc_apersize	sc_bars[0].vb_size
98 
99 #define sc_iobase	sc_bars[1].vb_base
100 #define sc_iosize	sc_bars[1].vb_size
101 
102 #define sc_regbase	sc_bars[2].vb_base
103 #define sc_regsize	sc_bars[2].vb_size
104 
105 	bus_space_tag_t sc_regt;
106 	bus_space_tag_t sc_memt;
107 	bus_space_tag_t sc_iot;
108 	bus_space_handle_t sc_regh;
109 	bus_space_handle_t sc_memh;
110 #if 0
111 	void *sc_aperture;		/* mapped aperture vaddr */
112 	void *sc_registers;		/* mapped registers vaddr */
113 #endif
114 	uint32_t sc_nbus, sc_ndev, sc_nfunc;
115 	size_t memsize;
116 	int memtype;
117 
118 	int sc_mode;
119 	int sc_bg;
120 	int sc_locked;
121 
122 	int has_dsp;
123 	int bits_per_pixel;
124 	int max_x;
125 	int max_y;
126 	int virt_x;
127 	int virt_y;
128 	int stride;	/* in pixels */
129 	int color_depth;
130 
131 	int mem_freq;
132 	int ramdac_freq;
133 	int ref_freq;
134 	int vclk_freq;
135 
136 	int ref_div;
137 	int log2_vclk_post_div;
138 	int vclk_post_div;
139 	int vclk_fb_div;
140 	int mclk_post_div;
141 	int mclk_fb_div;
142 	int sc_clock;	/* which clock to use */
143 	int minref, m;
144 
145 	struct videomode *sc_my_mode;
146 	int sc_edid_size;
147 	uint8_t sc_edid_data[1024];
148     	struct edid_info sc_ei;
149     	int sc_setmode;
150     	int sc_gen_cntl;
151 
152 	u_char sc_cmap_red[256];
153 	u_char sc_cmap_green[256];
154 	u_char sc_cmap_blue[256];
155 	int sc_dacw, sc_blanked, sc_console;
156 	struct vcons_data vd;
157 	struct wsdisplay_accessops sc_accessops;
158 	glyphcache sc_gc;
159 };
160 
161 struct mach64_crtcregs {
162 	uint32_t h_total_disp;
163 	uint32_t h_sync_strt_wid;
164 	uint32_t v_total_disp;
165 	uint32_t v_sync_strt_wid;
166 	uint32_t gen_cntl;
167 	uint32_t clock_cntl;
168 	uint32_t color_depth;
169 	uint32_t dot_clock;
170 };
171 
172 static struct {
173 	uint16_t chip_id;
174 	uint32_t ramdac_freq;
175 } const mach64_info[] = {
176 	{ PCI_PRODUCT_ATI_MACH64_GX, 135000 },
177 	{ PCI_PRODUCT_ATI_MACH64_CX, 135000 },
178 	{ PCI_PRODUCT_ATI_MACH64_CT, 135000 },
179 	{ PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 },
180 	{ PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 },
181 	{ PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 },
182 	{ PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 },
183 	{ PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 },
184 	{ PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 },
185 	{ PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 },
186 	{ PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 },
187 	{ PCI_PRODUCT_ATI_RAGE_II, 135000 },
188 	{ PCI_PRODUCT_ATI_RAGE_IIP, 200000 },
189 	{ PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 },
190 	{ PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 },
191 	{ PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 },
192 #if 0
193 	{ PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 },
194 	{ PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 },
195 	{ PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 },
196 #endif
197 	{ PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI, 230000 },
198 	{ PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 },
199 	{ PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 },
200 	{ PCI_PRODUCT_ATI_RAGE_LT, 230000 },
201 	{ PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 },
202 	{ PCI_PRODUCT_ATI_MACH64_VT, 170000 },
203 	{ PCI_PRODUCT_ATI_MACH64_VTB, 200000 },
204 	{ PCI_PRODUCT_ATI_MACH64_VT4, 230000 }
205 };
206 
207 static int mach64_chip_id, mach64_chip_rev;
208 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
209 
210 static const char *mach64_gx_memtype_names[] = {
211 	"DRAM", "VRAM", "VRAM", "DRAM",
212 	"DRAM", "VRAM", "VRAM", "(unknown type)"
213 };
214 
215 static const char *mach64_memtype_names[] = {
216 	"(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM",
217 	"(unknown type)"
218 };
219 
220 extern const u_char rasops_cmap[768];
221 
222 static int	mach64_match(device_t, cfdata_t, void *);
223 static void	mach64_attach(device_t, device_t, void *);
224 
225 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match,
226     mach64_attach, NULL, NULL);
227 
228 static void	mach64_init(struct mach64_softc *);
229 static int	mach64_get_memsize(struct mach64_softc *);
230 static int	mach64_get_max_ramdac(struct mach64_softc *);
231 static int	mach64_ref_freq(void);
232 
233 #ifdef MACHFB_DEBUG
234 static void	mach64_get_mode(struct mach64_softc *, struct videomode *);
235 static void	mach64_print_reg(struct mach64_softc *);
236 #endif
237 
238 static int	mach64_calc_crtcregs(struct mach64_softc *,
239 				     struct mach64_crtcregs *,
240 				     struct videomode *);
241 static void	mach64_set_crtcregs(struct mach64_softc *,
242 				    struct mach64_crtcregs *);
243 
244 static int	mach64_modeswitch(struct mach64_softc *, struct videomode *);
245 static void	mach64_set_dsp(struct mach64_softc *);
246 static void	mach64_set_pll(struct mach64_softc *, int);
247 static void	mach64_reset_engine(struct mach64_softc *);
248 static void	mach64_init_engine(struct mach64_softc *);
249 #if 0
250 static void	mach64_adjust_frame(struct mach64_softc *, int, int);
251 #endif
252 static void	mach64_init_lut(struct mach64_softc *);
253 
254 static void	mach64_init_screen(void *, struct vcons_screen *, int, long *);
255 static int	mach64_is_console(struct mach64_softc *);
256 
257 static void	mach64_cursor(void *, int, int, int);
258 #if 0
259 static int	mach64_mapchar(void *, int, u_int *);
260 #endif
261 static void	mach64_putchar_mono(void *, int, int, u_int, long);
262 static void	mach64_putchar_aa8(void *, int, int, u_int, long);
263 static void	mach64_copycols(void *, int, int, int, int);
264 static void	mach64_erasecols(void *, int, int, int, long);
265 static void	mach64_copyrows(void *, int, int, int);
266 static void	mach64_eraserows(void *, int, int, long);
267 static void 	mach64_clearscreen(struct mach64_softc *);
268 
269 static int	mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *);
270 static int	mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *);
271 static int	mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t,
272 				 uint8_t, uint8_t);
273 static void	mach64_bitblt(void *, int, int, int, int, int, int, int);
274 static void	mach64_rectfill(struct mach64_softc *, int, int, int, int, int);
275 static void	mach64_setup_mono(struct mach64_softc *, int, int, int, int,
276 				  uint32_t, uint32_t);
277 static void	mach64_feed_bytes(struct mach64_softc *, int, uint8_t *);
278 #if 0
279 static void	mach64_showpal(struct mach64_softc *);
280 #endif
281 
282 static void	machfb_blank(struct mach64_softc *, int);
283 static int	machfb_drm_print(void *, const char *);
284 
285 static struct wsscreen_descr mach64_defaultscreen = {
286 	"default",
287 	80, 30,
288 	NULL,
289 	8, 16,
290 	WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE
291 	 | WSSCREEN_RESIZE ,
292 	NULL
293 };
294 
295 static const struct wsscreen_descr *_mach64_scrlist[] = {
296 	&mach64_defaultscreen,
297 };
298 
299 static struct wsscreen_list mach64_screenlist = {
300 	__arraycount(_mach64_scrlist),
301 	_mach64_scrlist
302 };
303 
304 static int	mach64_ioctl(void *, void *, u_long, void *, int,
305 		             struct lwp *);
306 static paddr_t	mach64_mmap(void *, void *, off_t, int);
307 
308 static struct vcons_screen mach64_console_screen;
309 
310 /*
311  * Inline functions for getting access to register aperture.
312  */
313 
314 static inline uint32_t
regr(struct mach64_softc * sc,uint32_t index)315 regr(struct mach64_softc *sc, uint32_t index)
316 {
317 	return bus_space_read_4(sc->sc_regt, sc->sc_regh, index + 0x400);
318 }
319 
320 static inline uint8_t
regrb(struct mach64_softc * sc,uint32_t index)321 regrb(struct mach64_softc *sc, uint32_t index)
322 {
323 	return bus_space_read_1(sc->sc_regt, sc->sc_regh, index + 0x400);
324 }
325 
326 static inline void
regw(struct mach64_softc * sc,uint32_t index,uint32_t data)327 regw(struct mach64_softc *sc, uint32_t index, uint32_t data)
328 {
329 	bus_space_write_4(sc->sc_regt, sc->sc_regh, index + 0x400, data);
330 	bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4,
331 	    BUS_SPACE_BARRIER_WRITE);
332 }
333 
334 static inline void
regws(struct mach64_softc * sc,uint32_t index,uint32_t data)335 regws(struct mach64_softc *sc, uint32_t index, uint32_t data)
336 {
337 	bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, index + 0x400, data);
338 	bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 4,
339 	    BUS_SPACE_BARRIER_WRITE);
340 }
341 
342 static inline void
regwb(struct mach64_softc * sc,uint32_t index,uint8_t data)343 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data)
344 {
345 	bus_space_write_1(sc->sc_regt, sc->sc_regh, index + 0x400, data);
346 	bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 1,
347 	    BUS_SPACE_BARRIER_WRITE);
348 }
349 
350 static inline void
regwb_pll(struct mach64_softc * sc,uint32_t index,uint8_t data)351 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data)
352 {
353 	uint32_t reg;
354 
355 	reg = regr(sc, CLOCK_CNTL);
356 	reg |= PLL_WR_EN;
357 	regw(sc, CLOCK_CNTL, reg);
358 	reg &= ~(PLL_ADDR | PLL_DATA);
359 	reg |= (index & 0x3f) << PLL_ADDR_SHIFT;
360 	reg |= data << PLL_DATA_SHIFT;
361 	reg |= CLOCK_STROBE;
362 	regw(sc, CLOCK_CNTL, reg);
363 	reg &= ~PLL_WR_EN;
364 	regw(sc, CLOCK_CNTL, reg);
365 }
366 
367 static inline uint8_t
regrb_pll(struct mach64_softc * sc,uint32_t index)368 regrb_pll(struct mach64_softc *sc, uint32_t index)
369 {
370 
371 	regwb(sc, CLOCK_CNTL + 1, index << 2);
372 	return regrb(sc, CLOCK_CNTL + 2);
373 }
374 
375 static inline void
wait_for_fifo(struct mach64_softc * sc,uint8_t v)376 wait_for_fifo(struct mach64_softc *sc, uint8_t v)
377 {
378 	while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v))
379 		continue;
380 }
381 
382 static inline void
wait_for_idle(struct mach64_softc * sc)383 wait_for_idle(struct mach64_softc *sc)
384 {
385 	wait_for_fifo(sc, 16);
386 	while ((regr(sc, GUI_STAT) & 1) != 0)
387 		continue;
388 }
389 
390 static int
mach64_match(device_t parent,cfdata_t match,void * aux)391 mach64_match(device_t parent, cfdata_t match, void *aux)
392 {
393 	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
394 	int i;
395 
396 	if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY ||
397 	    PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA)
398 		return 0;
399 
400 	for (i = 0; i < __arraycount(mach64_info); i++)
401 		if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) {
402 			mach64_chip_id = PCI_PRODUCT(pa->pa_id);
403 			mach64_chip_rev = PCI_REVISION(pa->pa_class);
404 			return 100;
405 		}
406 
407 	return 0;
408 }
409 
410 static void
mach64_attach(device_t parent,device_t self,void * aux)411 mach64_attach(device_t parent, device_t self, void *aux)
412 {
413 	struct mach64_softc *sc = device_private(self);
414 	struct pci_attach_args *pa = aux;
415 	struct rasops_info *ri;
416 	const char *mptr = NULL;
417 	prop_data_t edid_data;
418 	const struct videomode *mode = NULL;
419 	int bar, id, expected_id;
420 	int is_gx;
421 	const char **memtype_names;
422 	struct wsemuldisplaydev_attach_args aa;
423 	long defattr;
424 	int width = 1024, height = 768;
425 	pcireg_t screg;
426 	uint32_t reg;
427 	const pcireg_t enables = PCI_COMMAND_MEM_ENABLE;
428 	int use_mmio = FALSE;
429 
430 	sc->sc_dev = self;
431 	sc->sc_pc = pa->pa_pc;
432 	sc->sc_pcitag = pa->pa_tag;
433 	sc->sc_dacw = -1;
434 	sc->sc_mode = WSDISPLAYIO_MODE_EMUL;
435 	sc->sc_nbus = pa->pa_bus;
436 	sc->sc_ndev = pa->pa_device;
437 	sc->sc_nfunc = pa->pa_function;
438 	sc->sc_locked = 0;
439 	sc->sc_iot = pa->pa_iot;
440 	sc->sc_accessops.ioctl = mach64_ioctl;
441 	sc->sc_accessops.mmap = mach64_mmap;
442 	sc->sc_setmode = 0;
443 
444 	pci_aprint_devinfo(pa, "Graphics processor");
445 #ifdef MACHFB_DEBUG
446 	printf(prop_dictionary_externalize(device_properties(self)));
447 #endif
448 
449 	/* enable memory access */
450 	screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
451 	if ((screg & enables) != enables) {
452 		screg |= enables;
453 		pci_conf_write(sc->sc_pc, sc->sc_pcitag,
454 		    PCI_COMMAND_STATUS_REG, screg);
455 	}
456 	for (bar = 0; bar < NBARS; bar++) {
457 		reg = PCI_MAPREG_START + (bar * 4);
458 		sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc,
459 		    sc->sc_pcitag, reg);
460 		(void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg,
461 		    sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base,
462 		    &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags);
463 	}
464 	aprint_debug_dev(sc->sc_dev, "aperture size %08x\n",
465 	    (uint32_t)sc->sc_apersize);
466 
467 	sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM;
468 	pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM,
469 		    sc->sc_rom.vb_type, &sc->sc_rom.vb_base,
470 		    &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags);
471 	sc->sc_memt = pa->pa_memt;
472 
473 	/* use MMIO register aperture if available */
474 	if ((sc->sc_regbase != 0) && (sc->sc_regbase != 0xffffffff)) {
475 		if (pci_mapreg_map(pa, MACH64_BAR_MMIO,  PCI_MAPREG_TYPE_MEM,
476 		    0, &sc->sc_regt, &sc->sc_regh, &sc->sc_regbase,
477 		    &sc->sc_regsize) == 0) {
478 
479 			/*
480 			 * the MMIO aperture maps both 1KB register blocks, but
481 			 * all register offsets are relative to the 2nd one so
482 			 * for now fix this up in MACH64_REG_OFF and the access
483 			 * functions
484 			 */
485 			aprint_normal_dev(sc->sc_dev, "using MMIO aperture\n");
486 			use_mmio = TRUE;
487 		}
488 	}
489 	if (!use_mmio) {
490 		if (bus_space_map(sc->sc_memt, sc->sc_aperbase,
491 		    sc->sc_apersize, BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) {
492 			panic("%s: failed to map aperture",
493 			    device_xname(sc->sc_dev));
494 		}
495 
496 		sc->sc_regt = sc->sc_memt;
497 		bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF,
498 		    MACH64_REG_SIZE, &sc->sc_regh);
499 	}
500 
501 	mach64_init(sc);
502 
503 	aprint_normal_dev(sc->sc_dev,
504 	    "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n",
505 	    (u_int)(sc->sc_apersize / (1024 * 1024)),
506 	    (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024),
507 	    (u_int)sc->sc_regbase);
508 
509 	printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev),
510 	    (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base);
511 #ifdef MACHFB_DEBUG
512 	mach64_get_mode(sc, NULL);
513 	mach64_print_reg(sc);
514 #endif
515 
516 	prop_dictionary_get_uint32(device_properties(self), "width", &width);
517 	prop_dictionary_get_uint32(device_properties(self), "height", &height);
518 
519 	default_mode.hdisplay = width;
520 	default_mode.vdisplay = height;
521 
522 	prop_dictionary_get_string(device_properties(sc->sc_dev),
523 	    "videomode", &mptr);
524 
525 	memset(&sc->sc_ei, 0, sizeof(sc->sc_ei));
526 	if (mptr == NULL &&
527 	    (edid_data = prop_dictionary_get(device_properties(self), "EDID"))
528 	    != NULL) {
529 
530 		sc->sc_edid_size = uimin(1024, prop_data_size(edid_data));
531 		memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data));
532 		memcpy(sc->sc_edid_data, prop_data_value(edid_data),
533 		    sc->sc_edid_size);
534 
535 		edid_parse(sc->sc_edid_data, &sc->sc_ei);
536 
537 #ifdef MACHFB_DEBUG
538 		edid_print(&sc->sc_ei);
539 #endif
540 	}
541 	is_gx = 0;
542 	switch(mach64_chip_id) {
543 		case PCI_PRODUCT_ATI_MACH64_GX:
544 		case PCI_PRODUCT_ATI_MACH64_CX:
545 			is_gx = 1;
546 			/* FALLTHROUGH */
547 		case PCI_PRODUCT_ATI_MACH64_CT:
548 			sc->has_dsp = 0;
549 			break;
550 		case PCI_PRODUCT_ATI_MACH64_VT:
551 		case PCI_PRODUCT_ATI_RAGE_II:
552 			if((mach64_chip_rev & 0x07) == 0) {
553 				sc->has_dsp = 0;
554 				break;
555 			}
556 			/* FALLTHROUGH */
557 		default:
558 			sc->has_dsp = 1;
559 	}
560 
561 	memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names;
562 
563 	sc->memsize = mach64_get_memsize(sc);
564 
565 	if(is_gx)
566 		sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07;
567 	else
568 		sc->memtype = regr(sc, CONFIG_STAT0) & 0x07;
569 
570 	sc->ref_freq = mach64_ref_freq();
571 
572 	reg = regr(sc, CLOCK_CNTL);
573 	sc->sc_clock = reg & 3;
574 	DPRINTF("using clock %d\n", sc->sc_clock);
575 
576 	DPRINTF("ref_freq: %d\n", sc->ref_freq);
577 	sc->ref_div = regrb_pll(sc, PLL_REF_DIV);
578 	DPRINTF("ref_div: %d\n", sc->ref_div);
579 	sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV);
580 	DPRINTF("mclk_fb_div: %d\n", sc->mclk_fb_div);
581 	sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) /
582 	    (sc->ref_div * 2);
583 	sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) /
584 	    (sc->mem_freq * sc->ref_div);
585 	sc->ramdac_freq = mach64_get_max_ramdac(sc);
586 	{
587 		sc->minref = sc->ramdac_freq / 510;
588 		sc->m = sc->ref_freq / sc->minref;
589 		DPRINTF("minref: %d m: %d\n", sc->minref, sc->m);
590 	}
591 	aprint_normal_dev(sc->sc_dev,
592 	    "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n",
593 	    (u_long)sc->memsize,
594 	    memtype_names[sc->memtype],
595 	    sc->mem_freq / 1000, sc->mem_freq % 1000,
596 	    sc->ramdac_freq / 1000);
597 
598 	id = regr(sc, CONFIG_CHIP_ID) & 0xffff;
599 	switch(mach64_chip_id) {
600 		case PCI_PRODUCT_ATI_MACH64_GX:
601 			expected_id = 0x00d7;
602 			break;
603 		case PCI_PRODUCT_ATI_MACH64_CX:
604 			expected_id = 0x0057;
605 			break;
606 		default:
607 			/* Most chip IDs match their PCI product ID. */
608 			expected_id = mach64_chip_id;
609 	}
610 
611 	if (id != expected_id) {
612 		aprint_error_dev(sc->sc_dev,
613 		    "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id);
614 		return;
615 	}
616 
617 	sc->sc_console = mach64_is_console(sc);
618 	sc->sc_gen_cntl = regr(sc, CRTC_GEN_CNTL);
619 	aprint_debug("gen_cntl: %08x\n", sc->sc_gen_cntl);
620 	sc->sc_gen_cntl &= CRTC_CSYNC_EN;
621 	aprint_normal_dev(sc->sc_dev, "found composite sync %s\n",
622 	    sc->sc_gen_cntl ? "enabled" : "disabled");
623 
624 #define MODE_IS_VALID(m) ((sc->ramdac_freq >= (m)->dot_clock) && \
625 			  ((m)->hdisplay <= 1280))
626 
627 	/* no mode setting support on ancient chips with external clocks */
628 	sc->sc_setmode = 0;
629 	if (!is_gx) {
630 		/*
631 		 * Now pick a mode.
632 		 */
633 		if ((sc->sc_ei.edid_preferred_mode != NULL)) {
634 			struct videomode *m = sc->sc_ei.edid_preferred_mode;
635 			if (MODE_IS_VALID(m)) {
636 				memcpy(&default_mode, m,
637 				    sizeof(struct videomode));
638 				sc->sc_setmode = 1;
639 			} else {
640 				aprint_normal_dev(sc->sc_dev,
641 				    "unable to use EDID preferred mode "
642 				    "(%d x %d)\n", m->hdisplay, m->vdisplay);
643 			}
644 		}
645 		/*
646 		 * if we can't use the preferred mode go look for the
647 		 * best one we can support
648 		 */
649 		if (sc->sc_setmode == 0) {
650 			struct videomode *m = sc->sc_ei.edid_modes;
651 
652 			mode = NULL;
653 			sort_modes(sc->sc_ei.edid_modes,
654 			    &sc->sc_ei.edid_preferred_mode,
655 			    sc->sc_ei.edid_nmodes);
656 			for (int n = 0; n < sc->sc_ei.edid_nmodes; n++)
657 				if (MODE_IS_VALID(&m[n])) {
658 					mode = &m[n];
659 					break;
660 				}
661 			if (mode != NULL) {
662 				memcpy(&default_mode, mode,
663 				    sizeof(struct videomode));
664 				sc->sc_setmode = 1;
665 			}
666 		}
667 	}
668 
669 	/* make sure my_mode points at something sensible if the above fails */
670 	if (default_mode.dot_clock == 0) {
671 		sc->sc_setmode = 0;
672 		mode = pick_mode_by_ref(width, height, 60);
673 		if (mode != NULL) {
674 			memcpy(&default_mode, mode, sizeof(default_mode));
675 		} else if ((width > 0) && (height > 0)) {
676 			default_mode.hdisplay = width;
677 			default_mode.vdisplay = height;
678 		} else {
679 			/*
680 			 * if we end up here we're probably dealing with
681 			 * uninitialized hardware - try to set 1024x768@60 and
682 			 * hope for the best...
683 			 */
684 			mode = pick_mode_by_ref(1024, 768, 60);
685 			if (mode == NULL) return;
686 			memcpy(&default_mode, mode, sizeof(default_mode));
687 			if (!is_gx) sc->sc_setmode = 1;
688 		}
689 	}
690 
691 	sc->sc_my_mode = &default_mode;
692 
693 	if ((width == sc->sc_my_mode->hdisplay) &&
694 	    (height == sc->sc_my_mode->vdisplay))
695 		sc->sc_setmode = 0;
696 
697 	sc->bits_per_pixel = 8;
698 	sc->virt_x = sc->sc_my_mode->hdisplay;
699 	sc->virt_y = sc->sc_my_mode->vdisplay;
700 	sc->stride = (sc->virt_x + 7) & ~7;	/* hw needs multiples of 8 */
701 	sc->max_x = sc->virt_x - 1;
702 	sc->max_y = (sc->memsize * 1024) /
703 	    (sc->stride * (sc->bits_per_pixel / 8)) - 1;
704 
705 	sc->color_depth = CRTC_PIX_WIDTH_8BPP;
706 
707 	mach64_init_engine(sc);
708 
709 	if (sc->sc_setmode)
710 		mach64_modeswitch(sc, sc->sc_my_mode);
711 
712 	aprint_normal_dev(sc->sc_dev,
713 	    "initial resolution %dx%d at %d bpp\n",
714 	    sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay,
715 	    sc->bits_per_pixel);
716 
717 	wsfont_init();
718 
719 #ifdef GLYPHCACHE_DEBUG
720 	/* shrink the screen so we can see part of the glyph cache */
721 	sc->sc_my_mode->vdisplay -= 200;
722 #endif
723 
724 	vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops);
725 	sc->vd.init_screen = mach64_init_screen;
726 	sc->vd.show_screen_cookie = &sc->sc_gc;
727 	sc->vd.show_screen_cb = glyphcache_adapt;
728 
729 	sc->sc_gc.gc_bitblt = mach64_bitblt;
730 	sc->sc_gc.gc_blitcookie = sc;
731 	sc->sc_gc.gc_rop = MIX_SRC;
732 
733 	ri = &mach64_console_screen.scr_ri;
734 	if (sc->sc_console) {
735 
736 		vcons_init_screen(&sc->vd, &mach64_console_screen, 1,
737 		    &defattr);
738 		mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC;
739 
740 		mach64_defaultscreen.textops = &ri->ri_ops;
741 		mach64_defaultscreen.capabilities = ri->ri_caps;
742 		mach64_defaultscreen.nrows = ri->ri_rows;
743 		mach64_defaultscreen.ncols = ri->ri_cols;
744 		glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5,
745 		    ((sc->memsize * 1024) / sc->stride) -
746 		      sc->sc_my_mode->vdisplay - 5,
747 		    sc->stride,
748 		    ri->ri_font->fontwidth,
749 		    ri->ri_font->fontheight,
750 		    defattr);
751 		wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr);
752 	} else {
753 		/*
754 		 * since we're not the console we can postpone the rest
755 		 * until someone actually allocates a screen for us
756 		 */
757 		if (mach64_console_screen.scr_ri.ri_rows == 0) {
758 			/* do some minimal setup to avoid weirdnesses later */
759 			vcons_init_screen(&sc->vd, &mach64_console_screen, 1,
760 			    &defattr);
761 		} else
762 			(*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr);
763 
764 		glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5,
765 		    ((sc->memsize * 1024) / sc->stride) -
766 		      sc->sc_my_mode->vdisplay - 5,
767 		    sc->stride,
768 		    ri->ri_font->fontwidth,
769 		    ri->ri_font->fontheight,
770 		    defattr);
771 	}
772 
773 	sc->sc_bg = mach64_console_screen.scr_ri.ri_devcmap[WS_DEFAULT_BG];
774 	mach64_clearscreen(sc);
775 	mach64_init_lut(sc);
776 
777 	if (sc->sc_console)
778 		vcons_replay_msgbuf(&mach64_console_screen);
779 
780 	machfb_blank(sc, 0);	/* unblank the screen */
781 
782 	aa.console = sc->sc_console;
783 	aa.scrdata = &mach64_screenlist;
784 	aa.accessops = &sc->sc_accessops;
785 	aa.accesscookie = &sc->vd;
786 
787 	config_found(self, &aa, wsemuldisplaydevprint,
788 	    CFARGS(.iattr = "wsemuldisplaydev"));
789 #if 0
790 	/* XXX
791 	 * turns out some firmware doesn't turn these back on when needed
792 	 * so we need to turn them off only when mapping vram in
793 	 * WSDISPLAYIO_MODE_DUMB would overlap ( unlikely but far from
794 	 * impossible )
795 	 */
796 	if (use_mmio) {
797 		/*
798 		 * Now that we took over, turn off the aperture registers if we
799 		 * don't use them. Can't do this earlier since on some hardware
800 		 * we use firmware calls as early console output which may in
801 		 * turn try to access these registers.
802 		 */
803 		reg = regr(sc, BUS_CNTL);
804 		aprint_debug_dev(sc->sc_dev, "BUS_CNTL: %08x\n", reg);
805 		reg |= BUS_APER_REG_DIS;
806 		regw(sc, BUS_CNTL, reg);
807 	}
808 #endif
809 	config_found(self, aux, machfb_drm_print,
810 	    CFARGS(.iattr = "drm"));
811 }
812 
813 static int
machfb_drm_print(void * aux,const char * pnp)814 machfb_drm_print(void *aux, const char *pnp)
815 {
816 	if (pnp)
817 		aprint_normal("direct rendering for %s", pnp);
818 	return (UNSUPP);
819 }
820 
821 static void
mach64_init_screen(void * cookie,struct vcons_screen * scr,int existing,long * defattr)822 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing,
823     long *defattr)
824 {
825 	struct mach64_softc *sc = cookie;
826 	struct rasops_info *ri = &scr->scr_ri;
827 
828 	ri->ri_depth = sc->bits_per_pixel;
829 	ri->ri_width = sc->sc_my_mode->hdisplay;
830 	ri->ri_height = sc->sc_my_mode->vdisplay;
831 	ri->ri_stride = sc->stride;
832 	ri->ri_flg = RI_CENTER | RI_FULLCLEAR;
833 	if (ri->ri_depth == 8)
834 		ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA |
835 			      RI_PREFER_ALPHA;
836 
837 #ifdef VCONS_DRAW_INTR
838 	scr->scr_flags |= VCONS_DONT_READ;
839 #endif
840 	scr->scr_flags |= VCONS_LOADFONT;
841 
842 	rasops_init(ri, 0, 0);
843 	ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE |
844 		      WSSCREEN_RESIZE;
845 	rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight,
846 		    sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth);
847 
848 	/* enable acceleration */
849 	ri->ri_hw = scr;
850 	ri->ri_ops.copyrows = mach64_copyrows;
851 	ri->ri_ops.copycols = mach64_copycols;
852 	ri->ri_ops.eraserows = mach64_eraserows;
853 	ri->ri_ops.erasecols = mach64_erasecols;
854 	ri->ri_ops.cursor = mach64_cursor;
855 	if (FONT_IS_ALPHA(ri->ri_font)) {
856 		ri->ri_ops.putchar = mach64_putchar_aa8;
857 	} else
858 		ri->ri_ops.putchar = mach64_putchar_mono;
859 }
860 
861 static void
mach64_init(struct mach64_softc * sc)862 mach64_init(struct mach64_softc *sc)
863 {
864 	sc->sc_blanked = 0;
865 }
866 
867 static int
mach64_get_memsize(struct mach64_softc * sc)868 mach64_get_memsize(struct mach64_softc *sc)
869 {
870 	int tmp, memsize;
871 	int mem_tab[] = {
872 		512, 1024, 2048, 4096, 6144, 8192, 12288, 16384
873 	};
874 	tmp = regr(sc, MEM_CNTL);
875 #ifdef DIAGNOSTIC
876 	aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp);
877 #endif
878 	if (sc->has_dsp) {
879 		tmp &= 0x0000000f;
880 		if (tmp < 8)
881 			memsize = (tmp + 1) * 512;
882 		else if (tmp < 12)
883 			memsize = (tmp - 3) * 1024;
884 		else
885 			memsize = (tmp - 7) * 2048;
886 	} else {
887 		memsize = mem_tab[tmp & 0x07];
888 	}
889 
890 	return memsize;
891 }
892 
893 static int
mach64_get_max_ramdac(struct mach64_softc * sc)894 mach64_get_max_ramdac(struct mach64_softc *sc)
895 {
896 	int i;
897 
898 	if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT ||
899 	     mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) &&
900 	     (mach64_chip_rev & 0x07))
901 		return 170000;
902 
903 	for (i = 0; i < __arraycount(mach64_info); i++)
904 		if (mach64_chip_id == mach64_info[i].chip_id)
905 			return mach64_info[i].ramdac_freq;
906 
907 	if (sc->bits_per_pixel == 8)
908 		return 135000;
909 	else
910 		return 80000;
911 }
912 
913 static int
mach64_ref_freq(void)914 mach64_ref_freq(void)
915 {
916 	/*
917 	 * There doesn't seem to be any way to calculate the reference
918 	 * frequency from known values
919 	 */
920 	if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) ||
921 	    ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) &&
922 	    (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI)))
923 		return 29498;
924 	else
925 		return 14318;
926 }
927 
928 #ifdef MACHFB_DEBUG
929 static void
mach64_get_mode(struct mach64_softc * sc,struct videomode * mode)930 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode)
931 {
932 	int htotal, hdisplay, hsync_start, hsync_end;
933 	int vtotal, vdisplay, vsync_start, vsync_end;
934 	int clk_ctl, clock;
935 	int ref_freq, ref_div, vclk_post_div, vclk_fb_div;
936 	int nhsync, nvsync;
937 	int post_div, dot_clock, vrefresh, vrefresh2;
938 
939 	hdisplay = regr(sc, CRTC_H_TOTAL_DISP);
940 	hsync_end = regr(sc, CRTC_H_SYNC_STRT_WID);
941 	vdisplay = regr(sc, CRTC_V_TOTAL_DISP);
942 	vsync_end = regr(sc, CRTC_V_SYNC_STRT_WID);
943 	clk_ctl = regr(sc, CLOCK_CNTL);
944 	clock = clk_ctl & 3;
945 	ref_div = regrb_pll(sc, PLL_REF_DIV);
946 	vclk_post_div = regrb_pll(sc, VCLK_POST_DIV);
947 	vclk_fb_div = regrb_pll(sc, VCLK0_FB_DIV + clock);
948 	ref_freq = mach64_ref_freq();
949 
950 	htotal = ((hdisplay & 0x01ff) + 1) << 3;
951 	hdisplay = (((hdisplay & 0x1ff0000) >> 16) + 1) << 3;
952 	if (hsync_end & CRTC_HSYNC_NEG)
953 		nhsync = 1;
954 	else
955 		nhsync = 0;
956 	hsync_start = (((hsync_end & 0xff) + 1) << 3) +
957 	    ((hsync_end & 0x700) >> 8);
958 	hsync_end = (((hsync_end & 0x1f0000) >> 16) << 3) + hsync_start;
959 
960 	vtotal = (vdisplay & 0x07ff) + 1;
961 	vdisplay = ((vdisplay & 0x7ff0000) >> 16) + 1;
962 	if (vsync_end & CRTC_VSYNC_NEG)
963 		nvsync = 1;
964 	else
965 		nvsync = 0;
966 	vsync_start = (vsync_end & 0x07ff) + 1;
967 	vsync_end = ((vsync_end & 0x1f0000) >> 16) + vsync_start;
968 
969 	switch ((vclk_post_div >> (clock * 2)) & 3) {
970 		case 3:
971 			post_div = 8;
972 			break;
973 		case 2:
974 			post_div = 4;
975 			break;
976 		case 1:
977 			post_div = 2;
978 			break;
979 		default:
980 			post_div = 1;
981 			break;
982 	}
983 	dot_clock = (2 * ref_freq * vclk_fb_div) / (ref_div * post_div);
984 	vrefresh = (dot_clock * 1000) / (htotal * vtotal);
985 	vrefresh2 = ((dot_clock * 1000) - (vrefresh * htotal * vtotal)) * 100 /
986 	    (htotal * vtotal);
987 
988 	aprint_normal_dev(sc->sc_dev, "Video mode:\n");
989 	aprint_normal("\t%d" "x%d @ %d.%02dHz "
990 	    "(%d %d %d %d %d %d %d %cH %cV)\n",
991 	    hdisplay, vdisplay, vrefresh, vrefresh2, dot_clock,
992 	    hsync_start, hsync_end, htotal, vsync_start, vsync_end, vtotal,
993 	    nhsync == 1 ? '-' : '+', nvsync == 1 ? '-' : '+');
994 
995 	if (mode != NULL) {
996 		mode->dot_clock = dot_clock;
997 		mode->htotal = htotal;
998 		mode->hdisplay = hdisplay;
999 		mode->hsync_start = hsync_start;
1000 		mode->hsync_end = hsync_end;
1001 		mode->vtotal = vtotal;
1002 		mode->vdisplay = vdisplay;
1003 		mode->vsync_start = vsync_start;
1004 		mode->vsync_end = vsync_end;
1005 		mode->flags = 0;
1006 		if (nhsync)
1007 			mode->flags |= VID_NHSYNC;
1008 		if (nvsync)
1009 			mode->flags |= VID_NVSYNC;
1010 	}
1011 }
1012 
1013 static void
mach64_print_reg(struct mach64_softc * sc)1014 mach64_print_reg(struct mach64_softc *sc)
1015 {
1016 	struct reglist {
1017 		int offset;
1018 		const char *name;
1019 	};
1020 	static const struct reglist reglist_tab[] = {
1021 		{ 0x0000, "CRTC_H_TOTAL_DISP" },
1022 		{ 0x0004, "CRTC_H_SYNC_STRT_WID" },
1023 		{ 0x0008, "CRTC_V_TOTAL_DISP" },
1024 		{ 0x000C, "CRTC_V_SYNC_STRT_WID" },
1025 		{ 0x0010, "CRTC_VLINE_CRNT_VLINE" },
1026 		{ 0x0014, "CRTC_OFF_PITCH" },
1027 		{ 0x001C, "CRTC_GEN_CNTL" },
1028 		{ 0x0090, "CLOCK_CNTL" },
1029 		{ 0, NULL }
1030 	};
1031 	static const struct reglist plllist_tab[] = {
1032 		{ 0x02, "PLL_REF_DIV" },
1033 		{ 0x03, "PLL_GEN_CNTL" },
1034 		{ 0x04, "MCLK_FB_DIV" },
1035 		{ 0x05, "PLL_VCLK_CNTL" },
1036 		{ 0x06, "VCLK_POST_DIV" },
1037 		{ 0x07, "VCLK0_FB_DIV" },
1038 		{ 0x08, "VCLK1_FB_DIV" },
1039 		{ 0x09, "VCLK2_FB_DIV" },
1040 		{ 0x0A, "VCLK3_FB_DIV" },
1041 		{ 0x0B, "PLL_XCLK_CNTL" },
1042 		{ 0x10, "LVDSPLL_CNTL0" },
1043 		{ 0x11, "LVDSPLL_CNTL0" },
1044 		{ 0x19, "EXT_VPLL_CNTL" },
1045 		{ 0x1A, "EXT_VPLL_REF_DIV" },
1046 		{ 0x1B, "EXT_VPLL_FB_DIV" },
1047 		{ 0x1C, "EXT_VPLL_MSB" },
1048 		{ 0, NULL }
1049 	};
1050 	const struct reglist *r;
1051 
1052 	aprint_normal("CRTC registers\n");
1053 	for (r = reglist_tab; r->name != NULL; r++)
1054 		aprint_normal("0x%04x 0x%08x %s\n", r->offset,
1055 		    regr(sc, r->offset), r->name);
1056 	aprint_normal("PLL registers\n");
1057 	for (r = plllist_tab; r->name != NULL; r++)
1058 		aprint_normal("0x%02x 0x%02x %s\n", r->offset,
1059 		    regrb_pll(sc, r->offset), r->name);
1060 }
1061 #endif
1062 
1063 static int
mach64_calc_crtcregs(struct mach64_softc * sc,struct mach64_crtcregs * crtc,struct videomode * mode)1064 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc,
1065     struct videomode *mode)
1066 {
1067 
1068 	if (mode->dot_clock > sc->ramdac_freq)
1069 		/* Clock too high. */
1070 		return 1;
1071 
1072 	crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) |
1073 	    ((mode->htotal >> 3) - 1);
1074 	crtc->h_sync_strt_wid =
1075 	    (((mode->hsync_end - mode->hsync_start) >> 3) << 16) |
1076 	    ((mode->hsync_start >> 3) - 1) | ((mode->hsync_start & 7) << 8);
1077 
1078 	crtc->v_total_disp = ((mode->vdisplay - 1) << 16) |
1079 	    (mode->vtotal - 1);
1080 	crtc->v_sync_strt_wid =
1081 	    ((mode->vsync_end - mode->vsync_start) << 16) |
1082 	    (mode->vsync_start - 1);
1083 
1084 	if (mode->flags & VID_NVSYNC)
1085 		crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG;
1086 
1087 	switch (sc->bits_per_pixel) {
1088 	case 8:
1089 		crtc->color_depth = CRTC_PIX_WIDTH_8BPP;
1090 		break;
1091 	case 16:
1092 		crtc->color_depth = CRTC_PIX_WIDTH_16BPP;
1093 		break;
1094 	case 32:
1095 		crtc->color_depth = CRTC_PIX_WIDTH_32BPP;
1096 		break;
1097 	}
1098 
1099 	crtc->gen_cntl = 0;
1100 	if (mode->flags & VID_INTERLACE)
1101 		crtc->gen_cntl |= CRTC_INTERLACE_EN;
1102 
1103 	if (mode->flags & VID_CSYNC)
1104 		crtc->gen_cntl |= CRTC_CSYNC_EN;
1105 
1106 	crtc->dot_clock = mode->dot_clock;
1107 
1108 	return 0;
1109 }
1110 
1111 static void
mach64_set_crtcregs(struct mach64_softc * sc,struct mach64_crtcregs * crtc)1112 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc)
1113 {
1114 
1115 	mach64_set_pll(sc, crtc->dot_clock);
1116 
1117 	if (sc->has_dsp)
1118 		mach64_set_dsp(sc);
1119 
1120 	DPRINTF("\th total: 0x%08x  h sync: 0x%08x\n",
1121 	    crtc->h_total_disp, crtc->h_sync_strt_wid);
1122 	DPRINTF("\tv total: 0x%08x  v sync: 0x%08x\n",
1123 	    crtc->v_total_disp, crtc->v_sync_strt_wid);
1124 	regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp);
1125 	regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
1126 	regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp);
1127 	regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
1128 
1129 	regw(sc, CRTC_VLINE_CRNT_VLINE, 0);
1130 
1131 	regw(sc, CRTC_OFF_PITCH, (sc->stride >> 3) << 22);
1132 
1133 	regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth |
1134 	    sc->sc_gen_cntl | CRTC_EXT_DISP_EN | CRTC_EXT_EN);
1135 }
1136 
1137 static int
mach64_modeswitch(struct mach64_softc * sc,struct videomode * mode)1138 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode)
1139 {
1140 	struct mach64_crtcregs crtc;
1141 
1142 	memset(&crtc, 0, sizeof crtc);	/* XXX gcc */
1143 
1144 	if (mach64_calc_crtcregs(sc, &crtc, mode))
1145 		return 1;
1146 	aprint_debug("crtc dot clock: %d\n", crtc.dot_clock);
1147 	if (crtc.dot_clock == 0) {
1148 		aprint_error("%s: preposterous dot clock (%d)\n",
1149 		    device_xname(sc->sc_dev), crtc.dot_clock);
1150 		return 1;
1151 	}
1152 	mach64_set_crtcregs(sc, &crtc);
1153 	return 0;
1154 }
1155 
1156 static void
mach64_reset_engine(struct mach64_softc * sc)1157 mach64_reset_engine(struct mach64_softc *sc)
1158 {
1159 
1160 	/* Reset engine.*/
1161 	regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE);
1162 
1163 	/* Enable engine. */
1164 	regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE);
1165 
1166 	/* Ensure engine is not locked up by clearing any FIFO or
1167 	   host errors. */
1168 	regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK |
1169 	    BUS_FIFO_ERR_ACK);
1170 }
1171 
1172 static void
mach64_init_engine(struct mach64_softc * sc)1173 mach64_init_engine(struct mach64_softc *sc)
1174 {
1175 	uint32_t pitch_value;
1176 
1177 	pitch_value = sc->stride;
1178 
1179 	if (sc->bits_per_pixel == 24)
1180 		pitch_value *= 3;
1181 
1182 	mach64_reset_engine(sc);
1183 
1184 	wait_for_fifo(sc, 14);
1185 
1186 	regw(sc, CONTEXT_MASK, 0xffffffff);
1187 
1188 	regw(sc, DST_OFF_PITCH, (pitch_value >> 3) << 22);
1189 
1190 	/* make sure the visible area starts where we're going to draw */
1191 	regw(sc, CRTC_OFF_PITCH, (sc->stride >> 3) << 22);
1192 
1193 	regw(sc, DST_Y_X, 0);
1194 	regw(sc, DST_HEIGHT, 0);
1195 	regw(sc, DST_BRES_ERR, 0);
1196 	regw(sc, DST_BRES_INC, 0);
1197 	regw(sc, DST_BRES_DEC, 0);
1198 
1199 	regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT |
1200 	    DST_Y_TOP_TO_BOTTOM);
1201 
1202 	regw(sc, SRC_OFF_PITCH, (pitch_value >> 3) << 22);
1203 
1204 	regw(sc, SRC_Y_X, 0);
1205 	regw(sc, SRC_HEIGHT1_WIDTH1, 1);
1206 	regw(sc, SRC_Y_X_START, 0);
1207 	regw(sc, SRC_HEIGHT2_WIDTH2, 1);
1208 
1209 	regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT);
1210 
1211 	wait_for_fifo(sc, 13);
1212 	regw(sc, HOST_CNTL, 0);
1213 
1214 	regw(sc, PAT_REG0, 0);
1215 	regw(sc, PAT_REG1, 0);
1216 	regw(sc, PAT_CNTL, 0);
1217 
1218 	regw(sc, SC_LEFT, 0);
1219 	regw(sc, SC_TOP, 0);
1220 	regw(sc, SC_BOTTOM, 0x3fff);
1221 	regw(sc, SC_RIGHT, pitch_value - 1);
1222 
1223 	regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG);
1224 	regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG);
1225 	regw(sc, DP_WRITE_MASK, 0xffffffff);
1226 	regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST);
1227 
1228 	regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR);
1229 
1230 	wait_for_fifo(sc, 3);
1231 	regw(sc, CLR_CMP_CLR, 0);
1232 	regw(sc, CLR_CMP_MASK, 0xffffffff);
1233 	regw(sc, CLR_CMP_CNTL, 0);
1234 
1235 	wait_for_fifo(sc, 3);
1236 	switch (sc->bits_per_pixel) {
1237 	case 8:
1238 		regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP);
1239 		regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP);
1240 		/* We want 8 bit per channel */
1241 		regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN);
1242 		break;
1243 	case 32:
1244 		regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP);
1245 		regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP);
1246 		regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN);
1247 		break;
1248 	}
1249 	regw(sc, DP_WRITE_MASK, 0xff);
1250 
1251 	wait_for_fifo(sc, 5);
1252 	regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20);
1253 	regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
1254 
1255 	wait_for_idle(sc);
1256 }
1257 
1258 #if 0
1259 static void
1260 mach64_adjust_frame(struct mach64_softc *sc, int x, int y)
1261 {
1262 	int offset;
1263 
1264 	offset = ((x + y * sc->stride) * (sc->bits_per_pixel >> 3)) >> 3;
1265 
1266 	regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) |
1267 	     offset);
1268 }
1269 #endif
1270 
1271 static void
mach64_set_dsp(struct mach64_softc * sc)1272 mach64_set_dsp(struct mach64_softc *sc)
1273 {
1274 	uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency;
1275 	uint32_t dsp_off, dsp_on, dsp_xclks_per_qw;
1276 	uint32_t xclks_per_qw, xclks_per_qw_m, y;
1277 	uint32_t fifo_off, fifo_on;
1278 
1279 	aprint_normal_dev(sc->sc_dev, "initializing the DSP\n");
1280 
1281 	if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT ||
1282 	    mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II ||
1283 	    mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP ||
1284 	    mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI ||
1285 	    mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B ||
1286 	    mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) {
1287 		dsp_loop_latency = 0;
1288 		fifo_depth = 24;
1289 	} else {
1290 		dsp_loop_latency = 2;
1291 		fifo_depth = 32;
1292 	}
1293 
1294 	dsp_precision = 0;
1295 
1296 	xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) /
1297 	    (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel);
1298 
1299 	xclks_per_qw_m = (sc->mem_freq * 64 << 4) /
1300 		       (sc->vclk_freq * sc->bits_per_pixel);
1301 
1302 	DPRINTF("xclks_per_qw %d %d\n", xclks_per_qw >> 7, xclks_per_qw_m);
1303 	DPRINTF("mem %dkHz v %dkHz\n", sc->mem_freq, sc->vclk_freq);
1304 
1305 	y = (xclks_per_qw * fifo_depth) >> 11;
1306 
1307 	while (y) {
1308 		y >>= 1;
1309 		dsp_precision++;
1310 	}
1311 	dsp_precision -= 5;
1312 	fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6);
1313 
1314 	switch (sc->memtype) {
1315 	case DRAM:
1316 	case EDO_DRAM:
1317 	case PSEUDO_EDO:
1318 		if (sc->memsize > 1024) {
1319 			page_size = 9;
1320 			dsp_loop_latency += 6;
1321 		} else {
1322 			page_size = 10;
1323 			if (sc->memtype == DRAM)
1324 				dsp_loop_latency += 8;
1325 			else
1326 				dsp_loop_latency += 7;
1327 		}
1328 		break;
1329 	case SDRAM:
1330 		if (sc->memsize > 1024) {
1331 			page_size = 8;
1332 			dsp_loop_latency += 8;
1333 		} else {
1334 			page_size = 10;
1335 			dsp_loop_latency += 9;
1336 		}
1337 		break;
1338 	case SGRAM:
1339 		page_size = 8;
1340 		dsp_loop_latency = 8;
1341 		break;
1342 	default:
1343 		page_size = 10;
1344 		dsp_loop_latency += 9;
1345 		break;
1346 	}
1347 
1348 	if (xclks_per_qw >= (page_size << 11))
1349 		fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5);
1350 	else
1351 		fifo_on = (3 * page_size + 2) << 6;
1352 
1353 	dsp_xclks_per_qw = xclks_per_qw >> dsp_precision;
1354 	dsp_on = fifo_on >> dsp_precision;
1355 	dsp_off = fifo_off >> dsp_precision;
1356 
1357 	DPRINTF("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n"
1358 	    "dsp_precision = %d, dsp_loop_latency = %d,\n"
1359 	    "mclk_fb_div = %d, vclk_fb_div = %d,\n"
1360 	    "mclk_post_div = %d, vclk_post_div = %d\n",
1361 	    dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency,
1362 	    sc->mclk_fb_div, sc->vclk_fb_div,
1363 	    sc->mclk_post_div, sc->vclk_post_div);
1364 	DPRINTF("DSP_ON_OFF %08x\n", regr(sc, DSP_ON_OFF));
1365 	DPRINTF("DSP_CONFIG %08x\n", regr(sc, DSP_CONFIG));
1366 	regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF));
1367 	regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) |
1368 	    ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) |
1369 	    (dsp_xclks_per_qw & DSP_XCLKS_PER_QW));
1370 	DPRINTF("DSP_ON_OFF %08x\n", regr(sc, DSP_ON_OFF));
1371 	DPRINTF("DSP_CONFIG %08x\n", regr(sc, DSP_CONFIG));
1372 }
1373 
1374 static void
mach64_set_pll(struct mach64_softc * sc,int clock)1375 mach64_set_pll(struct mach64_softc *sc, int clock)
1376 {
1377 	uint32_t q, clockreg;
1378 	int clockshift = sc->sc_clock << 1;
1379 	uint8_t reg, vclk_ctl;
1380 
1381 	q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq);
1382 #ifdef MACHFB_DEBUG
1383 	printf("q = %d\n", q);
1384 #endif
1385 	if (q > 25500) {
1386 		aprint_error_dev(sc->sc_dev, "Warning: q > 25500\n");
1387 		q = 25500;
1388 		sc->vclk_post_div = 1;
1389 		sc->log2_vclk_post_div = 0;
1390 	} else if (q > 12750) {
1391 		sc->vclk_post_div = 1;
1392 		sc->log2_vclk_post_div = 0;
1393 	} else if (q > 6350) {
1394 		sc->vclk_post_div = 2;
1395 		sc->log2_vclk_post_div = 1;
1396 	} else if (q > 3150) {
1397 		sc->vclk_post_div = 4;
1398 		sc->log2_vclk_post_div = 2;
1399 	} else if (q >= 1600) {
1400 		sc->vclk_post_div = 8;
1401 		sc->log2_vclk_post_div = 3;
1402 	} else {
1403 		aprint_error_dev(sc->sc_dev, "Warning: q < 1600\n");
1404 		sc->vclk_post_div = 8;
1405 		sc->log2_vclk_post_div = 3;
1406 	}
1407 	sc->vclk_fb_div = q * sc->vclk_post_div / 100;
1408 	DPRINTF("post_div: %d log2_post_div: %d mclk_div: %d\n",
1409 	    sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div);
1410 
1411 	vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL);
1412 	aprint_debug("vclk_ctl: %02x\n", vclk_ctl);
1413 	vclk_ctl |= PLL_VCLK_RESET;
1414 	regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl);
1415 
1416 	DPRINTF("target: %d output: %d\n", clock,
1417 	    (2 * sc->ref_freq * sc->vclk_fb_div) /
1418 	    (sc->ref_div * sc->vclk_post_div));
1419 
1420 	regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div);
1421 	reg = regrb_pll(sc, VCLK_POST_DIV);
1422 	reg &= ~(3 << clockshift);
1423 	reg |= (sc->log2_vclk_post_div << clockshift);
1424 	regwb_pll(sc, VCLK_POST_DIV, reg);
1425 	regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div);
1426 
1427 	vclk_ctl &= ~PLL_VCLK_RESET;
1428 	regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl);
1429 
1430 	clockreg = regr(sc, CLOCK_CNTL);
1431 	clockreg &= ~CLOCK_SEL;
1432 	clockreg |= sc->sc_clock | CLOCK_STROBE;
1433 	regw(sc, CLOCK_CNTL, clockreg);
1434 	sc->vclk_freq = clock;
1435 }
1436 
1437 static void
mach64_init_lut(struct mach64_softc * sc)1438 mach64_init_lut(struct mach64_softc *sc)
1439 {
1440 	uint8_t cmap[768];
1441 	int i, idx;
1442 
1443 	rasops_get_cmap(&mach64_console_screen.scr_ri, cmap, sizeof(cmap));
1444 	idx = 0;
1445 	for (i = 0; i < 256; i++) {
1446 		mach64_putpalreg(sc, i, cmap[idx], cmap[idx + 1],
1447 		    cmap[idx + 2]);
1448 		idx += 3;
1449 	}
1450 }
1451 
1452 static int
mach64_putpalreg(struct mach64_softc * sc,uint8_t index,uint8_t r,uint8_t g,uint8_t b)1453 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g,
1454     uint8_t b)
1455 {
1456 	sc->sc_cmap_red[index] = r;
1457 	sc->sc_cmap_green[index] = g;
1458 	sc->sc_cmap_blue[index] = b;
1459 	/*
1460 	 * writing the dac index takes a while, in theory we can poll some
1461 	 * register to see when it's ready - but we better avoid writing it
1462 	 * unnecessarily
1463 	 */
1464 	if (index != sc->sc_dacw) {
1465 		regwb(sc, DAC_MASK, 0xff);
1466 		regwb(sc, DAC_WINDEX, index);
1467 	}
1468 	sc->sc_dacw = index + 1;
1469 	regwb(sc, DAC_DATA, r);
1470 	regwb(sc, DAC_DATA, g);
1471 	regwb(sc, DAC_DATA, b);
1472 	return 0;
1473 }
1474 
1475 static int
mach64_putcmap(struct mach64_softc * sc,struct wsdisplay_cmap * cm)1476 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm)
1477 {
1478 	uint index = cm->index;
1479 	uint count = cm->count;
1480 	int i, error;
1481 	uint8_t rbuf[256], gbuf[256], bbuf[256];
1482 	uint8_t *r, *g, *b;
1483 
1484 	if (cm->index >= 256 || cm->count > 256 ||
1485 	    (cm->index + cm->count) > 256)
1486 		return EINVAL;
1487 	error = copyin(cm->red, &rbuf[index], count);
1488 	if (error)
1489 		return error;
1490 	error = copyin(cm->green, &gbuf[index], count);
1491 	if (error)
1492 		return error;
1493 	error = copyin(cm->blue, &bbuf[index], count);
1494 	if (error)
1495 		return error;
1496 
1497 	memcpy(&sc->sc_cmap_red[index], &rbuf[index], count);
1498 	memcpy(&sc->sc_cmap_green[index], &gbuf[index], count);
1499 	memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count);
1500 
1501 	r = &sc->sc_cmap_red[index];
1502 	g = &sc->sc_cmap_green[index];
1503 	b = &sc->sc_cmap_blue[index];
1504 
1505 	for (i = 0; i < count; i++) {
1506 		mach64_putpalreg(sc, index, *r, *g, *b);
1507 		index++;
1508 		r++, g++, b++;
1509 	}
1510 	return 0;
1511 }
1512 
1513 static int
mach64_getcmap(struct mach64_softc * sc,struct wsdisplay_cmap * cm)1514 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm)
1515 {
1516 	u_int index = cm->index;
1517 	u_int count = cm->count;
1518 	int error;
1519 
1520 	if (index >= 255 || count > 256 || index + count > 256)
1521 		return EINVAL;
1522 
1523 	error = copyout(&sc->sc_cmap_red[index],   cm->red,   count);
1524 	if (error)
1525 		return error;
1526 	error = copyout(&sc->sc_cmap_green[index], cm->green, count);
1527 	if (error)
1528 		return error;
1529 	error = copyout(&sc->sc_cmap_blue[index],  cm->blue,  count);
1530 	if (error)
1531 		return error;
1532 
1533 	return 0;
1534 }
1535 
1536 static int
mach64_is_console(struct mach64_softc * sc)1537 mach64_is_console(struct mach64_softc *sc)
1538 {
1539 	bool console = 0;
1540 
1541 	prop_dictionary_get_bool(device_properties(sc->sc_dev),
1542 	    "is_console", &console);
1543 	return console;
1544 }
1545 
1546 /*
1547  * wsdisplay_emulops
1548  */
1549 
1550 static void
mach64_cursor(void * cookie,int on,int row,int col)1551 mach64_cursor(void *cookie, int on, int row, int col)
1552 {
1553 	struct rasops_info *ri = cookie;
1554 	struct vcons_screen *scr = ri->ri_hw;
1555 	struct mach64_softc *sc = scr->scr_cookie;
1556 	int x, y, wi, he;
1557 
1558 	wi = ri->ri_font->fontwidth;
1559 	he = ri->ri_font->fontheight;
1560 
1561 	if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) {
1562 		x = ri->ri_ccol * wi + ri->ri_xorigin;
1563 		y = ri->ri_crow * he + ri->ri_yorigin;
1564 		if (ri->ri_flg & RI_CURSOR) {
1565 			mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC);
1566 			ri->ri_flg &= ~RI_CURSOR;
1567 		}
1568 		ri->ri_crow = row;
1569 		ri->ri_ccol = col;
1570 		if (on) {
1571 			x = ri->ri_ccol * wi + ri->ri_xorigin;
1572 			y = ri->ri_crow * he + ri->ri_yorigin;
1573 			mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC);
1574 			ri->ri_flg |= RI_CURSOR;
1575 		}
1576 	} else {
1577 		scr->scr_ri.ri_crow = row;
1578 		scr->scr_ri.ri_ccol = col;
1579 		scr->scr_ri.ri_flg &= ~RI_CURSOR;
1580 	}
1581 }
1582 
1583 #if 0
1584 static int
1585 mach64_mapchar(void *cookie, int uni, u_int *index)
1586 {
1587 	return 0;
1588 }
1589 #endif
1590 
1591 static void
mach64_putchar_mono(void * cookie,int row,int col,u_int c,long attr)1592 mach64_putchar_mono(void *cookie, int row, int col, u_int c, long attr)
1593 {
1594 	struct rasops_info *ri = cookie;
1595 	struct wsdisplay_font *font = PICK_FONT(ri, c);
1596 	struct vcons_screen *scr = ri->ri_hw;
1597 	struct mach64_softc *sc = scr->scr_cookie;
1598 
1599 	if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) {
1600 		int fg, bg, uc;
1601 		uint8_t *data;
1602 		int x, y, wi, he;
1603 		wi = font->fontwidth;
1604 		he = font->fontheight;
1605 
1606 		if (!CHAR_IN_FONT(c, font))
1607 			return;
1608 		bg = ri->ri_devcmap[(attr >> 16) & 0x0f];
1609 		fg = ri->ri_devcmap[(attr >> 24) & 0x0f];
1610 		x = ri->ri_xorigin + col * wi;
1611 		y = ri->ri_yorigin + row * he;
1612 		if (c == 0x20) {
1613 			mach64_rectfill(sc, x, y, wi, he, bg);
1614 		} else {
1615 			uc = c - font->firstchar;
1616 			data = (uint8_t *)font->data + uc *
1617 			    ri->ri_fontscale;
1618 
1619 			mach64_setup_mono(sc, x, y, wi, he, fg, bg);
1620 			mach64_feed_bytes(sc, ri->ri_fontscale, data);
1621 		}
1622 		if (attr & 1)
1623 			mach64_rectfill(sc, x, y + he - 2, wi, 1, fg);
1624 	}
1625 }
1626 
1627 static void
mach64_putchar_aa8(void * cookie,int row,int col,u_int c,long attr)1628 mach64_putchar_aa8(void *cookie, int row, int col, u_int c, long attr)
1629 {
1630 	struct rasops_info *ri = cookie;
1631 	struct wsdisplay_font *font = PICK_FONT(ri, c);
1632 	struct vcons_screen *scr = ri->ri_hw;
1633 	struct mach64_softc *sc = scr->scr_cookie;
1634 	uint32_t bg, fg, latch = 0, bg8, fg8, pixel;
1635 	int i, x, y, wi, he, r, g, b, aval;
1636 	int r1, g1, b1, r0, g0, b0, fgo, bgo;
1637 	uint8_t *data8;
1638 	int rv = 0, cnt = 0;
1639 
1640 	if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL)
1641 		return;
1642 
1643 	if (!CHAR_IN_FONT(c, font))
1644 		return;
1645 
1646 	wi = font->fontwidth;
1647 	he = font->fontheight;
1648 	bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f];
1649 	fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f];
1650 	x = ri->ri_xorigin + col * wi;
1651 	y = ri->ri_yorigin + row * he;
1652 
1653 	if (c == 0x20) {
1654 		mach64_rectfill(sc, x, y, wi, he, bg);
1655 		if (attr & 1)
1656 			mach64_rectfill(sc, x, y + he - 2, wi, 1, fg);
1657 		return;
1658 	}
1659 
1660 	rv = glyphcache_try(&sc->sc_gc, c, x, y, attr);
1661 	if (rv == GC_OK)
1662 		return;
1663 
1664 	data8 = WSFONT_GLYPH(c, font);
1665 
1666 	wait_for_fifo(sc, 11);
1667 	regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP);
1668 	regw(sc, DP_SRC, MONO_SRC_ONE | BKGD_SRC_HOST | FRGD_SRC_HOST);
1669 	regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC);
1670 	regw(sc, CLR_CMP_CNTL ,0);	/* no transparency */
1671 	regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT);
1672 	regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT);
1673 	regw(sc, HOST_CNTL, HOST_BYTE_ALIGN);
1674 	regw(sc, SRC_Y_X, 0);
1675 	regw(sc, SRC_WIDTH1, wi);
1676 	regw(sc, DST_Y_X, (x << 16) | y);
1677 	regw(sc, DST_HEIGHT_WIDTH, (wi << 16) | he);
1678 
1679 	/*
1680 	 * we need the RGB colours here, so get offsets into rasops_cmap
1681 	 */
1682 	fgo = ((attr >> 24) & 0xf) * 3;
1683 	bgo = ((attr >> 16) & 0xf) * 3;
1684 
1685 	r0 = rasops_cmap[bgo];
1686 	r1 = rasops_cmap[fgo];
1687 	g0 = rasops_cmap[bgo + 1];
1688 	g1 = rasops_cmap[fgo + 1];
1689 	b0 = rasops_cmap[bgo + 2];
1690 	b1 = rasops_cmap[fgo + 2];
1691 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6))
1692 	bg8 = R3G3B2(r0, g0, b0);
1693 	fg8 = R3G3B2(r1, g1, b1);
1694 
1695 	wait_for_fifo(sc, 10);
1696 
1697 	for (i = 0; i < ri->ri_fontscale; i++) {
1698 		aval = *data8;
1699 		if (aval == 0) {
1700 			pixel = bg8;
1701 		} else if (aval == 255) {
1702 			pixel = fg8;
1703 		} else {
1704 			r = aval * r1 + (255 - aval) * r0;
1705 			g = aval * g1 + (255 - aval) * g0;
1706 			b = aval * b1 + (255 - aval) * b0;
1707 			pixel = ((r & 0xe000) >> 8) |
1708 				((g & 0xe000) >> 11) |
1709 				((b & 0xc000) >> 14);
1710 		}
1711 		latch = (latch << 8) | pixel;
1712 		/* write in 32bit chunks */
1713 		if ((i & 3) == 3) {
1714 			regws(sc, HOST_DATA0, latch);
1715 			/*
1716 			 * not strictly necessary, old data should be shifted
1717 			 * out
1718 			 */
1719 			latch = 0;
1720 			cnt++;
1721 			if (cnt > 8) {
1722 				wait_for_fifo(sc, 10);
1723 				cnt = 0;
1724 			}
1725 		}
1726 		data8++;
1727 	}
1728 	/* if we have pixels left in latch write them out */
1729 	if ((i & 3) != 0) {
1730 		latch = latch << ((4 - (i & 3)) << 3);
1731 		regws(sc, HOST_DATA0, latch);
1732 	}
1733 
1734 	if (rv == GC_ADD) {
1735 		glyphcache_add(&sc->sc_gc, c, x, y);
1736 	} else 	if (attr & 1) {
1737 		mach64_rectfill(sc, x, y + he - 2, wi, 1, fg);
1738 	}
1739 
1740 }
1741 
1742 static void
mach64_copycols(void * cookie,int row,int srccol,int dstcol,int ncols)1743 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols)
1744 {
1745 	struct rasops_info *ri = cookie;
1746 	struct vcons_screen *scr = ri->ri_hw;
1747 	struct mach64_softc *sc = scr->scr_cookie;
1748 	int32_t xs, xd, y, width, height;
1749 
1750 	if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) {
1751 		xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol;
1752 		xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol;
1753 		y = ri->ri_yorigin + ri->ri_font->fontheight * row;
1754 		width = ri->ri_font->fontwidth * ncols;
1755 		height = ri->ri_font->fontheight;
1756 		mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC);
1757 	}
1758 }
1759 
1760 static void
mach64_erasecols(void * cookie,int row,int startcol,int ncols,long fillattr)1761 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr)
1762 {
1763 	struct rasops_info *ri = cookie;
1764 	struct vcons_screen *scr = ri->ri_hw;
1765 	struct mach64_softc *sc = scr->scr_cookie;
1766 	int32_t x, y, width, height, fg, bg, ul;
1767 
1768 	if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) {
1769 		x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol;
1770 		y = ri->ri_yorigin + ri->ri_font->fontheight * row;
1771 		width = ri->ri_font->fontwidth * ncols;
1772 		height = ri->ri_font->fontheight;
1773 		rasops_unpack_attr(fillattr, &fg, &bg, &ul);
1774 
1775 		mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]);
1776 	}
1777 }
1778 
1779 static void
mach64_copyrows(void * cookie,int srcrow,int dstrow,int nrows)1780 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows)
1781 {
1782 	struct rasops_info *ri = cookie;
1783 	struct vcons_screen *scr = ri->ri_hw;
1784 	struct mach64_softc *sc = scr->scr_cookie;
1785 	int32_t x, ys, yd, width, height;
1786 
1787 	if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) {
1788 		x = ri->ri_xorigin;
1789 		ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow;
1790 		yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow;
1791 		width = ri->ri_emuwidth;
1792 		height = ri->ri_font->fontheight*nrows;
1793 		mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC);
1794 	}
1795 }
1796 
1797 static void
mach64_eraserows(void * cookie,int row,int nrows,long fillattr)1798 mach64_eraserows(void *cookie, int row, int nrows, long fillattr)
1799 {
1800 	struct rasops_info *ri = cookie;
1801 	struct vcons_screen *scr = ri->ri_hw;
1802 	struct mach64_softc *sc = scr->scr_cookie;
1803 	int32_t x, y, width, height, fg, bg, ul;
1804 
1805 	if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) {
1806 		if ((row == 0) && (nrows == ri->ri_rows)) {
1807 			/* clear full screen */
1808 			x = 0;
1809 			y = 0;
1810 			width = sc->virt_x;
1811 			height = sc->virt_y;
1812 		} else {
1813 			x = ri->ri_xorigin;
1814 			y = ri->ri_yorigin + ri->ri_font->fontheight * row;
1815 			width = ri->ri_emuwidth;
1816 			height = ri->ri_font->fontheight * nrows;
1817 		}
1818 		rasops_unpack_attr(fillattr, &fg, &bg, &ul);
1819 
1820 		mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]);
1821 	}
1822 }
1823 
1824 static void
mach64_bitblt(void * cookie,int xs,int ys,int xd,int yd,int width,int height,int rop)1825 mach64_bitblt(void *cookie, int xs, int ys, int xd, int yd, int width,
1826     int height, int rop)
1827 {
1828 	struct mach64_softc *sc = cookie;
1829 	uint32_t dest_ctl = 0;
1830 
1831 #if 0
1832 	wait_for_idle(sc);
1833 #else
1834 	wait_for_fifo(sc, 10);
1835 #endif
1836 
1837 	regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP);
1838 	regw(sc, DP_SRC, FRGD_SRC_BLIT);
1839 	regw(sc, DP_MIX, (rop & 0xffff) << 16);
1840 	regw(sc, CLR_CMP_CNTL, 0);	/* no transparency */
1841 	if (yd < ys) {
1842 		dest_ctl = DST_Y_TOP_TO_BOTTOM;
1843 	} else {
1844 		ys += height - 1;
1845 		yd += height - 1;
1846 		dest_ctl = DST_Y_BOTTOM_TO_TOP;
1847 	}
1848 	if (xd < xs) {
1849 		dest_ctl |= DST_X_LEFT_TO_RIGHT;
1850 		regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT);
1851 	} else {
1852 		dest_ctl |= DST_X_RIGHT_TO_LEFT;
1853 		xs += width - 1;
1854 		xd += width - 1;
1855 		regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT);
1856 	}
1857 	regw(sc, DST_CNTL, dest_ctl);
1858 
1859 	regw(sc, SRC_Y_X, (xs << 16) | ys);
1860 	regw(sc, SRC_WIDTH1, width);
1861 	regw(sc, DST_Y_X, (xd << 16) | yd);
1862 	regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height);
1863 }
1864 
1865 static void
mach64_setup_mono(struct mach64_softc * sc,int xd,int yd,int width,int height,uint32_t fg,uint32_t bg)1866 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width,
1867      int height, uint32_t fg, uint32_t bg)
1868 {
1869 	wait_for_idle(sc);
1870 	regw(sc, DP_WRITE_MASK, 0xff);	/* XXX only good for 8 bit */
1871 	regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP);
1872 	regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR);
1873 	regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC);
1874 	regw(sc, CLR_CMP_CNTL ,0);	/* no transparency */
1875 	regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT);
1876 	regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT);
1877 	regw(sc, HOST_CNTL, HOST_BYTE_ALIGN);
1878 	regw(sc, DP_BKGD_CLR, bg);
1879 	regw(sc, DP_FRGD_CLR, fg);
1880 	regw(sc, SRC_Y_X, 0);
1881 	regw(sc, SRC_WIDTH1, width);
1882 	regw(sc, DST_Y_X, (xd << 16) | yd);
1883 	regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height);
1884 	/* now feed the data into the chip */
1885 }
1886 
1887 static void
mach64_feed_bytes(struct mach64_softc * sc,int count,uint8_t * data)1888 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data)
1889 {
1890 	int i;
1891 	uint32_t latch = 0, bork;
1892 	int shift = 0;
1893 	int reg = 0;
1894 
1895 	for (i = 0; i < count; i++) {
1896 		bork = data[i];
1897 		latch |= (bork << shift);
1898 		if (shift == 24) {
1899 			regw(sc, HOST_DATA0 + reg, latch);
1900 			latch = 0;
1901 			shift = 0;
1902 			reg = (reg + 4) & 0x3c;
1903 		} else
1904 			shift += 8;
1905 	}
1906 	if (shift != 0)	/* 24 */
1907 		regw(sc, HOST_DATA0 + reg, latch);
1908 }
1909 
1910 
1911 static void
mach64_rectfill(struct mach64_softc * sc,int x,int y,int width,int height,int colour)1912 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height,
1913     int colour)
1914 {
1915 	wait_for_fifo(sc, 11);
1916 	regw(sc, DP_FRGD_CLR, colour);
1917 	regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP);
1918 	regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR);
1919 	regw(sc, DP_MIX, MIX_SRC << 16);
1920 	regw(sc, CLR_CMP_CNTL, 0);	/* no transparency */
1921 	regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT);
1922 	regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
1923 
1924 	regw(sc, SRC_Y_X, (x << 16) | y);
1925 	regw(sc, SRC_WIDTH1, width);
1926 	regw(sc, DST_Y_X, (x << 16) | y);
1927 	regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height);
1928 }
1929 
1930 static void
mach64_clearscreen(struct mach64_softc * sc)1931 mach64_clearscreen(struct mach64_softc *sc)
1932 {
1933 	mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg);
1934 }
1935 
1936 
1937 #if 0
1938 static void
1939 mach64_showpal(struct mach64_softc *sc)
1940 {
1941 	int i, x = 0;
1942 
1943 	for (i = 0; i < 16; i++) {
1944 		mach64_rectfill(sc, x, 0, 64, 64, i);
1945 		x += 64;
1946 	}
1947 }
1948 #endif
1949 
1950 /*
1951  * wsdisplay_accessops
1952  */
1953 
1954 static int
mach64_ioctl(void * v,void * vs,u_long cmd,void * data,int flag,struct lwp * l)1955 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag,
1956 	struct lwp *l)
1957 {
1958 	struct vcons_data *vd = v;
1959 	struct mach64_softc *sc = vd->cookie;
1960 	struct wsdisplay_fbinfo *wdf;
1961 	struct vcons_screen *ms = vd->active;
1962 
1963 	switch (cmd) {
1964 	case WSDISPLAYIO_GTYPE:
1965 		*(u_int *)data = WSDISPLAY_TYPE_PCIMISC;
1966 		return 0;
1967 
1968 	case WSDISPLAYIO_LINEBYTES:
1969 		*(u_int *)data = sc->stride * sc->bits_per_pixel / 8;
1970 		return 0;
1971 
1972 	case WSDISPLAYIO_GINFO:
1973 		wdf = (void *)data;
1974 		wdf->height = sc->virt_y;
1975 		wdf->width = sc->virt_x;
1976 		wdf->depth = sc->bits_per_pixel;
1977 		wdf->cmsize = 256;
1978 		return 0;
1979 
1980 	case WSDISPLAYIO_GETCMAP:
1981 		return mach64_getcmap(sc,
1982 		    (struct wsdisplay_cmap *)data);
1983 
1984 	case WSDISPLAYIO_PUTCMAP:
1985 		return mach64_putcmap(sc,
1986 		    (struct wsdisplay_cmap *)data);
1987 
1988 	/* PCI config read/write passthrough. */
1989 	case PCI_IOC_CFGREAD:
1990 	case PCI_IOC_CFGWRITE:
1991 		return pci_devioctl(sc->sc_pc, sc->sc_pcitag,
1992 		    cmd, data, flag, l);
1993 
1994 	case WSDISPLAYIO_GET_BUSID:
1995 		return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc,
1996 		    sc->sc_pcitag, data);
1997 
1998 	case WSDISPLAYIO_SMODE: {
1999 		int new_mode = *(int*)data;
2000 		if (new_mode != sc->sc_mode) {
2001 			sc->sc_mode = new_mode;
2002 			if ((new_mode == WSDISPLAYIO_MODE_EMUL)
2003 			    && (ms != NULL))
2004 			{
2005 				/* restore initial video mode */
2006 				mach64_init(sc);
2007 				mach64_init_engine(sc);
2008 				mach64_init_lut(sc);
2009 				if (sc->sc_setmode)
2010 					mach64_modeswitch(sc, sc->sc_my_mode);
2011 				mach64_clearscreen(sc);
2012 				glyphcache_wipe(&sc->sc_gc);
2013 				vcons_redraw_screen(ms);
2014 			}
2015 		}
2016 		}
2017 		return 0;
2018 	case WSDISPLAYIO_GET_EDID: {
2019 		struct wsdisplayio_edid_info *d = data;
2020 		return wsdisplayio_get_edid(sc->sc_dev, d);
2021 	}
2022 
2023 	case WSDISPLAYIO_GET_FBINFO: {
2024 		struct wsdisplayio_fbinfo *fbi = data;
2025 		return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi);
2026 	}
2027 	}
2028 	return EPASSTHROUGH;
2029 }
2030 
2031 static paddr_t
mach64_mmap(void * v,void * vs,off_t offset,int prot)2032 mach64_mmap(void *v, void *vs, off_t offset, int prot)
2033 {
2034 	struct vcons_data *vd = v;
2035 	struct mach64_softc *sc = vd->cookie;
2036 	paddr_t pa;
2037 
2038 	if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) {
2039 		/*
2040 		 *'regular' framebuffer mmap()ing
2041 		 */
2042 		if (offset < (sc->memsize * 1024)) {
2043 			pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase,
2044 			    offset, prot, BUS_SPACE_MAP_LINEAR);
2045 			return pa;
2046 		}
2047 	} else if (sc->sc_mode == WSDISPLAYIO_MODE_MAPPED) {
2048 		/*
2049 		 * restrict all other mappings to processes with superuser
2050 		 * privileges
2051 		 */
2052 		if (kauth_authorize_machdep(kauth_cred_get(),
2053 		    KAUTH_MACHDEP_UNMANAGEDMEM,
2054 		    NULL, NULL, NULL, NULL) != 0) {
2055 			return -1;
2056 		}
2057 		if ((offset >= sc->sc_aperbase) &&
2058 		    (offset < (sc->sc_aperbase + sc->sc_apersize))) {
2059 			pa = bus_space_mmap(sc->sc_memt, offset, 0, prot,
2060 			    BUS_SPACE_MAP_LINEAR);
2061 			return pa;
2062 		}
2063 
2064 		if ((offset >= sc->sc_regbase) &&
2065 		    (offset < (sc->sc_regbase + sc->sc_regsize))) {
2066 			pa = bus_space_mmap(sc->sc_regt, offset, 0, prot,
2067 			    BUS_SPACE_MAP_LINEAR);
2068 			return pa;
2069 		}
2070 
2071 		if ((offset >= sc->sc_rom.vb_base) &&
2072 		    (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) {
2073 			pa = bus_space_mmap(sc->sc_memt, offset, 0, prot,
2074 			    BUS_SPACE_MAP_LINEAR);
2075 			return pa;
2076 		}
2077 
2078 #ifdef PCI_MAGIC_IO_RANGE
2079 		if ((offset >= PCI_MAGIC_IO_RANGE) &&
2080 		    (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) {
2081 		    	return bus_space_mmap(sc->sc_iot,
2082 		    	   offset - PCI_MAGIC_IO_RANGE, 0, prot, 0);
2083 		}
2084 #endif
2085 	}
2086 	return -1;
2087 }
2088 
2089 #if 0
2090 static int
2091 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data)
2092 {
2093 
2094 	return 0;
2095 }
2096 #endif
2097 
2098 void
machfb_blank(struct mach64_softc * sc,int blank)2099 machfb_blank(struct mach64_softc *sc, int blank)
2100 {
2101 	uint32_t reg;
2102 
2103 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS)
2104 
2105 	switch (blank)
2106 	{
2107     		case 0:
2108 			reg = regr(sc, CRTC_GEN_CNTL);
2109 			regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK));
2110 			sc->sc_blanked = 0;
2111 			break;
2112 		case 1:
2113 			reg = regr(sc, CRTC_GEN_CNTL);
2114 			regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK));
2115 			sc->sc_blanked = 1;
2116 			break;
2117 		default:
2118         		break;
2119 	}
2120 }
2121