1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #ifndef HNS3_CMD_H 6 #define HNS3_CMD_H 7 8 #include <stdint.h> 9 10 #include <rte_byteorder.h> 11 #include <rte_spinlock.h> 12 13 #define HNS3_CMDQ_TX_TIMEOUT 30000 14 #define HNS3_CMDQ_CLEAR_WAIT_TIME 200 15 #define HNS3_CMDQ_RX_INVLD_B 0 16 #define HNS3_CMDQ_RX_OUTVLD_B 1 17 #define HNS3_CMD_DESC_ALIGNMENT 4096 18 #define HNS3_CMD_FLAG_NEXT BIT(2) 19 20 struct hns3_hw; 21 22 #define HNS3_CMD_DESC_DATA_NUM 6 23 struct hns3_cmd_desc { 24 uint16_t opcode; 25 uint16_t flag; 26 uint16_t retval; 27 uint16_t rsv; 28 uint32_t data[HNS3_CMD_DESC_DATA_NUM]; 29 }; 30 31 struct hns3_cmq_ring { 32 uint64_t desc_dma_addr; 33 struct hns3_cmd_desc *desc; 34 struct hns3_hw *hw; 35 36 uint16_t buf_size; 37 uint16_t desc_num; /* max number of cmq descriptor */ 38 uint32_t next_to_use; 39 uint32_t next_to_clean; 40 uint8_t ring_type; /* cmq ring type */ 41 rte_spinlock_t lock; /* Command queue lock */ 42 43 const void *zone; /* memory zone */ 44 }; 45 46 enum hns3_cmd_return_status { 47 HNS3_CMD_EXEC_SUCCESS = 0, 48 HNS3_CMD_NO_AUTH = 1, 49 HNS3_CMD_NOT_SUPPORTED = 2, 50 HNS3_CMD_QUEUE_FULL = 3, 51 HNS3_CMD_NEXT_ERR = 4, 52 HNS3_CMD_UNEXE_ERR = 5, 53 HNS3_CMD_PARA_ERR = 6, 54 HNS3_CMD_RESULT_ERR = 7, 55 HNS3_CMD_TIMEOUT = 8, 56 HNS3_CMD_HILINK_ERR = 9, 57 HNS3_CMD_QUEUE_ILLEGAL = 10, 58 HNS3_CMD_INVALID = 11, 59 HNS3_CMD_ROH_CHECK_FAIL = 12 60 }; 61 62 struct hns3_cmq { 63 struct hns3_cmq_ring csq; 64 struct hns3_cmq_ring crq; 65 uint16_t tx_timeout; 66 enum hns3_cmd_return_status last_status; 67 }; 68 69 enum hns3_opcode_type { 70 /* Generic commands */ 71 HNS3_OPC_QUERY_FW_VER = 0x0001, 72 HNS3_OPC_CFG_RST_TRIGGER = 0x0020, 73 HNS3_OPC_GBL_RST_STATUS = 0x0021, 74 HNS3_OPC_QUERY_FUNC_STATUS = 0x0022, 75 HNS3_OPC_QUERY_PF_RSRC = 0x0023, 76 HNS3_OPC_QUERY_VF_RSRC = 0x0024, 77 HNS3_OPC_GET_CFG_PARAM = 0x0025, 78 HNS3_OPC_PF_RST_DONE = 0x0026, 79 80 HNS3_OPC_STATS_64_BIT = 0x0030, 81 HNS3_OPC_STATS_32_BIT = 0x0031, 82 HNS3_OPC_STATS_MAC = 0x0032, 83 HNS3_OPC_QUERY_MAC_REG_NUM = 0x0033, 84 HNS3_OPC_STATS_MAC_ALL = 0x0034, 85 86 HNS3_OPC_QUERY_REG_NUM = 0x0040, 87 HNS3_OPC_QUERY_32_BIT_REG = 0x0041, 88 HNS3_OPC_QUERY_64_BIT_REG = 0x0042, 89 HNS3_OPC_DFX_BD_NUM = 0x0043, 90 HNS3_OPC_DFX_BIOS_COMMON_REG = 0x0044, 91 HNS3_OPC_DFX_SSU_REG_0 = 0x0045, 92 HNS3_OPC_DFX_SSU_REG_1 = 0x0046, 93 HNS3_OPC_DFX_IGU_EGU_REG = 0x0047, 94 HNS3_OPC_DFX_RPU_REG_0 = 0x0048, 95 HNS3_OPC_DFX_RPU_REG_1 = 0x0049, 96 HNS3_OPC_DFX_NCSI_REG = 0x004A, 97 HNS3_OPC_DFX_RTC_REG = 0x004B, 98 HNS3_OPC_DFX_PPP_REG = 0x004C, 99 HNS3_OPC_DFX_RCB_REG = 0x004D, 100 HNS3_OPC_DFX_TQP_REG = 0x004E, 101 HNS3_OPC_DFX_SSU_REG_2 = 0x004F, 102 103 HNS3_OPC_QUERY_DEV_SPECS = 0x0050, 104 105 HNS3_OPC_SSU_DROP_REG = 0x0065, 106 107 /* MAC command */ 108 HNS3_OPC_CONFIG_MAC_MODE = 0x0301, 109 HNS3_OPC_CONFIG_AN_MODE = 0x0304, 110 HNS3_OPC_QUERY_LINK_STATUS = 0x0307, 111 HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 112 HNS3_OPC_CONFIG_SPEED_DUP = 0x0309, 113 HNS3_OPC_QUERY_MAC_TNL_INT = 0x0310, 114 HNS3_OPC_MAC_TNL_INT_EN = 0x0311, 115 HNS3_OPC_CLEAR_MAC_TNL_INT = 0x0312, 116 HNS3_OPC_CONFIG_FEC_MODE = 0x031A, 117 118 /* PTP command */ 119 HNS3_OPC_PTP_INT_EN = 0x0501, 120 HNS3_OPC_CFG_PTP_MODE = 0x0507, 121 122 /* PFC/Pause commands */ 123 HNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701, 124 HNS3_OPC_CFG_PFC_PAUSE_EN = 0x0702, 125 HNS3_OPC_CFG_MAC_PARA = 0x0703, 126 HNS3_OPC_CFG_PFC_PARA = 0x0704, 127 HNS3_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 128 HNS3_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 129 HNS3_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 130 HNS3_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 131 HNS3_OPC_PRI_TO_TC_MAPPING = 0x0709, 132 HNS3_OPC_QOS_MAP = 0x070A, 133 134 /* ETS/scheduler commands */ 135 HNS3_OPC_TM_PG_TO_PRI_LINK = 0x0804, 136 HNS3_OPC_TM_QS_TO_PRI_LINK = 0x0805, 137 HNS3_OPC_TM_NQ_TO_QS_LINK = 0x0806, 138 HNS3_OPC_TM_RQ_TO_QS_LINK = 0x0807, 139 HNS3_OPC_TM_PORT_WEIGHT = 0x0808, 140 HNS3_OPC_TM_PG_WEIGHT = 0x0809, 141 HNS3_OPC_TM_QS_WEIGHT = 0x080A, 142 HNS3_OPC_TM_PRI_WEIGHT = 0x080B, 143 HNS3_OPC_TM_PRI_C_SHAPPING = 0x080C, 144 HNS3_OPC_TM_PRI_P_SHAPPING = 0x080D, 145 HNS3_OPC_TM_PG_C_SHAPPING = 0x080E, 146 HNS3_OPC_TM_PG_P_SHAPPING = 0x080F, 147 HNS3_OPC_TM_PORT_SHAPPING = 0x0810, 148 HNS3_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 149 HNS3_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 150 HNS3_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 151 HNS3_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 152 HNS3_OPC_ETS_TC_WEIGHT = 0x0843, 153 HNS3_OPC_QSET_DFX_STS = 0x0844, 154 HNS3_OPC_PRI_DFX_STS = 0x0845, 155 HNS3_OPC_PG_DFX_STS = 0x0846, 156 HNS3_OPC_PORT_DFX_STS = 0x0847, 157 HNS3_OPC_SCH_NQ_CNT = 0x0848, 158 HNS3_OPC_SCH_RQ_CNT = 0x0849, 159 HNS3_OPC_TM_INTERNAL_STS = 0x0850, 160 HNS3_OPC_TM_INTERNAL_CNT = 0x0851, 161 HNS3_OPC_TM_INTERNAL_STS_1 = 0x0852, 162 163 HNS3_OPC_TM_PORT_LIMIT_RATE = 0x0870, 164 HNS3_OPC_TM_TC_LIMIT_RATE = 0x0871, 165 166 /* Mailbox cmd */ 167 HNS3_OPC_MBX_VF_TO_PF = 0x2001, 168 169 /* Packet buffer allocate commands */ 170 HNS3_OPC_TX_BUFF_ALLOC = 0x0901, 171 HNS3_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 172 HNS3_OPC_RX_PRIV_WL_ALLOC = 0x0903, 173 HNS3_OPC_RX_COM_THRD_ALLOC = 0x0904, 174 HNS3_OPC_RX_COM_WL_ALLOC = 0x0905, 175 176 /* TQP management command */ 177 HNS3_OPC_SET_TQP_MAP = 0x0A01, 178 179 /* TQP commands */ 180 HNS3_OPC_QUERY_TX_STATUS = 0x0B03, 181 HNS3_OPC_QUERY_RX_STATUS = 0x0B13, 182 HNS3_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 183 HNS3_OPC_RESET_TQP_QUEUE = 0x0B22, 184 HNS3_OPC_RESET_TQP_QUEUE_INDEP = 0x0B23, 185 186 /* TSO command */ 187 HNS3_OPC_TSO_GENERIC_CONFIG = 0x0C01, 188 HNS3_OPC_GRO_GENERIC_CONFIG = 0x0C10, 189 190 /* RSS commands */ 191 HNS3_OPC_RSS_GENERIC_CONFIG = 0x0D01, 192 HNS3_OPC_RSS_INPUT_TUPLE = 0x0D02, 193 HNS3_OPC_RSS_INDIR_TABLE = 0x0D07, 194 HNS3_OPC_RSS_TC_MODE = 0x0D08, 195 196 /* Promisuous mode command */ 197 HNS3_OPC_CFG_PROMISC_MODE = 0x0E01, 198 199 /* Vlan offload commands */ 200 HNS3_OPC_VLAN_PORT_TX_CFG = 0x0F01, 201 HNS3_OPC_VLAN_PORT_RX_CFG = 0x0F02, 202 203 /* MAC commands */ 204 HNS3_OPC_MAC_VLAN_ADD = 0x1000, 205 HNS3_OPC_MAC_VLAN_REMOVE = 0x1001, 206 HNS3_OPC_MAC_VLAN_TYPE_ID = 0x1002, 207 HNS3_OPC_MAC_VLAN_INSERT = 0x1003, 208 HNS3_OPC_MAC_VLAN_ALLOCATE = 0x1004, 209 HNS3_OPC_MAC_ETHTYPE_ADD = 0x1010, 210 211 /* VLAN commands */ 212 HNS3_OPC_VLAN_FILTER_CTRL = 0x1100, 213 HNS3_OPC_VLAN_FILTER_PF_CFG = 0x1101, 214 HNS3_OPC_VLAN_FILTER_VF_CFG = 0x1102, 215 216 /* Flow Director command */ 217 HNS3_OPC_FD_MODE_CTRL = 0x1200, 218 HNS3_OPC_FD_GET_ALLOCATION = 0x1201, 219 HNS3_OPC_FD_KEY_CONFIG = 0x1202, 220 HNS3_OPC_FD_TCAM_OP = 0x1203, 221 HNS3_OPC_FD_AD_OP = 0x1204, 222 HNS3_OPC_FD_COUNTER_OP = 0x1205, 223 224 /* Clear hardware state command */ 225 HNS3_OPC_CLEAR_HW_STATE = 0x700B, 226 227 /* Firmware stats command */ 228 HNS3_OPC_FIRMWARE_COMPAT_CFG = 0x701A, 229 /* Firmware control phy command */ 230 HNS3_OPC_PHY_PARAM_CFG = 0x7025, 231 232 /* SFP command */ 233 HNS3_OPC_GET_SFP_EEPROM = 0x7100, 234 HNS3_OPC_GET_SFP_EXIST = 0x7101, 235 HNS3_OPC_GET_SFP_INFO = 0x7104, 236 237 /* Interrupts commands */ 238 HNS3_OPC_ADD_RING_TO_VECTOR = 0x1503, 239 HNS3_OPC_DEL_RING_TO_VECTOR = 0x1504, 240 241 /* Error INT commands */ 242 HNS3_OPC_MAC_COMMON_INT_EN = 0x030E, 243 HNS3_OPC_TM_SCH_ECC_INT_EN = 0x0829, 244 HNS3_OPC_SSU_ECC_INT_CMD = 0x0989, 245 HNS3_OPC_SSU_COMMON_INT_CMD = 0x098C, 246 HNS3_OPC_PPU_MPF_ECC_INT_CMD = 0x0B40, 247 HNS3_OPC_PPU_MPF_OTHER_INT_CMD = 0x0B41, 248 HNS3_OPC_PPU_PF_OTHER_INT_CMD = 0x0B42, 249 HNS3_OPC_COMMON_ECC_INT_CFG = 0x1505, 250 HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM = 0x1510, 251 HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT = 0x1511, 252 HNS3_OPC_QUERY_CLEAR_PF_RAS_INT = 0x1512, 253 HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, 254 HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, 255 HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, 256 HNS3_OPC_QUERY_ALL_ERR_BD_NUM = 0x1516, 257 HNS3_OPC_QUERY_ALL_ERR_INFO = 0x1517, 258 HNS3_OPC_IGU_EGU_TNL_INT_EN = 0x1803, 259 HNS3_OPC_IGU_COMMON_INT_EN = 0x1806, 260 HNS3_OPC_TM_QCN_MEM_INT_CFG = 0x1A14, 261 HNS3_OPC_PPP_CMD0_INT_CMD = 0x2100, 262 HNS3_OPC_PPP_CMD1_INT_CMD = 0x2101, 263 HNS3_OPC_NCSI_INT_EN = 0x2401, 264 }; 265 266 #define HNS3_CMD_FLAG_IN BIT(0) 267 #define HNS3_CMD_FLAG_OUT BIT(1) 268 #define HNS3_CMD_FLAG_NEXT BIT(2) 269 #define HNS3_CMD_FLAG_WR BIT(3) 270 #define HNS3_CMD_FLAG_NO_INTR BIT(4) 271 #define HNS3_CMD_FLAG_ERR_INTR BIT(5) 272 273 #define HNS3_MPF_RAS_INT_MIN_BD_NUM 10 274 #define HNS3_PF_RAS_INT_MIN_BD_NUM 4 275 #define HNS3_MPF_MSIX_INT_MIN_BD_NUM 10 276 #define HNS3_PF_MSIX_INT_MIN_BD_NUM 4 277 278 #define HNS3_BUF_SIZE_UNIT 256 279 #define HNS3_BUF_MUL_BY 2 280 #define HNS3_BUF_DIV_BY 2 281 #define NEED_RESERVE_TC_NUM 2 282 #define BUF_MAX_PERCENT 100 283 #define BUF_RESERVE_PERCENT 90 284 285 #define HNS3_MAX_TC_NUM 8 286 #define HNS3_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 287 #define HNS3_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 288 #define HNS3_TX_BUFF_RSV_NUM 8 289 struct hns3_tx_buff_alloc_cmd { 290 uint16_t tx_pkt_buff[HNS3_MAX_TC_NUM]; 291 uint8_t tx_buff_rsv[HNS3_TX_BUFF_RSV_NUM]; 292 }; 293 294 struct hns3_rx_priv_buff_cmd { 295 uint16_t buf_num[HNS3_MAX_TC_NUM]; 296 uint16_t shared_buf; 297 uint8_t rsv[6]; 298 }; 299 300 #define HNS3_FW_VERSION_BYTE3_S 24 301 #define HNS3_FW_VERSION_BYTE3_M GENMASK(31, 24) 302 #define HNS3_FW_VERSION_BYTE2_S 16 303 #define HNS3_FW_VERSION_BYTE2_M GENMASK(23, 16) 304 #define HNS3_FW_VERSION_BYTE1_S 8 305 #define HNS3_FW_VERSION_BYTE1_M GENMASK(15, 8) 306 #define HNS3_FW_VERSION_BYTE0_S 0 307 #define HNS3_FW_VERSION_BYTE0_M GENMASK(7, 0) 308 309 enum HNS3_CAPS_BITS { 310 /* 311 * The following capability index definitions must be the same as those 312 * of the firmware. 313 */ 314 HNS3_CAPS_FD_QUEUE_REGION_B = 2, 315 HNS3_CAPS_PTP_B, 316 HNS3_CAPS_SIMPLE_BD_B = 5, 317 HNS3_CAPS_TX_PUSH_B = 6, 318 HNS3_CAPS_PHY_IMP_B = 7, 319 HNS3_CAPS_TQP_TXRX_INDEP_B, 320 HNS3_CAPS_HW_PAD_B, 321 HNS3_CAPS_STASH_B, 322 HNS3_CAPS_UDP_TUNNEL_CSUM_B, 323 HNS3_CAPS_RAS_IMP_B, 324 HNS3_CAPS_RXD_ADV_LAYOUT_B = 15, 325 HNS3_CAPS_TM_B = 19, 326 HNS3_CAPS_GRO_B = 20, 327 HNS3_CAPS_FC_AUTO_B = 30, 328 }; 329 330 /* Capabilities of VF dependent on the PF */ 331 enum HNS3VF_CAPS_BITS { 332 /* 333 * The following capability index definitions must be the same as those 334 * in kernel side PF. 335 */ 336 HNS3VF_CAPS_VLAN_FLT_MOD_B = 0, 337 }; 338 339 enum HNS3_API_CAP_BITS { 340 HNS3_API_CAP_FLEX_RSS_TBL_B, 341 }; 342 343 #define HNS3_QUERY_CAP_LENGTH 3 344 struct hns3_query_version_cmd { 345 uint32_t firmware; 346 uint32_t hardware; 347 uint32_t api_caps; 348 uint32_t caps[HNS3_QUERY_CAP_LENGTH]; /* capabilities of device */ 349 }; 350 351 #define HNS3_RX_PRIV_EN_B 15 352 #define HNS3_TC_NUM_ONE_DESC 4 353 struct hns3_priv_wl { 354 uint16_t high; 355 uint16_t low; 356 }; 357 358 struct hns3_rx_priv_wl_buf { 359 struct hns3_priv_wl tc_wl[HNS3_TC_NUM_ONE_DESC]; 360 }; 361 362 struct hns3_rx_com_thrd { 363 struct hns3_priv_wl com_thrd[HNS3_TC_NUM_ONE_DESC]; 364 }; 365 366 struct hns3_rx_com_wl { 367 struct hns3_priv_wl com_wl; 368 }; 369 370 struct hns3_waterline { 371 uint32_t low; 372 uint32_t high; 373 }; 374 375 struct hns3_tc_thrd { 376 uint32_t low; 377 uint32_t high; 378 }; 379 380 struct hns3_priv_buf { 381 struct hns3_waterline wl; /* Waterline for low and high */ 382 uint32_t buf_size; /* TC private buffer size */ 383 uint32_t tx_buf_size; 384 uint32_t enable; /* Enable TC private buffer or not */ 385 }; 386 387 struct hns3_shared_buf { 388 struct hns3_waterline self; 389 struct hns3_tc_thrd tc_thrd[HNS3_MAX_TC_NUM]; 390 uint32_t buf_size; 391 }; 392 393 struct hns3_pkt_buf_alloc { 394 struct hns3_priv_buf priv_buf[HNS3_MAX_TC_NUM]; 395 struct hns3_shared_buf s_buf; 396 }; 397 398 #define HNS3_PF_STATE_DONE_B 0 399 #define HNS3_PF_STATE_MAIN_B 1 400 #define HNS3_PF_STATE_BOND_B 2 401 #define HNS3_PF_STATE_MAC_N_B 6 402 #define HNS3_PF_MAC_NUM_MASK 0x3 403 #define HNS3_PF_STATE_MAIN BIT(HNS3_PF_STATE_MAIN_B) 404 #define HNS3_PF_STATE_DONE BIT(HNS3_PF_STATE_DONE_B) 405 #define HNS3_VF_RST_STATE_NUM 4 406 struct hns3_func_status_cmd { 407 uint32_t vf_rst_state[HNS3_VF_RST_STATE_NUM]; 408 uint8_t pf_state; 409 uint8_t mac_id; 410 uint8_t rsv1; 411 uint8_t pf_cnt_in_mac; 412 uint8_t pf_num; 413 uint8_t vf_num; 414 uint8_t rsv[2]; 415 }; 416 417 #define HNS3_PF_VEC_NUM_S 0 418 #define HNS3_PF_VEC_NUM_M GENMASK(15, 0) 419 #define HNS3_MIN_VECTOR_NUM 2 /* one for msi-x, another for IO */ 420 struct hns3_pf_res_cmd { 421 uint16_t tqp_num; 422 uint16_t buf_size; 423 uint16_t msixcap_localid_ba_nic; 424 uint16_t nic_pf_intr_vector_number; 425 uint16_t roce_pf_intr_vector_number; 426 uint16_t pf_own_fun_number; 427 uint16_t tx_buf_size; 428 uint16_t dv_buf_size; 429 /* number of queues that exceed 1024 */ 430 uint16_t ext_tqp_num; 431 uint16_t roh_pf_intr_vector_number; 432 uint32_t rsv[1]; 433 }; 434 435 #define HNS3_VF_VEC_NUM_S 0 436 #define HNS3_VF_VEC_NUM_M GENMASK(7, 0) 437 struct hns3_vf_res_cmd { 438 uint16_t tqp_num; 439 uint16_t reserved; 440 uint16_t msixcap_localid_ba_nic; 441 uint16_t msixcap_localid_ba_rocee; 442 uint16_t vf_intr_vector_number; 443 uint16_t rsv[7]; 444 }; 445 446 #define HNS3_UMV_SPC_ALC_B 0 447 struct hns3_umv_spc_alc_cmd { 448 uint8_t allocate; 449 uint8_t rsv1[3]; 450 uint32_t space_size; 451 uint8_t rsv2[16]; 452 }; 453 454 #define HNS3_CFG_OFFSET_S 0 455 #define HNS3_CFG_OFFSET_M GENMASK(19, 0) 456 #define HNS3_CFG_RD_LEN_S 24 457 #define HNS3_CFG_RD_LEN_M GENMASK(27, 24) 458 #define HNS3_CFG_RD_LEN_BYTES 16 459 #define HNS3_CFG_RD_LEN_UNIT 4 460 461 #define HNS3_CFG_TC_NUM_S 8 462 #define HNS3_CFG_TC_NUM_M GENMASK(15, 8) 463 #define HNS3_CFG_TQP_DESC_N_S 16 464 #define HNS3_CFG_TQP_DESC_N_M GENMASK(31, 16) 465 #define HNS3_CFG_PHY_ADDR_S 0 466 #define HNS3_CFG_PHY_ADDR_M GENMASK(7, 0) 467 #define HNS3_CFG_MEDIA_TP_S 8 468 #define HNS3_CFG_MEDIA_TP_M GENMASK(15, 8) 469 #define HNS3_CFG_RX_BUF_LEN_S 16 470 #define HNS3_CFG_RX_BUF_LEN_M GENMASK(31, 16) 471 #define HNS3_CFG_MAC_ADDR_H_S 0 472 #define HNS3_CFG_MAC_ADDR_H_M GENMASK(15, 0) 473 #define HNS3_CFG_DEFAULT_SPEED_S 16 474 #define HNS3_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 475 #define HNS3_CFG_RSS_SIZE_S 24 476 #define HNS3_CFG_RSS_SIZE_M GENMASK(31, 24) 477 #define HNS3_CFG_SPEED_ABILITY_S 0 478 #define HNS3_CFG_SPEED_ABILITY_M GENMASK(7, 0) 479 #define HNS3_CFG_UMV_TBL_SPACE_S 16 480 #define HNS3_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 481 #define HNS3_CFG_EXT_RSS_SIZE_S 0 482 #define HNS3_CFG_EXT_RSS_SIZE_M GENMASK(3, 0) 483 484 #define HNS3_ACCEPT_TAG1_B 0 485 #define HNS3_ACCEPT_UNTAG1_B 1 486 #define HNS3_PORT_INS_TAG1_EN_B 2 487 #define HNS3_PORT_INS_TAG2_EN_B 3 488 #define HNS3_CFG_NIC_ROCE_SEL_B 4 489 #define HNS3_ACCEPT_TAG2_B 5 490 #define HNS3_ACCEPT_UNTAG2_B 6 491 #define HNS3_TAG_SHIFT_MODE_EN_B 7 492 493 #define HNS3_REM_TAG1_EN_B 0 494 #define HNS3_REM_TAG2_EN_B 1 495 #define HNS3_SHOW_TAG1_EN_B 2 496 #define HNS3_SHOW_TAG2_EN_B 3 497 #define HNS3_DISCARD_TAG1_EN_B 5 498 #define HNS3_DISCARD_TAG2_EN_B 6 499 500 /* Factor used to calculate offset and bitmap of VF num */ 501 #define HNS3_VF_NUM_PER_CMD 64 502 #define HNS3_VF_NUM_PER_BYTE 8 503 504 struct hns3_cfg_param_cmd { 505 uint32_t offset; 506 uint32_t rsv; 507 uint32_t param[4]; 508 }; 509 510 #define HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM 8 511 struct hns3_vport_vtag_rx_cfg_cmd { 512 uint8_t vport_vlan_cfg; 513 uint8_t vf_offset; 514 uint8_t rsv1[6]; 515 uint8_t vf_bitmap[HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM]; 516 uint8_t rsv2[8]; 517 }; 518 519 struct hns3_vport_vtag_tx_cfg_cmd { 520 uint8_t vport_vlan_cfg; 521 uint8_t vf_offset; 522 uint8_t rsv1[2]; 523 uint16_t def_vlan_tag1; 524 uint16_t def_vlan_tag2; 525 uint8_t vf_bitmap[8]; 526 uint8_t rsv2[8]; 527 }; 528 529 530 struct hns3_vlan_filter_ctrl_cmd { 531 uint8_t vlan_type; 532 uint8_t vlan_fe; 533 uint8_t rsv1[2]; 534 uint8_t vf_id; 535 uint8_t rsv2[19]; 536 }; 537 538 #define HNS3_VLAN_OFFSET_BITMAP_NUM 20 539 struct hns3_vlan_filter_pf_cfg_cmd { 540 uint8_t vlan_offset; 541 uint8_t vlan_cfg; 542 uint8_t rsv[2]; 543 uint8_t vlan_offset_bitmap[HNS3_VLAN_OFFSET_BITMAP_NUM]; 544 }; 545 546 #define HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM 16 547 struct hns3_vlan_filter_vf_cfg_cmd { 548 uint16_t vlan_id; 549 uint8_t resp_code; 550 uint8_t rsv; 551 uint8_t vlan_cfg; 552 uint8_t rsv1[3]; 553 uint8_t vf_bitmap[HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM]; 554 }; 555 556 struct hns3_tx_vlan_type_cfg_cmd { 557 uint16_t ot_vlan_type; 558 uint16_t in_vlan_type; 559 uint8_t rsv[20]; 560 }; 561 562 struct hns3_rx_vlan_type_cfg_cmd { 563 uint16_t ot_fst_vlan_type; 564 uint16_t ot_sec_vlan_type; 565 uint16_t in_fst_vlan_type; 566 uint16_t in_sec_vlan_type; 567 uint8_t rsv[16]; 568 }; 569 570 #define HNS3_TSO_MSS_MIN_S 0 571 #define HNS3_TSO_MSS_MIN_M GENMASK(13, 0) 572 573 #define HNS3_TSO_MSS_MAX_S 16 574 #define HNS3_TSO_MSS_MAX_M GENMASK(29, 16) 575 576 struct hns3_cfg_tso_status_cmd { 577 rte_le16_t tso_mss_min; 578 rte_le16_t tso_mss_max; 579 uint8_t rsv[20]; 580 }; 581 582 #define HNS3_GRO_EN_B 0 583 struct hns3_cfg_gro_status_cmd { 584 rte_le16_t gro_en; 585 uint8_t rsv[22]; 586 }; 587 588 #define HNS3_TSO_MSS_MIN 256 589 #define HNS3_TSO_MSS_MAX 9668 590 591 #define HNS3_RSS_HASH_KEY_OFFSET_B 4 592 593 #define HNS3_RSS_HASH_KEY_NUM 16 594 /* Configure the algorithm mode and Hash Key, opcode:0x0D01 */ 595 struct hns3_rss_generic_config_cmd { 596 /* Hash_algorithm(8.0~8.3), hash_key_offset(8.4~8.7) */ 597 uint8_t hash_config; 598 uint8_t rsv[7]; 599 uint8_t hash_key[HNS3_RSS_HASH_KEY_NUM]; 600 }; 601 602 /* Configure the tuple selection for RSS hash input, opcode:0x0D02 */ 603 struct hns3_rss_input_tuple_cmd { 604 uint64_t tuple_field; 605 uint8_t rsv[16]; 606 }; 607 608 #define HNS3_RSS_CFG_TBL_SIZE 16 609 #define HNS3_RSS_CFG_TBL_SIZE_H 4 610 #define HNS3_RSS_CFG_TBL_BW_H 2 611 #define HNS3_RSS_CFG_TBL_BW_L 8 612 #define HNS3_RSS_CFG_TBL_BW_H_M 0x3 613 614 /* Configure the indirection table, opcode:0x0D07 */ 615 struct hns3_rss_indirection_table_cmd { 616 uint16_t start_table_index; /* Bit3~0 must be 0x0. */ 617 uint16_t rss_set_bitmap; 618 uint8_t rss_result_h[HNS3_RSS_CFG_TBL_SIZE_H]; 619 uint8_t rss_result_l[HNS3_RSS_CFG_TBL_SIZE]; 620 }; 621 622 #define HNS3_RSS_TC_OFFSET_S 0 623 #define HNS3_RSS_TC_OFFSET_M GENMASK(10, 0) 624 #define HNS3_RSS_TC_SIZE_MSB_S 11 625 #define HNS3_RSS_TC_SIZE_MSB_OFFSET 3 626 #define HNS3_RSS_TC_SIZE_S 12 627 #define HNS3_RSS_TC_SIZE_M GENMASK(14, 12) 628 #define HNS3_RSS_TC_VALID_B 15 629 630 /* Configure the tc_size and tc_offset, opcode:0x0D08 */ 631 struct hns3_rss_tc_mode_cmd { 632 uint16_t rss_tc_mode[HNS3_MAX_TC_NUM]; 633 uint8_t rsv[8]; 634 }; 635 636 #define HNS3_LINK_STATUS_UP_B 0 637 #define HNS3_LINK_STATUS_UP_M BIT(HNS3_LINK_STATUS_UP_B) 638 struct hns3_link_status_cmd { 639 uint8_t status; 640 uint8_t rsv[23]; 641 }; 642 643 struct hns3_promisc_param { 644 uint8_t vf_id; 645 uint8_t enable; 646 }; 647 648 #define HNS3_PROMISC_TX_EN_B BIT(4) 649 #define HNS3_PROMISC_RX_EN_B BIT(5) 650 #define HNS3_PROMISC_EN_B 1 651 #define HNS3_PROMISC_EN_ALL 0x7 652 #define HNS3_PROMISC_EN_UC 0x1 653 #define HNS3_PROMISC_EN_MC 0x2 654 #define HNS3_PROMISC_EN_BC 0x4 655 struct hns3_promisc_cfg_cmd { 656 uint8_t flag; 657 uint8_t vf_id; 658 uint16_t rsv0; 659 uint8_t rsv1[20]; 660 }; 661 662 enum hns3_promisc_type { 663 HNS3_UNICAST = 1, 664 HNS3_MULTICAST = 2, 665 HNS3_BROADCAST = 3, 666 }; 667 668 #define HNS3_LINK_EVENT_REPORT_EN_B 0 669 #define HNS3_NCSI_ERROR_REPORT_EN_B 1 670 #define HNS3_FIRMWARE_PHY_DRIVER_EN_B 2 671 672 #define HNS3_LLRS_FEC_EN_B 5 673 #define HNS3_MAC_FC_AUTONEG_EN_B 6 674 675 struct hns3_firmware_compat_cmd { 676 uint32_t compat; 677 uint8_t rsv[20]; 678 }; 679 680 /* Bitmap flags in supported, advertising and lp_advertising */ 681 #define HNS3_PHY_LINK_SPEED_10M_HD_BIT BIT(0) 682 #define HNS3_PHY_LINK_SPEED_10M_BIT BIT(1) 683 #define HNS3_PHY_LINK_SPEED_100M_HD_BIT BIT(2) 684 #define HNS3_PHY_LINK_SPEED_100M_BIT BIT(3) 685 #define HNS3_PHY_LINK_SPEED_1000M_BIT BIT(5) 686 #define HNS3_PHY_LINK_MODE_AUTONEG_BIT BIT(6) 687 #define HNS3_PHY_LINK_MODE_PAUSE_BIT BIT(13) 688 #define HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT BIT(14) 689 #define HNS3_PHY_LINK_MODE_PAUSE_S 13 690 691 #define HNS3_PHY_PARAM_CFG_BD_NUM 2 692 struct hns3_phy_params_bd0_cmd { 693 uint32_t speed; 694 #define HNS3_PHY_DUPLEX_CFG_B 0 695 uint8_t duplex; 696 #define HNS3_PHY_AUTONEG_CFG_B 0 697 uint8_t autoneg; 698 uint8_t eth_tp_mdix; 699 uint8_t eth_tp_mdix_ctrl; 700 uint8_t port; 701 uint8_t transceiver; 702 uint8_t phy_address; 703 uint8_t rsv; 704 uint32_t supported; 705 uint32_t advertising; 706 uint32_t lp_advertising; 707 }; 708 709 struct hns3_phy_params_bd1_cmd { 710 uint8_t master_slave_cfg; 711 uint8_t master_slave_state; 712 uint8_t rsv1[2]; 713 uint32_t rsv2[5]; 714 }; 715 716 #define HNS3_MAC_TX_EN_B 6 717 #define HNS3_MAC_RX_EN_B 7 718 #define HNS3_MAC_PAD_TX_B 11 719 #define HNS3_MAC_PAD_RX_B 12 720 #define HNS3_MAC_1588_TX_B 13 721 #define HNS3_MAC_1588_RX_B 14 722 #define HNS3_MAC_APP_LP_B 15 723 #define HNS3_MAC_LINE_LP_B 16 724 #define HNS3_MAC_FCS_TX_B 17 725 #define HNS3_MAC_RX_OVERSIZE_TRUNCATE_B 18 726 #define HNS3_MAC_RX_FCS_STRIP_B 19 727 #define HNS3_MAC_RX_FCS_B 20 728 #define HNS3_MAC_TX_UNDER_MIN_ERR_B 21 729 #define HNS3_MAC_TX_OVERSIZE_TRUNCATE_B 22 730 731 struct hns3_config_mac_mode_cmd { 732 uint32_t txrx_pad_fcs_loop_en; 733 uint8_t rsv[20]; 734 }; 735 736 #define HNS3_CFG_SPEED_10M 6 737 #define HNS3_CFG_SPEED_100M 7 738 #define HNS3_CFG_SPEED_1G 0 739 #define HNS3_CFG_SPEED_10G 1 740 #define HNS3_CFG_SPEED_25G 2 741 #define HNS3_CFG_SPEED_40G 3 742 #define HNS3_CFG_SPEED_50G 4 743 #define HNS3_CFG_SPEED_100G 5 744 #define HNS3_CFG_SPEED_200G 8 745 746 #define HNS3_CFG_SPEED_S 0 747 #define HNS3_CFG_SPEED_M GENMASK(5, 0) 748 #define HNS3_CFG_DUPLEX_B 7 749 #define HNS3_CFG_DUPLEX_M BIT(HNS3_CFG_DUPLEX_B) 750 751 #define HNS3_CFG_MAC_SPEED_CHANGE_EN_B 0 752 753 struct hns3_config_mac_speed_dup_cmd { 754 uint8_t speed_dup; 755 uint8_t mac_change_fec_en; 756 uint8_t rsv[22]; 757 }; 758 759 #define HNS3_TQP_ENABLE_B 0 760 761 #define HNS3_MAC_CFG_AN_EN_B 0 762 #define HNS3_MAC_CFG_AN_INT_EN_B 1 763 #define HNS3_MAC_CFG_AN_INT_MSK_B 2 764 #define HNS3_MAC_CFG_AN_INT_CLR_B 3 765 #define HNS3_MAC_CFG_AN_RST_B 4 766 767 #define HNS3_MAC_CFG_AN_EN BIT(HNS3_MAC_CFG_AN_EN_B) 768 769 struct hns3_config_auto_neg_cmd { 770 uint32_t cfg_an_cmd_flag; 771 uint8_t rsv[20]; 772 }; 773 774 #define HNS3_SFP_INFO_BD0_LEN 20UL 775 #define HNS3_SFP_INFO_BDX_LEN 24UL 776 777 struct hns3_sfp_info_bd0_cmd { 778 uint16_t offset; 779 uint16_t read_len; 780 uint8_t data[HNS3_SFP_INFO_BD0_LEN]; 781 }; 782 783 struct hns3_sfp_type { 784 uint8_t type; 785 uint8_t ext_type; 786 }; 787 788 /* Bitmap flags in supported_speed */ 789 #define HNS3_FIBER_LINK_SPEED_1G_BIT BIT(0) 790 #define HNS3_FIBER_LINK_SPEED_10G_BIT BIT(1) 791 #define HNS3_FIBER_LINK_SPEED_25G_BIT BIT(2) 792 #define HNS3_FIBER_LINK_SPEED_50G_BIT BIT(3) 793 #define HNS3_FIBER_LINK_SPEED_100G_BIT BIT(4) 794 #define HNS3_FIBER_LINK_SPEED_40G_BIT BIT(5) 795 #define HNS3_FIBER_LINK_SPEED_100M_BIT BIT(6) 796 #define HNS3_FIBER_LINK_SPEED_10M_BIT BIT(7) 797 #define HNS3_FIBER_LINK_SPEED_200G_BIT BIT(8) 798 799 #define HNS3_FIBER_FEC_AUTO_BIT BIT(0) 800 #define HNS3_FIBER_FEC_BASER_BIT BIT(1) 801 #define HNS3_FIBER_FEC_RS_BIT BIT(2) 802 #define HNS3_FIBER_FEC_LLRS_BIT BIT(3) 803 #define HNS3_FIBER_FEC_NOFEC_BIT BIT(4) 804 805 /* Flags for pause status field */ 806 #define HNS3_FIBER_LOCAL_PAUSE_BIT BIT(0) 807 #define HNS3_FIBER_LOCAL_ASYM_PAUSE_BIT BIT(1) 808 #define HNS3_FIBER_LP_PAUSE_BIT BIT(2) 809 #define HNS3_FIBER_LP_ASYM_PAUSE_BIT BIT(3) 810 #define HNS3_FIBER_LOCAL_PAUSE_MASK (HNS3_FIBER_LOCAL_PAUSE_BIT | \ 811 HNS3_FIBER_LOCAL_ASYM_PAUSE_BIT) 812 #define HNS3_FIBER_LP_PAUSE_MASK (HNS3_FIBER_LP_PAUSE_BIT | \ 813 HNS3_FIBER_LP_ASYM_PAUSE_BIT) 814 #define HNS3_FIBER_LP_PAUSE_S 2 815 816 struct hns3_sfp_info_cmd { 817 uint32_t sfp_speed; 818 uint8_t query_type; /* 0: sfp speed, 1: active */ 819 uint8_t active_fec; /* current FEC mode */ 820 uint8_t autoneg; /* current autoneg state */ 821 /* 0: not support autoneg, 1: support autoneg */ 822 uint8_t autoneg_ability; 823 uint32_t supported_speed; /* speed supported by current media */ 824 uint32_t module_type; 825 uint8_t fec_ability; /* supported fec modes, see HNS3_FIBER_FEC_XXX_BIT */ 826 uint8_t rsv0; 827 uint8_t pause_status; 828 uint8_t rsv1[5]; 829 }; 830 831 #define HNS3_MAC_CFG_FEC_AUTO_EN_B 0 832 #define HNS3_MAC_CFG_FEC_MODE_S 1 833 #define HNS3_MAC_CFG_FEC_MODE_M GENMASK(3, 1) 834 #define HNS3_MAC_FEC_OFF 0 835 #define HNS3_MAC_FEC_BASER 1 836 #define HNS3_MAC_FEC_RS 2 837 #define HNS3_MAC_FEC_LLRS 3 838 839 /* Configure FEC mode, opcode:0x031A */ 840 struct hns3_config_fec_cmd { 841 uint8_t fec_mode; 842 uint8_t rsv[23]; 843 }; 844 845 #define HNS3_MAC_MGR_MASK_VLAN_B BIT(0) 846 #define HNS3_MAC_MGR_MASK_MAC_B BIT(1) 847 #define HNS3_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 848 #define HNS3_MAC_ETHERTYPE_LLDP 0x88cc 849 850 struct hns3_mac_mgr_tbl_entry_cmd { 851 uint8_t flags; 852 uint8_t resp_code; 853 uint16_t vlan_tag; 854 uint32_t mac_addr_hi32; 855 uint16_t mac_addr_lo16; 856 uint16_t rsv1; 857 uint16_t ethter_type; 858 uint16_t egress_port; 859 uint16_t egress_queue; 860 uint8_t sw_port_id_aware; 861 uint8_t rsv2; 862 uint8_t i_port_bitmap; 863 uint8_t i_port_direction; 864 uint8_t rsv3[2]; 865 }; 866 867 struct hns3_cfg_com_tqp_queue_cmd { 868 uint16_t tqp_id; 869 uint16_t stream_id; 870 uint8_t enable; 871 uint8_t rsv[19]; 872 }; 873 874 #define HNS3_TQP_MAP_TYPE_PF 0 875 #define HNS3_TQP_MAP_TYPE_VF 1 876 #define HNS3_TQP_MAP_TYPE_B 0 877 #define HNS3_TQP_MAP_EN_B 1 878 879 struct hns3_tqp_map_cmd { 880 uint16_t tqp_id; /* Absolute tqp id for in this pf */ 881 uint8_t tqp_vf; /* VF id */ 882 uint8_t tqp_flag; /* Indicate it's pf or vf tqp */ 883 uint16_t tqp_vid; /* Virtual id in this pf/vf */ 884 uint8_t rsv[18]; 885 }; 886 887 enum hns3_ring_type { 888 HNS3_RING_TYPE_TX, 889 HNS3_RING_TYPE_RX 890 }; 891 892 enum hns3_int_gl_idx { 893 HNS3_RING_GL_RX, 894 HNS3_RING_GL_TX, 895 HNS3_RING_GL_IMMEDIATE = 3 896 }; 897 898 #define HNS3_RING_GL_IDX_S 0 899 #define HNS3_RING_GL_IDX_M GENMASK(1, 0) 900 901 #define HNS3_VECTOR_ELEMENTS_PER_CMD 10 902 903 #define HNS3_INT_TYPE_S 0 904 #define HNS3_INT_TYPE_M GENMASK(1, 0) 905 #define HNS3_TQP_ID_S 2 906 #define HNS3_TQP_ID_M GENMASK(12, 2) 907 #define HNS3_INT_GL_IDX_S 13 908 #define HNS3_INT_GL_IDX_M GENMASK(14, 13) 909 #define HNS3_TQP_INT_ID_L_S 0 910 #define HNS3_TQP_INT_ID_L_M GENMASK(7, 0) 911 #define HNS3_TQP_INT_ID_H_S 8 912 #define HNS3_TQP_INT_ID_H_M GENMASK(15, 8) 913 struct hns3_ctrl_vector_chain_cmd { 914 uint8_t int_vector_id; /* the low order of the interrupt id */ 915 uint8_t int_cause_num; 916 uint16_t tqp_type_and_id[HNS3_VECTOR_ELEMENTS_PER_CMD]; 917 uint8_t vfid; 918 uint8_t int_vector_id_h; /* the high order of the interrupt id */ 919 }; 920 921 struct hns3_config_max_frm_size_cmd { 922 uint16_t max_frm_size; 923 uint8_t min_frm_size; 924 uint8_t rsv[21]; 925 }; 926 927 enum hns3_mac_vlan_tbl_opcode { 928 HNS3_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 929 HNS3_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 930 HNS3_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 931 HNS3_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 932 }; 933 934 enum hns3_mac_vlan_add_resp_code { 935 HNS3_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */ 936 HNS3_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */ 937 }; 938 939 #define HNS3_MC_MAC_VLAN_OPS_DESC_NUM 3 940 #define HNS3_UC_MAC_VLAN_OPS_DESC_NUM 1 941 942 #define HNS3_MAC_VLAN_BIT0_EN_B 0 943 #define HNS3_MAC_VLAN_BIT1_EN_B 1 944 #define HNS3_MAC_EPORT_SW_EN_B 12 945 #define HNS3_MAC_EPORT_TYPE_B 11 946 #define HNS3_MAC_EPORT_VFID_S 3 947 #define HNS3_MAC_EPORT_VFID_M GENMASK(10, 3) 948 #define HNS3_MAC_EPORT_PFID_S 0 949 #define HNS3_MAC_EPORT_PFID_M GENMASK(2, 0) 950 struct hns3_mac_vlan_tbl_entry_cmd { 951 uint8_t flags; 952 uint8_t resp_code; 953 uint16_t vlan_tag; 954 uint32_t mac_addr_hi32; 955 uint16_t mac_addr_lo16; 956 uint16_t rsv1; 957 uint8_t entry_type; 958 uint8_t mc_mac_en; 959 uint16_t egress_port; 960 uint16_t egress_queue; 961 uint8_t rsv2[6]; 962 }; 963 964 #define HNS3_TQP_RESET_B 0 965 struct hns3_reset_tqp_queue_cmd { 966 uint16_t tqp_id; 967 uint8_t reset_req; 968 uint8_t ready_to_reset; 969 uint8_t queue_direction; 970 uint8_t rsv[19]; 971 }; 972 973 #define HNS3_CFG_RESET_MAC_B 3 974 #define HNS3_CFG_RESET_FUNC_B 7 975 #define HNS3_CFG_RESET_RCB_B 1 976 struct hns3_reset_cmd { 977 uint8_t mac_func_reset; 978 uint8_t fun_reset_vfid; 979 uint8_t fun_reset_rcb; 980 uint8_t rsv1; 981 uint16_t fun_reset_rcb_vqid_start; 982 uint16_t fun_reset_rcb_vqid_num; 983 uint8_t fun_reset_rcb_return_status; 984 uint8_t rsv2[15]; 985 }; 986 987 #define HNS3_QUERY_DEV_SPECS_BD_NUM 4 988 struct hns3_dev_specs_0_cmd { 989 uint32_t rsv0; 990 uint32_t mac_entry_num; 991 uint32_t mng_entry_num; 992 uint16_t rss_ind_tbl_size; 993 uint16_t rss_key_size; 994 uint16_t intr_ql_max; 995 uint8_t max_non_tso_bd_num; 996 uint8_t rsv1; 997 uint32_t max_tm_rate; 998 }; 999 1000 struct hns3_dev_specs_1_cmd { 1001 uint8_t rsv0[12]; 1002 uint8_t min_tx_pkt_len; 1003 uint8_t rsv1[11]; 1004 }; 1005 1006 struct hns3_query_rpu_cmd { 1007 uint32_t tc_queue_num; 1008 uint32_t rsv1[2]; 1009 uint32_t rpu_rx_pkt_drop_cnt; 1010 uint32_t rsv2[2]; 1011 }; 1012 1013 #define HNS3_OPC_SSU_DROP_REG_NUM 2 1014 1015 struct hns3_query_ssu_cmd { 1016 uint8_t rxtx; 1017 uint8_t rsv[3]; 1018 uint32_t full_drop_cnt; 1019 uint32_t part_drop_cnt; 1020 uint32_t oq_drop_cnt; 1021 uint32_t rev1[2]; 1022 }; 1023 1024 #define HNS3_PTP_ENABLE_B 0 1025 #define HNS3_PTP_TX_ENABLE_B 1 1026 #define HNS3_PTP_RX_ENABLE_B 2 1027 1028 #define HNS3_PTP_TYPE_S 0 1029 #define HNS3_PTP_TYPE_M (0x3 << HNS3_PTP_TYPE_S) 1030 1031 #define ALL_PTP_V2_TYPE 0xF 1032 #define HNS3_PTP_MESSAGE_TYPE_S 0 1033 #define HNS3_PTP_MESSAGE_TYPE_M (0xF << HNS3_PTP_MESSAGE_TYPE_S) 1034 1035 #define PTP_TYPE_L2_V2_TYPE 0 1036 1037 struct hns3_ptp_mode_cfg_cmd { 1038 uint8_t enable; 1039 uint8_t ptp_type; 1040 uint8_t v2_message_type_1; 1041 uint8_t v2_message_type_0; 1042 uint8_t rsv[20]; 1043 }; 1044 1045 struct hns3_ptp_int_cmd { 1046 uint8_t int_en; 1047 uint8_t rsvd[23]; 1048 }; 1049 1050 #define HNS3_MAX_TQP_NUM_HIP08_PF 64 1051 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 1052 #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 1053 #define HNS3_DEFAULT_DV 0xA000 /* 40k byte */ 1054 #define HNS3_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 1055 #define HNS3_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */ 1056 1057 #define HNS3_TYPE_CRQ 0 1058 #define HNS3_TYPE_CSQ 1 1059 1060 #define HNS3_NIC_SW_RST_RDY_B 16 1061 #define HNS3_NIC_SW_RST_RDY BIT(HNS3_NIC_SW_RST_RDY_B) 1062 #define HNS3_NIC_CMQ_DESC_NUM 1024 1063 #define HNS3_NIC_CMQ_DESC_NUM_S 3 1064 1065 #define HNS3_CMD_SEND_SYNC(flag) \ 1066 ((flag) & HNS3_CMD_FLAG_NO_INTR) 1067 1068 void hns3_cmd_reuse_desc(struct hns3_cmd_desc *desc, bool is_read); 1069 void hns3_cmd_setup_basic_desc(struct hns3_cmd_desc *desc, 1070 enum hns3_opcode_type opcode, bool is_read); 1071 int hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num); 1072 int hns3_cmd_init_queue(struct hns3_hw *hw); 1073 int hns3_cmd_init(struct hns3_hw *hw); 1074 void hns3_cmd_destroy_queue(struct hns3_hw *hw); 1075 void hns3_cmd_uninit(struct hns3_hw *hw); 1076 1077 #endif /* HNS3_CMD_H */ 1078