1 /* $NetBSD: viaide.c,v 1.91 2025/01/23 22:47:38 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.91 2025/01/23 22:47:38 andvar Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/pci/pciide_apollo_reg.h> 39 40 static int via_pcib_match(const struct pci_attach_args *); 41 static void via_chip_map(struct pciide_softc *, 42 const struct pci_attach_args *); 43 static void via_mapchan(const struct pci_attach_args *, 44 struct pciide_channel *, 45 pcireg_t, int (*)(void *)); 46 static void via_mapregs_compat_native(const struct pci_attach_args *, 47 struct pciide_channel *); 48 static int via_sata_chip_map_common(struct pciide_softc *, 49 const struct pci_attach_args *); 50 static void via_sata_chip_map(struct pciide_softc *, 51 const struct pci_attach_args *, int); 52 static void via_sata_chip_map_6(struct pciide_softc *, 53 const struct pci_attach_args *); 54 static void via_sata_chip_map_7(struct pciide_softc *, 55 const struct pci_attach_args *); 56 static void via_sata_chip_map_new(struct pciide_softc *, 57 const struct pci_attach_args *); 58 static void via_setup_channel(struct ata_channel *); 59 60 static int viaide_match(device_t, cfdata_t, void *); 61 static void viaide_attach(device_t, device_t, void *); 62 static const struct pciide_product_desc * 63 viaide_lookup(pcireg_t); 64 static bool viaide_suspend(device_t, const pmf_qual_t *); 65 static bool viaide_resume(device_t, const pmf_qual_t *); 66 67 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 68 viaide_match, viaide_attach, pciide_detach, NULL); 69 70 static const struct pciide_product_desc pciide_amd_products[] = { 71 { PCI_PRODUCT_AMD_PBC756_IDE, 72 0, 73 "AMD AMD756 IDE Controller", 74 via_chip_map 75 }, 76 { PCI_PRODUCT_AMD_PBC766_IDE, 77 0, 78 "AMD AMD766 IDE Controller", 79 via_chip_map 80 }, 81 { PCI_PRODUCT_AMD_PBC768_IDE, 82 0, 83 "AMD AMD768 IDE Controller", 84 via_chip_map 85 }, 86 { PCI_PRODUCT_AMD_PBC8111_IDE, 87 0, 88 "AMD AMD8111 IDE Controller", 89 via_chip_map 90 }, 91 { PCI_PRODUCT_AMD_CS5536_IDE, 92 0, 93 "AMD CS5536 IDE Controller", 94 via_chip_map 95 }, 96 { 0, 97 0, 98 NULL, 99 NULL 100 } 101 }; 102 103 static const struct pciide_product_desc pciide_nvidia_products[] = { 104 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 105 0, 106 "NVIDIA nForce IDE Controller", 107 via_chip_map 108 }, 109 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 110 0, 111 "NVIDIA nForce2 IDE Controller", 112 via_chip_map 113 }, 114 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 115 0, 116 "NVIDIA nForce2 Ultra 400 IDE Controller", 117 via_chip_map 118 }, 119 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 120 0, 121 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 122 via_sata_chip_map_6 123 }, 124 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 125 0, 126 "NVIDIA nForce3 IDE Controller", 127 via_chip_map 128 }, 129 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 130 0, 131 "NVIDIA nForce3 250 IDE Controller", 132 via_chip_map 133 }, 134 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 135 0, 136 "NVIDIA nForce3 250 Serial ATA Controller", 137 via_sata_chip_map_6 138 }, 139 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 140 0, 141 "NVIDIA nForce3 250 Serial ATA Controller", 142 via_sata_chip_map_6 143 }, 144 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 145 0, 146 "NVIDIA nForce4 IDE Controller", 147 via_chip_map 148 }, 149 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 150 0, 151 "NVIDIA nForce4 Serial ATA Controller", 152 via_sata_chip_map_6 153 }, 154 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 155 0, 156 "NVIDIA nForce4 Serial ATA Controller", 157 via_sata_chip_map_6 158 }, 159 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 160 0, 161 "NVIDIA nForce430 IDE Controller", 162 via_chip_map 163 }, 164 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 165 0, 166 "NVIDIA nForce430 Serial ATA Controller", 167 via_sata_chip_map_6 168 }, 169 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 170 0, 171 "NVIDIA nForce430 Serial ATA Controller", 172 via_sata_chip_map_6 173 }, 174 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 175 0, 176 "NVIDIA MCP04 IDE Controller", 177 via_chip_map 178 }, 179 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 180 0, 181 "NVIDIA MCP04 Serial ATA Controller", 182 via_sata_chip_map_6 183 }, 184 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 185 0, 186 "NVIDIA MCP04 Serial ATA Controller", 187 via_sata_chip_map_6 188 }, 189 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 190 0, 191 "NVIDIA MCP55 IDE Controller", 192 via_chip_map 193 }, 194 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 195 0, 196 "NVIDIA MCP55 Serial ATA Controller", 197 via_sata_chip_map_6 198 }, 199 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 200 0, 201 "NVIDIA MCP55 Serial ATA Controller", 202 via_sata_chip_map_6 203 }, 204 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 205 0, 206 "NVIDIA MCP61 IDE Controller", 207 via_chip_map 208 }, 209 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 210 0, 211 "NVIDIA MCP65 IDE Controller", 212 via_chip_map 213 }, 214 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 215 0, 216 "NVIDIA MCP73 IDE Controller", 217 via_chip_map 218 }, 219 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 220 0, 221 "NVIDIA MCP77 IDE Controller", 222 via_chip_map 223 }, 224 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 225 0, 226 "NVIDIA MCP61 Serial ATA Controller", 227 via_sata_chip_map_6 228 }, 229 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 230 0, 231 "NVIDIA MCP61 Serial ATA Controller", 232 via_sata_chip_map_6 233 }, 234 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 235 0, 236 "NVIDIA MCP61 Serial ATA Controller", 237 via_sata_chip_map_6 238 }, 239 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 240 0, 241 "NVIDIA MCP65 Serial ATA Controller", 242 via_sata_chip_map_6 243 }, 244 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 245 0, 246 "NVIDIA MCP65 Serial ATA Controller", 247 via_sata_chip_map_6 248 }, 249 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 250 0, 251 "NVIDIA MCP65 Serial ATA Controller", 252 via_sata_chip_map_6 253 }, 254 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 255 0, 256 "NVIDIA MCP65 Serial ATA Controller", 257 via_sata_chip_map_6 258 }, 259 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 260 0, 261 "NVIDIA MCP67 IDE Controller", 262 via_chip_map, 263 }, 264 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 265 0, 266 "NVIDIA MCP67 Serial ATA Controller", 267 via_sata_chip_map_6, 268 }, 269 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 270 0, 271 "NVIDIA MCP67 Serial ATA Controller", 272 via_sata_chip_map_6, 273 }, 274 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 275 0, 276 "NVIDIA MCP67 Serial ATA Controller", 277 via_sata_chip_map_6, 278 }, 279 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 280 0, 281 "NVIDIA MCP67 Serial ATA Controller", 282 via_sata_chip_map_6, 283 }, 284 { 0, 285 0, 286 NULL, 287 NULL 288 } 289 }; 290 291 static const struct pciide_product_desc pciide_via_products[] = { 292 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 293 0, 294 NULL, 295 via_chip_map, 296 }, 297 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 298 0, 299 NULL, 300 via_chip_map, 301 }, 302 { PCI_PRODUCT_VIATECH_CX700_IDE, 303 0, 304 NULL, 305 via_sata_chip_map_new, 306 }, 307 { PCI_PRODUCT_VIATECH_CX700M2_IDE, 308 0, 309 NULL, 310 via_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_VX900_IDE, 313 0, 314 NULL, 315 via_chip_map, 316 }, 317 { PCI_PRODUCT_VIATECH_VT6410_RAID, 318 0, 319 NULL, 320 via_chip_map, 321 }, 322 { PCI_PRODUCT_VIATECH_VT6421_RAID, 323 0, 324 "VIA Technologies VT6421 Serial ATA RAID Controller", 325 via_sata_chip_map_new, 326 }, 327 { PCI_PRODUCT_VIATECH_VT8237_SATA, 328 0, 329 "VIA Technologies VT8237 SATA Controller", 330 via_sata_chip_map_7, 331 }, 332 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 333 0, 334 "VIA Technologies VT8237A SATA Controller", 335 via_sata_chip_map_7, 336 }, 337 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, 338 0, 339 "VIA Technologies VT8237A (5337) SATA Controller", 340 via_sata_chip_map_7, 341 }, 342 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 343 0, 344 "VIA Technologies VT8237R SATA Controller", 345 via_sata_chip_map_7, 346 }, 347 { PCI_PRODUCT_VIATECH_VT8237S_SATA, 348 0, 349 "VIA Technologies VT8237S SATA Controller", 350 via_sata_chip_map_7, 351 }, 352 { PCI_PRODUCT_VIATECH_VT8237S_SATA_RAID, 353 0, 354 "VIA Technologies VT8237S SATA Controller (RAID mode)", 355 via_sata_chip_map_7, 356 }, 357 { PCI_PRODUCT_VIATECH_VT8261_SATA, 358 0, 359 "VIA Technologies VT8261 SATA Controller", 360 via_chip_map, 361 }, 362 { PCI_PRODUCT_VIATECH_VT8261_RAID, 363 0, 364 "VIA Technologies VT8261 SATA Controller (RAID mode)", 365 via_sata_chip_map_7, 366 }, 367 { 0, 368 0, 369 NULL, 370 NULL 371 } 372 }; 373 374 static const struct pciide_product_desc * 375 viaide_lookup(pcireg_t id) 376 { 377 378 switch (PCI_VENDOR(id)) { 379 case PCI_VENDOR_VIATECH: 380 return (pciide_lookup_product(id, pciide_via_products)); 381 382 case PCI_VENDOR_AMD: 383 return (pciide_lookup_product(id, pciide_amd_products)); 384 385 case PCI_VENDOR_NVIDIA: 386 return (pciide_lookup_product(id, pciide_nvidia_products)); 387 } 388 return (NULL); 389 } 390 391 static int 392 viaide_match(device_t parent, cfdata_t match, void *aux) 393 { 394 const struct pci_attach_args *pa = aux; 395 396 if (viaide_lookup(pa->pa_id) != NULL) 397 return (2); 398 return (0); 399 } 400 401 static void 402 viaide_attach(device_t parent, device_t self, void *aux) 403 { 404 const struct pci_attach_args *pa = aux; 405 struct pciide_softc *sc = device_private(self); 406 const struct pciide_product_desc *pp; 407 408 sc->sc_wdcdev.sc_atac.atac_dev = self; 409 410 pp = viaide_lookup(pa->pa_id); 411 if (pp == NULL) 412 panic("viaide_attach"); 413 pciide_common_attach(sc, pa, pp); 414 415 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 416 aprint_error_dev(self, "couldn't establish power handler\n"); 417 } 418 419 static int 420 via_pcib_match(const struct pci_attach_args *pa) 421 { 422 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 423 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 424 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 425 return (1); 426 return 0; 427 } 428 429 static bool 430 viaide_suspend(device_t dv, const pmf_qual_t *qual) 431 { 432 struct pciide_softc *sc = device_private(dv); 433 434 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 435 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 436 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 437 /* This two are VIA-only, but should be ignored by other devices. */ 438 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 439 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 440 441 return true; 442 } 443 444 static bool 445 viaide_resume(device_t dv, const pmf_qual_t *qual) 446 { 447 struct pciide_softc *sc = device_private(dv); 448 449 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 450 sc->sc_pm_reg[0]); 451 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 452 sc->sc_pm_reg[1]); 453 /* This two are VIA-only, but should be ignored by other devices. */ 454 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 455 sc->sc_pm_reg[2]); 456 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 457 sc->sc_pm_reg[3]); 458 459 return true; 460 } 461 462 static void 463 via_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 464 { 465 struct pciide_channel *cp; 466 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 467 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 468 int channel; 469 u_int32_t ideconf; 470 pcireg_t pcib_id, pcib_class; 471 struct pci_attach_args pcib_pa; 472 473 if (pciide_chipen(sc, pa) == 0) 474 return; 475 476 switch (vendor) { 477 case PCI_VENDOR_VIATECH: 478 switch (PCI_PRODUCT(pa->pa_id)) { 479 case PCI_PRODUCT_VIATECH_VT6410_RAID: 480 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 481 "VIA Technologies VT6410 IDE controller\n"); 482 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 483 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 484 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 485 break; 486 case PCI_PRODUCT_VIATECH_VT8261_SATA: 487 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 488 break; 489 case PCI_PRODUCT_VIATECH_VX900_IDE: 490 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 491 "VIA Technologies VX900 ATA133 controller\n"); 492 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 493 break; 494 default: 495 /* 496 * get a PCI tag for the ISA bridge. 497 */ 498 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 499 goto unknown; 500 pcib_id = pcib_pa.pa_id; 501 pcib_class = pcib_pa.pa_class; 502 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 503 "VIA Technologies "); 504 switch (PCI_PRODUCT(pcib_id)) { 505 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 506 aprint_normal("VT82C586 (Apollo VP) "); 507 if(PCI_REVISION(pcib_class) >= 0x02) { 508 aprint_normal("ATA33 controller\n"); 509 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 510 } else { 511 aprint_normal("controller\n"); 512 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 513 } 514 break; 515 case PCI_PRODUCT_VIATECH_VT82C596A: 516 aprint_normal("VT82C596A (Apollo Pro) "); 517 if (PCI_REVISION(pcib_class) >= 0x12) { 518 aprint_normal("ATA66 controller\n"); 519 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 520 } else { 521 aprint_normal("ATA33 controller\n"); 522 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 523 } 524 break; 525 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 526 aprint_normal("VT82C686A (Apollo KX133) "); 527 if (PCI_REVISION(pcib_class) >= 0x40) { 528 aprint_normal("ATA100 controller\n"); 529 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 530 } else { 531 aprint_normal("ATA66 controller\n"); 532 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 533 } 534 break; 535 case PCI_PRODUCT_VIATECH_VT8231: 536 aprint_normal("VT8231 ATA100 controller\n"); 537 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 538 break; 539 case PCI_PRODUCT_VIATECH_VT8233: 540 aprint_normal("VT8233 ATA100 controller\n"); 541 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 542 break; 543 case PCI_PRODUCT_VIATECH_VT8233A: 544 aprint_normal("VT8233A ATA133 controller\n"); 545 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 546 break; 547 case PCI_PRODUCT_VIATECH_VT8235: 548 aprint_normal("VT8235 ATA133 controller\n"); 549 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 550 break; 551 case PCI_PRODUCT_VIATECH_VT8237: 552 aprint_normal("VT8237 ATA133 controller\n"); 553 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 554 break; 555 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 556 aprint_normal("VT8237A ATA133 controller\n"); 557 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 558 break; 559 case PCI_PRODUCT_VIATECH_CX700: 560 aprint_normal("CX700 ATA133 controller\n"); 561 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 562 break; 563 case PCI_PRODUCT_VIATECH_VT8251: 564 aprint_normal("VT8251 ATA133 controller\n"); 565 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 566 break; 567 case PCI_PRODUCT_VIATECH_VT8261: 568 aprint_normal("VT8261 ATA133 controller\n"); 569 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 570 break; 571 case PCI_PRODUCT_VIATECH_VX800: 572 aprint_normal("VX800 ATA133 controller\n"); 573 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 574 break; 575 case PCI_PRODUCT_VIATECH_VX855: 576 aprint_normal("VX855 ATA133 controller\n"); 577 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 578 break; 579 default: 580 unknown: 581 aprint_normal("unknown VIA ATA controller\n"); 582 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 583 } 584 break; 585 } 586 sc->sc_apo_regbase = APO_VIA_REGBASE; 587 break; 588 case PCI_VENDOR_AMD: 589 switch (sc->sc_pp->ide_product) { 590 case PCI_PRODUCT_AMD_PBC8111_IDE: 591 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 592 break; 593 case PCI_PRODUCT_AMD_CS5536_IDE: 594 case PCI_PRODUCT_AMD_PBC766_IDE: 595 case PCI_PRODUCT_AMD_PBC768_IDE: 596 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 597 break; 598 default: 599 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 600 } 601 sc->sc_apo_regbase = APO_AMD_REGBASE; 602 break; 603 case PCI_VENDOR_NVIDIA: 604 switch (sc->sc_pp->ide_product) { 605 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 606 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 607 break; 608 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 609 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 610 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 611 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 612 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 613 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 614 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 615 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 616 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 617 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 618 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 619 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 620 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 621 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 622 break; 623 } 624 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 625 break; 626 default: 627 panic("via_chip_map: unknown vendor"); 628 } 629 630 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 631 "bus-master DMA support present"); 632 pciide_mapreg_dma(sc, pa); 633 aprint_verbose("\n"); 634 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 635 if (sc->sc_dma_ok) { 636 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 637 sc->sc_wdcdev.irqack = pciide_irqack; 638 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 639 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 640 } 641 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 642 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 643 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 644 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 645 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 646 sc->sc_wdcdev.wdc_maxdrives = 2; 647 648 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 649 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 650 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 651 652 wdc_allocate_regs(&sc->sc_wdcdev); 653 654 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 655 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 656 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 657 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 658 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 659 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 660 DEBUG_PROBE); 661 662 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 663 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 664 channel++) { 665 cp = &sc->pciide_channels[channel]; 666 if (pciide_chansetup(sc, channel, interface) == 0) 667 continue; 668 669 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 670 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 671 "%s channel ignored (disabled)\n", cp->name); 672 cp->ata_channel.ch_flags |= ATACH_DISABLED; 673 continue; 674 } 675 via_mapchan(pa, cp, interface, pciide_pci_intr); 676 } 677 } 678 679 static void 680 via_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp, 681 pcireg_t interface, int (*pci_intr)(void *)) 682 { 683 struct ata_channel *wdc_cp; 684 struct pciide_softc *sc; 685 prop_bool_t compat_nat_enable; 686 687 wdc_cp = &cp->ata_channel; 688 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 689 compat_nat_enable = prop_dictionary_get( 690 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 691 "use-compat-native-irq"); 692 693 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 694 /* native mode with irq 14/15 requested? */ 695 if (compat_nat_enable != NULL && 696 prop_bool_true(compat_nat_enable)) 697 via_mapregs_compat_native(pa, cp); 698 else 699 pciide_mapregs_native(pa, cp, pci_intr); 700 } else { 701 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 702 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 703 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 704 } 705 wdcattach(wdc_cp); 706 } 707 708 /* 709 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 710 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 711 * programmed to use a single native PCI irq alone. So we install an interrupt 712 * handler for each channel, as in compatibility mode. 713 */ 714 static void 715 via_mapregs_compat_native(const struct pci_attach_args *pa, 716 struct pciide_channel *cp) 717 { 718 struct ata_channel *wdc_cp; 719 struct pciide_softc *sc; 720 721 wdc_cp = &cp->ata_channel; 722 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 723 724 /* XXX prevent pciide_mapregs_native from installing a handler */ 725 if (sc->sc_pci_ih == NULL) 726 sc->sc_pci_ih = (void *)~0; 727 pciide_mapregs_native(pa, cp, NULL); 728 729 /* interrupts are fixed to 14/15, as in compatibility mode */ 730 cp->compat = 1; 731 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 732 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 733 cp->ih = pciide_machdep_compat_intr_establish( 734 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 735 pciide_compat_intr, cp); 736 if (cp->ih == NULL) { 737 #endif 738 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 739 "no compatibility interrupt for " 740 "use by %s channel\n", cp->name); 741 wdc_cp->ch_flags |= ATACH_DISABLED; 742 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 743 } 744 sc->sc_pci_ih = cp->ih; /* XXX */ 745 #endif 746 } 747 } 748 749 static void 750 via_setup_channel(struct ata_channel *chp) 751 { 752 u_int32_t udmatim_reg, datatim_reg; 753 u_int8_t idedma_ctl; 754 int mode, drive, s; 755 struct ata_drive_datas *drvp; 756 struct atac_softc *atac = chp->ch_atac; 757 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 758 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 759 #ifndef PCIIDE_AMD756_ENABLEDMA 760 int rev = PCI_REVISION( 761 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 762 #endif 763 764 idedma_ctl = 0; 765 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 766 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 767 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 768 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 769 770 /* setup DMA if needed */ 771 pciide_channel_dma_setup(cp); 772 773 for (drive = 0; drive < 2; drive++) { 774 drvp = &chp->ch_drive[drive]; 775 /* If no drive, skip */ 776 if (drvp->drive_type == ATA_DRIVET_NONE) 777 continue; 778 /* add timing values, setup DMA if needed */ 779 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 780 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0)) { 781 mode = drvp->PIO_mode; 782 goto pio; 783 } 784 if ((atac->atac_cap & ATAC_CAP_UDMA) && 785 (drvp->drive_flags & ATA_DRIVE_UDMA)) { 786 /* use Ultra/DMA */ 787 s = splbio(); 788 drvp->drive_flags &= ~ATA_DRIVE_DMA; 789 splx(s); 790 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 791 APO_UDMA_EN_MTH(chp->ch_channel, drive); 792 switch (PCI_VENDOR(sc->sc_pci_id)) { 793 case PCI_VENDOR_VIATECH: 794 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 795 /* 8233a */ 796 udmatim_reg |= APO_UDMA_TIME( 797 chp->ch_channel, 798 drive, 799 via_udma133_tim[drvp->UDMA_mode]); 800 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 801 /* 686b */ 802 udmatim_reg |= APO_UDMA_TIME( 803 chp->ch_channel, 804 drive, 805 via_udma100_tim[drvp->UDMA_mode]); 806 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 807 /* 596b or 686a */ 808 udmatim_reg |= APO_UDMA_CLK66( 809 chp->ch_channel); 810 udmatim_reg |= APO_UDMA_TIME( 811 chp->ch_channel, 812 drive, 813 via_udma66_tim[drvp->UDMA_mode]); 814 } else { 815 /* 596a or 586b */ 816 udmatim_reg |= APO_UDMA_TIME( 817 chp->ch_channel, 818 drive, 819 via_udma33_tim[drvp->UDMA_mode]); 820 } 821 break; 822 case PCI_VENDOR_AMD: 823 case PCI_VENDOR_NVIDIA: 824 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 825 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 826 break; 827 } 828 /* can use PIO timings, MW DMA unused */ 829 mode = drvp->PIO_mode; 830 } else { 831 /* use Multiword DMA, but only if revision is OK */ 832 s = splbio(); 833 drvp->drive_flags &= ~ATA_DRIVE_UDMA; 834 splx(s); 835 #ifndef PCIIDE_AMD756_ENABLEDMA 836 /* 837 * The workaround doesn't seem to be necessary 838 * with all drives, so it can be disabled by 839 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 840 * triggered. 841 */ 842 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 843 sc->sc_pp->ide_product == 844 PCI_PRODUCT_AMD_PBC756_IDE && 845 AMD756_CHIPREV_DISABLEDMA(rev)) { 846 aprint_normal( 847 "%s:%d:%d: multi-word DMA disabled due " 848 "to chip revision\n", 849 device_xname( 850 sc->sc_wdcdev.sc_atac.atac_dev), 851 chp->ch_channel, drive); 852 mode = drvp->PIO_mode; 853 s = splbio(); 854 drvp->drive_flags &= ~ATA_DRIVE_DMA; 855 splx(s); 856 goto pio; 857 } 858 #endif 859 /* mode = min(pio, dma+2) */ 860 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 861 mode = drvp->PIO_mode; 862 else 863 mode = drvp->DMA_mode + 2; 864 } 865 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 866 867 pio: /* setup PIO mode */ 868 if (mode <= 2) { 869 drvp->DMA_mode = 0; 870 drvp->PIO_mode = 0; 871 mode = 0; 872 } else { 873 drvp->PIO_mode = mode; 874 drvp->DMA_mode = mode - 2; 875 } 876 datatim_reg |= 877 APO_DATATIM_PULSE(chp->ch_channel, drive, 878 apollo_pio_set[mode]) | 879 APO_DATATIM_RECOV(chp->ch_channel, drive, 880 apollo_pio_rec[mode]); 881 } 882 if (idedma_ctl != 0) { 883 /* Add software bits in status register */ 884 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 885 idedma_ctl); 886 } 887 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 888 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 889 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 890 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 891 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 892 } 893 894 static int 895 via_sata_chip_map_common(struct pciide_softc *sc, 896 const struct pci_attach_args *cpa) 897 { 898 pcireg_t csr; 899 int maptype, ret; 900 struct pci_attach_args pac, *pa = &pac; 901 902 pac = *cpa; 903 904 if (pciide_chipen(sc, pa) == 0) 905 return 0; 906 907 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 908 "bus-master DMA support present"); 909 pciide_mapreg_dma(sc, pa); 910 aprint_verbose("\n"); 911 912 if (sc->sc_dma_ok) { 913 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 914 sc->sc_wdcdev.irqack = pciide_irqack; 915 } 916 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 917 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 918 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 919 920 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 921 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 922 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 923 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 924 sc->sc_wdcdev.wdc_maxdrives = 2; 925 926 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 927 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 928 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 929 930 wdc_allocate_regs(&sc->sc_wdcdev); 931 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 932 PCI_MAPREG_START + 0x14); 933 switch(maptype) { 934 case PCI_MAPREG_TYPE_IO: 935 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 936 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 937 NULL, &sc->sc_ba5_ss); 938 break; 939 case PCI_MAPREG_MEM_TYPE_32BIT: 940 /* 941 * Enable memory-space access if it isn't already there. 942 */ 943 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, 944 PCI_COMMAND_STATUS_REG); 945 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 && 946 (pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) { 947 948 pci_conf_write(pa->pa_pc, pa->pa_tag, 949 PCI_COMMAND_STATUS_REG, 950 csr | PCI_COMMAND_MEM_ENABLE); 951 } 952 953 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 954 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 955 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 956 NULL, &sc->sc_ba5_ss); 957 break; 958 default: 959 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 960 "couldn't map sata regs, unsupported maptype (0x%x)\n", 961 maptype); 962 return 0; 963 } 964 if (ret != 0) { 965 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 966 "couldn't map sata regs\n"); 967 return 0; 968 } 969 return 1; 970 } 971 972 static void 973 via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa, 974 int satareg_shift) 975 { 976 struct pciide_channel *cp; 977 struct ata_channel *wdc_cp; 978 struct wdc_regs *wdr; 979 pcireg_t interface; 980 int channel; 981 982 interface = PCI_INTERFACE(pa->pa_class); 983 984 if (via_sata_chip_map_common(sc, pa) == 0) 985 return; 986 987 if (interface == 0) { 988 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 989 DEBUG_PROBE); 990 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 991 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 992 } 993 994 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 995 sc->sc_wdcdev.wdc_maxdrives = 1; 996 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 997 channel++) { 998 cp = &sc->pciide_channels[channel]; 999 if (pciide_chansetup(sc, channel, interface) == 0) 1000 continue; 1001 wdc_cp = &cp->ata_channel; 1002 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1003 wdr->sata_iot = sc->sc_ba5_st; 1004 wdr->sata_baseioh = sc->sc_ba5_sh; 1005 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1006 (wdc_cp->ch_channel << satareg_shift) + 0x0, 4, 1007 &wdr->sata_status) != 0) { 1008 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1009 "couldn't map channel %d sata_status regs\n", 1010 wdc_cp->ch_channel); 1011 continue; 1012 } 1013 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1014 (wdc_cp->ch_channel << satareg_shift) + 0x4, 4, 1015 &wdr->sata_error) != 0) { 1016 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1017 "couldn't map channel %d sata_error regs\n", 1018 wdc_cp->ch_channel); 1019 continue; 1020 } 1021 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1022 (wdc_cp->ch_channel << satareg_shift) + 0x8, 4, 1023 &wdr->sata_control) != 0) { 1024 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1025 "couldn't map channel %d sata_control regs\n", 1026 wdc_cp->ch_channel); 1027 continue; 1028 } 1029 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 1030 } 1031 } 1032 1033 static void 1034 via_sata_chip_map_6(struct pciide_softc *sc, const struct pci_attach_args *pa) 1035 { 1036 via_sata_chip_map(sc, pa, 6); 1037 } 1038 1039 static void 1040 via_sata_chip_map_7(struct pciide_softc *sc, const struct pci_attach_args *pa) 1041 { 1042 via_sata_chip_map(sc, pa, 7); 1043 } 1044 1045 static void 1046 via_vt6421_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 1047 { 1048 struct pciide_channel *pc; 1049 int chan, reg; 1050 bus_size_t size; 1051 1052 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 1053 PCI_MAPREG_TYPE_IO, 0, &sc->sc_dma_iot, &sc->sc_dma_ioh, 1054 NULL, &sc->sc_dma_ios) == 0); 1055 sc->sc_dmat = pa->pa_dmat; 1056 if (sc->sc_dma_ok == 0) { 1057 aprint_verbose(", but unused (couldn't map registers)"); 1058 } else { 1059 sc->sc_wdcdev.dma_arg = sc; 1060 sc->sc_wdcdev.dma_init = pciide_dma_init; 1061 sc->sc_wdcdev.dma_start = pciide_dma_start; 1062 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 1063 } 1064 1065 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 1066 PCIIDE_OPTIONS_NODMA) { 1067 aprint_verbose( 1068 ", but unused (forced off by config file)"); 1069 sc->sc_dma_ok = 0; 1070 } 1071 1072 if (sc->sc_dma_ok == 0) 1073 return; 1074 1075 for (chan = 0; chan < 4; chan++) { 1076 pc = &sc->pciide_channels[chan]; 1077 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 1078 size = 4; 1079 if (size > (IDEDMA_SCH_OFFSET - reg)) 1080 size = IDEDMA_SCH_OFFSET - reg; 1081 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 1082 IDEDMA_SCH_OFFSET * chan + reg, size, 1083 &pc->dma_iohs[reg]) != 0) { 1084 sc->sc_dma_ok = 0; 1085 aprint_verbose(", but can't subregion offset " 1086 "%d size %lu", 1087 reg, (u_long)size); 1088 return; 1089 } 1090 } 1091 } 1092 } 1093 1094 static int 1095 via_vt6421_chansetup(struct pciide_softc *sc, int channel) 1096 { 1097 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1098 1099 sc->wdc_chanarray[channel] = &cp->ata_channel; 1100 1101 cp->ata_channel.ch_channel = channel; 1102 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 1103 1104 return 1; 1105 } 1106 1107 static void 1108 via_sata_chip_map_new(struct pciide_softc *sc, 1109 const struct pci_attach_args *pa) 1110 { 1111 struct pciide_channel *cp; 1112 struct ata_channel *wdc_cp; 1113 struct wdc_regs *wdr; 1114 int channel; 1115 pci_intr_handle_t intrhandle; 1116 const char *intrstr; 1117 int i; 1118 char intrbuf[PCI_INTRSTR_LEN]; 1119 1120 if (pciide_chipen(sc, pa) == 0) 1121 return; 1122 1123 sc->sc_apo_regbase = APO_VIA_VT6421_REGBASE; 1124 1125 if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0, 1126 &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 1127 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1128 "couldn't map SATA regs\n"); 1129 } 1130 1131 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1132 "bus-master DMA support present"); 1133 via_vt6421_mapreg_dma(sc, pa); 1134 aprint_verbose("\n"); 1135 1136 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 1137 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 1138 if (sc->sc_dma_ok) { 1139 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 1140 sc->sc_wdcdev.irqack = pciide_irqack; 1141 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 1142 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 1143 } 1144 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 1145 1146 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 1147 sc->sc_wdcdev.sc_atac.atac_nchannels = 3; 1148 sc->sc_wdcdev.wdc_maxdrives = 2; 1149 1150 wdc_allocate_regs(&sc->sc_wdcdev); 1151 1152 if (pci_intr_map(pa, &intrhandle) != 0) { 1153 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1154 "couldn't map native-PCI interrupt\n"); 1155 return; 1156 } 1157 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 1158 sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc, 1159 intrhandle, IPL_BIO, pciide_pci_intr, sc, 1160 device_xname(sc->sc_wdcdev.sc_atac.atac_dev)); 1161 if (sc->sc_pci_ih == NULL) { 1162 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1163 "couldn't establish native-PCI interrupt"); 1164 if (intrstr != NULL) 1165 aprint_error(" at %s", intrstr); 1166 aprint_error("\n"); 1167 return; 1168 } 1169 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1170 "using %s for native-PCI interrupt\n", 1171 intrstr ? intrstr : "unknown interrupt"); 1172 1173 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1174 channel++) { 1175 cp = &sc->pciide_channels[channel]; 1176 if (via_vt6421_chansetup(sc, channel) == 0) 1177 continue; 1178 wdc_cp = &cp->ata_channel; 1179 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1180 1181 wdr->sata_iot = sc->sc_ba5_st; 1182 wdr->sata_baseioh = sc->sc_ba5_sh; 1183 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1184 (wdc_cp->ch_channel << 6) + 0x0, 4, 1185 &wdr->sata_status) != 0) { 1186 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1187 "couldn't map channel %d sata_status regs\n", 1188 wdc_cp->ch_channel); 1189 continue; 1190 } 1191 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1192 (wdc_cp->ch_channel << 6) + 0x4, 4, 1193 &wdr->sata_error) != 0) { 1194 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1195 "couldn't map channel %d sata_error regs\n", 1196 wdc_cp->ch_channel); 1197 continue; 1198 } 1199 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1200 (wdc_cp->ch_channel << 6) + 0x8, 4, 1201 &wdr->sata_control) != 0) { 1202 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1203 "couldn't map channel %d sata_control regs\n", 1204 wdc_cp->ch_channel); 1205 continue; 1206 } 1207 1208 if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel), 1209 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1210 NULL, &wdr->cmd_ios) != 0) { 1211 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1212 "couldn't map %s channel regs\n", cp->name); 1213 } 1214 wdr->ctl_iot = wdr->cmd_iot; 1215 for (i = 0; i < WDC_NREG; i++) { 1216 if (bus_space_subregion(wdr->cmd_iot, 1217 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1218 &wdr->cmd_iohs[i]) != 0) { 1219 aprint_error_dev( 1220 sc->sc_wdcdev.sc_atac.atac_dev, 1221 "couldn't subregion %s " 1222 "channel cmd regs\n", cp->name); 1223 return; 1224 } 1225 } 1226 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1227 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1228 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1229 "couldn't map channel %d ctl regs\n", channel); 1230 return; 1231 } 1232 wdc_init_shadow_regs(wdr); 1233 wdr->data32iot = wdr->cmd_iot; 1234 wdr->data32ioh = wdr->cmd_iohs[wd_data]; 1235 wdcattach(wdc_cp); 1236 } 1237 } 1238