1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Huawei Technologies Co., Ltd 3 */ 4 5 #ifndef _HINIC_PMD_NICCFG_H_ 6 #define _HINIC_PMD_NICCFG_H_ 7 8 #define OS_VF_ID_TO_HW(os_vf_id) ((os_vf_id) + 1) 9 #define HW_VF_ID_TO_OS(hw_vf_id) ((hw_vf_id) - 1) 10 11 #define HINIC_VLAN_PRIORITY_SHIFT 13 12 13 #define HINIC_RSS_INDIR_SIZE 256 14 #define HINIC_DCB_TC_MAX 0x8 15 #define HINIC_DCB_UP_MAX 0x8 16 #define HINIC_DCB_PG_MAX 0x8 17 #define HINIC_RSS_KEY_SIZE 40 18 19 #define HINIC_MAX_NUM_RQ 64 20 21 #define ANTI_ATTACK_DEFAULT_CIR 500000 22 #define ANTI_ATTACK_DEFAULT_XIR 600000 23 #define ANTI_ATTACK_DEFAULT_CBS 10000000 24 #define ANTI_ATTACK_DEFAULT_XBS 12000000 25 26 #define NIC_RSS_INDIR_SIZE 256 27 #define NIC_RSS_KEY_SIZE 40 28 #define NIC_RSS_CMD_TEMP_ALLOC 0x01 29 #define NIC_RSS_CMD_TEMP_FREE 0x02 30 #define NIC_DCB_UP_MAX 0x8 31 32 enum hinic_rss_hash_type { 33 HINIC_RSS_HASH_ENGINE_TYPE_XOR = 0, 34 HINIC_RSS_HASH_ENGINE_TYPE_TOEP, 35 36 HINIC_RSS_HASH_ENGINE_TYPE_MAX, 37 }; 38 39 struct nic_port_info { 40 u8 port_type; 41 u8 autoneg_cap; 42 u8 autoneg_state; 43 u8 duplex; 44 u8 speed; 45 }; 46 47 enum nic_speed_level { 48 LINK_SPEED_10MB = 0, 49 LINK_SPEED_100MB, 50 LINK_SPEED_1GB, 51 LINK_SPEED_10GB, 52 LINK_SPEED_25GB, 53 LINK_SPEED_40GB, 54 LINK_SPEED_100GB, 55 LINK_SPEED_MAX 56 }; 57 58 enum hinic_link_status { 59 HINIC_LINK_DOWN = 0, 60 HINIC_LINK_UP 61 }; 62 63 struct hinic_up_ets_cfg { 64 struct hinic_mgmt_msg_head mgmt_msg_head; 65 66 u8 port_id; 67 u8 rsvd1[3]; 68 u8 up_tc[HINIC_DCB_UP_MAX]; 69 u8 pg_bw[HINIC_DCB_PG_MAX]; 70 u8 pgid[HINIC_DCB_UP_MAX]; 71 u8 up_bw[HINIC_DCB_UP_MAX]; 72 u8 prio[HINIC_DCB_PG_MAX]; 73 }; 74 75 struct nic_pause_config { 76 u32 auto_neg; 77 u32 rx_pause; 78 u32 tx_pause; 79 }; 80 81 struct nic_rss_type { 82 u8 tcp_ipv6_ext; 83 u8 ipv6_ext; 84 u8 tcp_ipv6; 85 u8 ipv6; 86 u8 tcp_ipv4; 87 u8 ipv4; 88 u8 udp_ipv6; 89 u8 udp_ipv4; 90 }; 91 92 enum hinic_rx_mod { 93 HINIC_RX_MODE_UC = 1 << 0, 94 HINIC_RX_MODE_MC = 1 << 1, 95 HINIC_RX_MODE_BC = 1 << 2, 96 HINIC_RX_MODE_MC_ALL = 1 << 3, 97 HINIC_RX_MODE_PROMISC = 1 << 4, 98 }; 99 100 enum hinic_link_mode { 101 HINIC_10GE_BASE_KR = 0, 102 HINIC_40GE_BASE_KR4 = 1, 103 HINIC_40GE_BASE_CR4 = 2, 104 HINIC_100GE_BASE_KR4 = 3, 105 HINIC_100GE_BASE_CR4 = 4, 106 HINIC_25GE_BASE_KR_S = 5, 107 HINIC_25GE_BASE_CR_S = 6, 108 HINIC_25GE_BASE_KR = 7, 109 HINIC_25GE_BASE_CR = 8, 110 HINIC_GE_BASE_KX = 9, 111 HINIC_LINK_MODE_NUMBERS, 112 113 HINIC_SUPPORTED_UNKNOWN = 0xFFFF, 114 }; 115 116 #define HINIC_DEFAULT_RX_MODE (HINIC_RX_MODE_UC | HINIC_RX_MODE_MC | \ 117 HINIC_RX_MODE_BC) 118 119 #define HINIC_PORT_DISABLE 0x0 120 #define HINIC_PORT_ENABLE 0x3 121 122 struct hinic_vport_stats { 123 u64 tx_unicast_pkts_vport; 124 u64 tx_unicast_bytes_vport; 125 u64 tx_multicast_pkts_vport; 126 u64 tx_multicast_bytes_vport; 127 u64 tx_broadcast_pkts_vport; 128 u64 tx_broadcast_bytes_vport; 129 130 u64 rx_unicast_pkts_vport; 131 u64 rx_unicast_bytes_vport; 132 u64 rx_multicast_pkts_vport; 133 u64 rx_multicast_bytes_vport; 134 u64 rx_broadcast_pkts_vport; 135 u64 rx_broadcast_bytes_vport; 136 137 u64 tx_discard_vport; 138 u64 rx_discard_vport; 139 u64 tx_err_vport; 140 u64 rx_err_vport; /* rx checksum err pkts in ucode */ 141 }; 142 143 struct hinic_phy_port_stats { 144 u64 mac_rx_total_pkt_num; 145 u64 mac_rx_total_oct_num; 146 u64 mac_rx_bad_pkt_num; 147 u64 mac_rx_bad_oct_num; 148 u64 mac_rx_good_pkt_num; 149 u64 mac_rx_good_oct_num; 150 u64 mac_rx_uni_pkt_num; 151 u64 mac_rx_multi_pkt_num; 152 u64 mac_rx_broad_pkt_num; 153 154 u64 mac_tx_total_pkt_num; 155 u64 mac_tx_total_oct_num; 156 u64 mac_tx_bad_pkt_num; 157 u64 mac_tx_bad_oct_num; 158 u64 mac_tx_good_pkt_num; 159 u64 mac_tx_good_oct_num; 160 u64 mac_tx_uni_pkt_num; 161 u64 mac_tx_multi_pkt_num; 162 u64 mac_tx_broad_pkt_num; 163 164 u64 mac_rx_fragment_pkt_num; 165 u64 mac_rx_undersize_pkt_num; 166 u64 mac_rx_undermin_pkt_num; 167 u64 mac_rx_64_oct_pkt_num; 168 u64 mac_rx_65_127_oct_pkt_num; 169 u64 mac_rx_128_255_oct_pkt_num; 170 u64 mac_rx_256_511_oct_pkt_num; 171 u64 mac_rx_512_1023_oct_pkt_num; 172 u64 mac_rx_1024_1518_oct_pkt_num; 173 u64 mac_rx_1519_2047_oct_pkt_num; 174 u64 mac_rx_2048_4095_oct_pkt_num; 175 u64 mac_rx_4096_8191_oct_pkt_num; 176 u64 mac_rx_8192_9216_oct_pkt_num; 177 u64 mac_rx_9217_12287_oct_pkt_num; 178 u64 mac_rx_12288_16383_oct_pkt_num; 179 u64 mac_rx_1519_max_bad_pkt_num; 180 u64 mac_rx_1519_max_good_pkt_num; 181 u64 mac_rx_oversize_pkt_num; 182 u64 mac_rx_jabber_pkt_num; 183 184 u64 mac_rx_mac_pause_num; 185 u64 mac_rx_pfc_pkt_num; 186 u64 mac_rx_pfc_pri0_pkt_num; 187 u64 mac_rx_pfc_pri1_pkt_num; 188 u64 mac_rx_pfc_pri2_pkt_num; 189 u64 mac_rx_pfc_pri3_pkt_num; 190 u64 mac_rx_pfc_pri4_pkt_num; 191 u64 mac_rx_pfc_pri5_pkt_num; 192 u64 mac_rx_pfc_pri6_pkt_num; 193 u64 mac_rx_pfc_pri7_pkt_num; 194 u64 mac_rx_mac_control_pkt_num; 195 u64 mac_rx_y1731_pkt_num; 196 u64 mac_rx_sym_err_pkt_num; 197 u64 mac_rx_fcs_err_pkt_num; 198 u64 mac_rx_send_app_good_pkt_num; 199 u64 mac_rx_send_app_bad_pkt_num; 200 201 u64 mac_tx_fragment_pkt_num; 202 u64 mac_tx_undersize_pkt_num; 203 u64 mac_tx_undermin_pkt_num; 204 u64 mac_tx_64_oct_pkt_num; 205 u64 mac_tx_65_127_oct_pkt_num; 206 u64 mac_tx_128_255_oct_pkt_num; 207 u64 mac_tx_256_511_oct_pkt_num; 208 u64 mac_tx_512_1023_oct_pkt_num; 209 u64 mac_tx_1024_1518_oct_pkt_num; 210 u64 mac_tx_1519_2047_oct_pkt_num; 211 u64 mac_tx_2048_4095_oct_pkt_num; 212 u64 mac_tx_4096_8191_oct_pkt_num; 213 u64 mac_tx_8192_9216_oct_pkt_num; 214 u64 mac_tx_9217_12287_oct_pkt_num; 215 u64 mac_tx_12288_16383_oct_pkt_num; 216 u64 mac_tx_1519_max_bad_pkt_num; 217 u64 mac_tx_1519_max_good_pkt_num; 218 u64 mac_tx_oversize_pkt_num; 219 u64 mac_trans_jabber_pkt_num; 220 221 u64 mac_tx_mac_pause_num; 222 u64 mac_tx_pfc_pkt_num; 223 u64 mac_tx_pfc_pri0_pkt_num; 224 u64 mac_tx_pfc_pri1_pkt_num; 225 u64 mac_tx_pfc_pri2_pkt_num; 226 u64 mac_tx_pfc_pri3_pkt_num; 227 u64 mac_tx_pfc_pri4_pkt_num; 228 u64 mac_tx_pfc_pri5_pkt_num; 229 u64 mac_tx_pfc_pri6_pkt_num; 230 u64 mac_tx_pfc_pri7_pkt_num; 231 u64 mac_tx_mac_control_pkt_num; 232 u64 mac_tx_y1731_pkt_num; 233 u64 mac_tx_1588_pkt_num; 234 u64 mac_tx_err_all_pkt_num; 235 u64 mac_tx_from_app_good_pkt_num; 236 u64 mac_tx_from_app_bad_pkt_num; 237 238 u64 rx_higig2_ext_pkts_port; 239 u64 rx_higig2_message_pkts_port; 240 u64 rx_higig2_error_pkts_port; 241 u64 rx_higig2_cpu_ctrl_pkts_port; 242 u64 rx_higig2_unicast_pkts_port; 243 u64 rx_higig2_broadcast_pkts_port; 244 u64 rx_higig2_l2_multicast_pkts; 245 u64 rx_higig2_l3_multicast_pkts; 246 247 u64 tx_higig2_message_pkts_port; 248 u64 tx_higig2_ext_pkts_port; 249 u64 tx_higig2_cpu_ctrl_pkts_port; 250 u64 tx_higig2_unicast_pkts_port; 251 u64 tx_higig2_broadcast_pkts_port; 252 u64 tx_higig2_l2_multicast_pkts; 253 u64 tx_higig2_l3_multicast_pkts; 254 }; 255 256 enum hinic_link_follow_status { 257 HINIC_LINK_FOLLOW_DEFAULT, 258 HINIC_LINK_FOLLOW_PORT, 259 HINIC_LINK_FOLLOW_SEPARATE, 260 HINIC_LINK_FOLLOW_STATUS_MAX, 261 }; 262 263 #define HINIC_PORT_STATS_VERSION 0 264 struct hinic_port_stats_info { 265 struct hinic_mgmt_msg_head mgmt_msg_head; 266 267 u16 func_id; 268 u16 rsvd1; 269 u32 stats_version; 270 u32 stats_size; 271 }; 272 273 struct hinic_port_stats { 274 struct hinic_mgmt_msg_head mgmt_msg_head; 275 276 struct hinic_phy_port_stats stats; 277 }; 278 279 struct hinic_cmd_vport_stats { 280 struct hinic_mgmt_msg_head mgmt_msg_head; 281 282 struct hinic_vport_stats stats; 283 }; 284 285 struct hinic_clear_port_stats { 286 struct hinic_mgmt_msg_head mgmt_msg_head; 287 288 u16 func_id; 289 u16 rsvd; 290 u32 stats_version; 291 u32 stats_size; 292 }; 293 294 struct hinic_clear_vport_stats { 295 struct hinic_mgmt_msg_head mgmt_msg_head; 296 297 u16 func_id; 298 u16 rsvd; 299 u32 stats_version; 300 u32 stats_size; 301 }; 302 303 struct hinic_fast_recycled_mode { 304 struct hinic_mgmt_msg_head mgmt_msg_head; 305 306 u16 func_id; 307 /* 308 * 1: enable fast recycle, available in dpdk mode, 309 * 0: normal mode, available in kernel nic mode 310 */ 311 u8 fast_recycled_mode; 312 u8 rsvd1; 313 }; 314 315 struct hinic_function_table { 316 struct hinic_mgmt_msg_head mgmt_msg_head; 317 318 u16 func_id; 319 u16 rx_wqe_buf_size; 320 u32 mtu; 321 }; 322 323 struct hinic_cmd_qpn { 324 struct hinic_mgmt_msg_head mgmt_msg_head; 325 326 u16 func_id; 327 u16 base_qpn; 328 }; 329 330 struct hinic_port_mac_set { 331 struct hinic_mgmt_msg_head mgmt_msg_head; 332 333 u16 func_id; 334 u16 vlan_id; 335 u16 rsvd1; 336 u8 mac[ETH_ALEN]; 337 }; 338 339 struct hinic_port_mac_update { 340 struct hinic_mgmt_msg_head mgmt_msg_head; 341 342 u16 func_id; 343 u16 vlan_id; 344 u16 rsvd1; 345 u8 old_mac[ETH_ALEN]; 346 u16 rsvd2; 347 u8 new_mac[ETH_ALEN]; 348 }; 349 350 struct hinic_vport_state { 351 struct hinic_mgmt_msg_head mgmt_msg_head; 352 353 u16 func_id; 354 u16 rsvd1; 355 u8 state; 356 u8 rsvd2[3]; 357 }; 358 359 struct hinic_port_state { 360 struct hinic_mgmt_msg_head mgmt_msg_head; 361 362 u8 state; 363 u8 rsvd1[3]; 364 }; 365 366 struct hinic_mtu { 367 struct hinic_mgmt_msg_head mgmt_msg_head; 368 369 u16 func_id; 370 u16 rsvd1; 371 u32 mtu; 372 }; 373 374 struct hinic_vlan_config { 375 struct hinic_mgmt_msg_head mgmt_msg_head; 376 377 u16 func_id; 378 u16 vlan_id; 379 }; 380 381 struct hinic_vlan_filter { 382 struct hinic_mgmt_msg_head mgmt_msg_head; 383 384 u16 func_id; 385 u8 rsvd1[2]; 386 u32 vlan_filter_ctrl; 387 }; 388 389 struct hinic_vlan_offload { 390 struct hinic_mgmt_msg_head mgmt_msg_head; 391 392 u16 func_id; 393 u8 vlan_rx_offload; 394 u8 rsvd1[5]; 395 }; 396 397 struct hinic_get_link { 398 struct hinic_mgmt_msg_head mgmt_msg_head; 399 400 u16 func_id; 401 u8 link_status; 402 u8 rsvd1; 403 }; 404 405 #define HINIC_DEFAUT_PAUSE_CONFIG 1 406 struct hinic_pause_config { 407 struct hinic_mgmt_msg_head mgmt_msg_head; 408 409 u16 func_id; 410 u16 rsvd1; 411 u32 auto_neg; 412 u32 rx_pause; 413 u32 tx_pause; 414 }; 415 416 struct hinic_port_info { 417 struct hinic_mgmt_msg_head mgmt_msg_head; 418 419 u16 func_id; 420 u16 rsvd1; 421 u8 port_type; 422 u8 autoneg_cap; 423 u8 autoneg_state; 424 u8 duplex; 425 u8 speed; 426 u8 resv2[3]; 427 }; 428 429 struct hinic_tso_config { 430 struct hinic_mgmt_msg_head mgmt_msg_head; 431 432 u16 func_id; 433 u16 rsvd1; 434 u8 tso_en; 435 u8 resv2[3]; 436 }; 437 438 struct hinic_lro_config { 439 struct hinic_mgmt_msg_head mgmt_msg_head; 440 441 u16 func_id; 442 u16 rsvd1; 443 u8 lro_ipv4_en; 444 u8 lro_ipv6_en; 445 u8 lro_max_wqe_num; 446 u8 resv2[13]; 447 }; 448 449 struct hinic_checksum_offload { 450 struct hinic_mgmt_msg_head mgmt_msg_head; 451 452 u16 func_id; 453 u16 rsvd1; 454 u32 rx_csum_offload; 455 }; 456 457 struct hinic_rx_mode_config { 458 struct hinic_mgmt_msg_head mgmt_msg_head; 459 460 u16 func_id; 461 u16 rsvd1; 462 u32 rx_mode; 463 }; 464 465 #define HINIC_MGMT_VERSION_MAX_LEN 32 466 #define HINIC_COMPILE_TIME_LEN 20 467 #define HINIC_FW_VERSION_NAME 16 468 469 struct hinic_version_info { 470 struct hinic_mgmt_msg_head mgmt_msg_head; 471 472 u8 ver[HINIC_FW_VERSION_NAME]; 473 u8 time[HINIC_COMPILE_TIME_LEN]; 474 }; 475 476 /* rss */ 477 struct nic_rss_indirect_tbl { 478 u32 group_index; 479 u32 offset; 480 u32 size; 481 u32 rsvd; 482 u8 entry[NIC_RSS_INDIR_SIZE]; 483 }; 484 485 struct nic_rss_context_tbl { 486 u32 group_index; 487 u32 offset; 488 u32 size; 489 u32 rsvd; 490 u32 ctx; 491 }; 492 493 struct hinic_rss_config { 494 struct hinic_mgmt_msg_head mgmt_msg_head; 495 496 u16 func_id; 497 u8 rss_en; 498 u8 template_id; 499 u8 rq_priority_number; 500 u8 rsvd1[3]; 501 u8 prio_tc[NIC_DCB_UP_MAX]; 502 }; 503 504 struct hinic_rss_template_mgmt { 505 struct hinic_mgmt_msg_head mgmt_msg_head; 506 507 u16 func_id; 508 u8 cmd; 509 u8 template_id; 510 u8 rsvd1[4]; 511 }; 512 513 struct hinic_rss_indir_table { 514 struct hinic_mgmt_msg_head mgmt_msg_head; 515 516 u16 func_id; 517 u8 template_id; 518 u8 rsvd1; 519 u8 indir[NIC_RSS_INDIR_SIZE]; 520 }; 521 522 struct hinic_rss_template_key { 523 struct hinic_mgmt_msg_head mgmt_msg_head; 524 525 u16 func_id; 526 u8 template_id; 527 u8 rsvd1; 528 u8 key[NIC_RSS_KEY_SIZE]; 529 }; 530 531 struct hinic_rss_engine_type { 532 struct hinic_mgmt_msg_head mgmt_msg_head; 533 534 u16 func_id; 535 u8 template_id; 536 u8 hash_engine; 537 u8 rsvd1[4]; 538 }; 539 540 struct hinic_rss_context_table { 541 struct hinic_mgmt_msg_head mgmt_msg_head; 542 543 u16 func_id; 544 u8 template_id; 545 u8 rsvd1; 546 u32 context; 547 }; 548 549 struct hinic_reset_link_cfg { 550 struct hinic_mgmt_msg_head mgmt_msg_head; 551 552 u16 func_id; 553 u16 rsvd1; 554 }; 555 556 struct hinic_set_vhd_mode { 557 struct hinic_mgmt_msg_head mgmt_msg_head; 558 559 u16 func_id; 560 u16 vhd_type; 561 u16 rx_wqe_buffer_size; 562 u16 rsvd; 563 }; 564 565 struct hinic_set_link_follow { 566 struct hinic_mgmt_msg_head mgmt_msg_head; 567 568 u16 func_id; 569 u16 rsvd0; 570 u8 follow_status; 571 u8 rsvd1[3]; 572 }; 573 574 struct hinic_link_mode_cmd { 575 struct hinic_mgmt_msg_head mgmt_msg_head; 576 577 u16 func_id; 578 u16 rsvd1; 579 u16 supported; /* 0xFFFF represent Invalid value */ 580 u16 advertised; 581 }; 582 583 struct hinic_set_xsfp_status { 584 struct hinic_mgmt_msg_head mgmt_msg_head; 585 586 u32 port_id; 587 u32 xsfp_tx_dis; /* 0: tx enable; 1: tx disable */ 588 }; 589 590 struct hinic_clear_qp_resource { 591 struct hinic_mgmt_msg_head mgmt_msg_head; 592 593 u16 func_id; 594 u16 rsvd1; 595 }; 596 597 struct hinic_dcb_state { 598 u8 dcb_on; 599 u8 default_cos; 600 u8 up_cos[8]; 601 }; 602 603 struct hinic_vf_default_cos { 604 struct hinic_mgmt_msg_head mgmt_msg_head; 605 606 struct hinic_dcb_state state; 607 }; 608 609 /* set physical port Anti-Attack rate */ 610 struct hinic_port_anti_attack_rate { 611 struct hinic_mgmt_msg_head mgmt_msg_head; 612 613 u16 func_id; 614 u16 enable; /* 1: enable rate-limiting, 0: disable rate-limiting */ 615 u32 cir; /* Committed Information Rate */ 616 u32 xir; /* eXtended Information Rate */ 617 u32 cbs; /* Committed Burst Size */ 618 u32 xbs; /* eXtended Burst Size */ 619 }; 620 621 struct pa_u8_s { 622 u8 val8; 623 u8 mask8; 624 }; 625 626 struct pa_u16_s { 627 u16 val16; 628 u16 mask16; 629 }; 630 631 struct pa_u32_s { 632 u32 val32; 633 u32 mask32; 634 }; 635 636 struct pa_u48_s { 637 u8 val8[6]; 638 u8 mask8[6]; 639 }; 640 641 struct pa_u64_s { 642 u8 val8[8]; 643 u8 mask8[8]; 644 }; 645 646 struct tag_pa_eth_ip_header { 647 struct pa_u8_s ip_ver; /* 3bit */ 648 struct pa_u8_s ipv4_option_flag; /* 1bit */ 649 /* 8bit ipv4 option or ipv6 next header */ 650 struct pa_u8_s protocol; 651 struct pa_u8_s dscp; /* 6bit DSCP */ 652 }; 653 654 struct tag_pa_common_l2_header { 655 struct pa_u48_s dmac; /* dmac 48bit */ 656 struct pa_u16_s eth_type; /* ethernet type/length 16bit */ 657 struct pa_u8_s tag_flag; /* tag flag: 4bit */ 658 struct pa_u8_s np2np_hdr_qindex; /* NP2NP Header Qindex 4bit */ 659 struct pa_u8_s e_tag_pcp; /* 3bit */ 660 struct pa_u8_s vlan_layer; /* 2bit */ 661 struct pa_u8_s s_tag; /* 3bit */ 662 struct pa_u8_s c_tag; /* 3bit */ 663 struct pa_u16_s vlan_id; /* 12bit */ 664 }; 665 666 struct tag_pa_tcp { 667 struct pa_u16_s sport; /* 16bit */ 668 struct pa_u16_s dport; /* 16bit */ 669 struct pa_u16_s tcp_flag; /* 6bit */ 670 }; 671 672 struct tag_pa_udp { 673 struct pa_u16_s sport; /* 16bit */ 674 struct pa_u16_s dport; /* 16bit */ 675 /* 8bit : 676 * 1.udp dport=67/68 && ipv4 protocol=0x11 677 * 2.udp dport=546/547 && ipv6 next header=0x11 678 * 3. do not care 679 */ 680 struct pa_u8_s dhcp_op_or_msg_type; 681 }; 682 683 /* ICMP: 684 * ipv4 protocol = 0x1 685 * ipv6 next header = 0x3A 686 */ 687 struct tag_pa_icmp { 688 struct pa_u8_s type; /* 8bit */ 689 struct pa_u8_s code; /* 8bit */ 690 }; 691 692 /* IGMP: 693 * ipv4 protocol = 0x2 694 */ 695 struct tag_pa_ipv4_igmp { 696 struct pa_u32_s dip; /* 32bit */ 697 struct pa_u8_s type; /* 8bit */ 698 }; 699 700 struct tag_pa_rule { 701 struct pa_u8_s ncsi_flag; /* 1bit valid */ 702 struct tag_pa_common_l2_header l2_header; 703 704 u8 eth_type; 705 706 struct pa_u64_s eth_other; /* eth_type=other 64bit */ 707 struct pa_u8_s eth_roce_opcode; /* eth_type=roce 8bit opcode */ 708 709 struct tag_pa_eth_ip_header ip_header; /* eth_type=ip */ 710 711 u8 ip_protocol_type; 712 713 struct tag_pa_tcp eth_ip_tcp; /* eth_type=ip && ip_protocol = tcp */ 714 struct tag_pa_udp eth_ip_udp; /* eth_type=ip && ip_protocol = udp */ 715 struct tag_pa_icmp eth_ip_icmp; /* eth_type=ip && ip_protocol = icmp */ 716 717 /* eth_type=ip && ip_protocol = ipv4_igmp */ 718 struct tag_pa_ipv4_igmp eth_ipv4_igmp; 719 720 /* eth_type=ip && ip_protocol = sctp; 721 * 16bit ipv4 protocol=0x84 or ipv6 nhr=0x84 722 */ 723 struct pa_u16_s eth_ip_sctp; 724 }; 725 726 struct tag_pa_action { 727 u16 pkt_type; 728 u8 err_type; 729 u8 pri; 730 u8 fwd_action; 731 u8 push_len; 732 }; 733 734 struct hinic_fdir_tcam_info { 735 struct hinic_mgmt_msg_head mgmt_msg_head; 736 737 u16 tcam_index; 738 u8 flag; /* clear or set tcam table flag */ 739 u8 rsvd1; 740 struct tag_pa_rule filter_rule; 741 struct tag_pa_action filter_action; 742 }; 743 744 #define TCAM_SET 0x1 745 #define TCAM_CLEAR 0x2 746 747 struct hinic_port_qfilter_info { 748 struct hinic_mgmt_msg_head mgmt_msg_head; 749 750 u16 func_id; 751 u8 normal_type_enable; 752 u8 filter_type_enable; 753 u8 filter_enable; 754 u8 filter_type; 755 u8 qid; 756 u8 fdir_flag; 757 u32 key; 758 }; 759 760 struct hinic_port_tcam_info { 761 struct hinic_mgmt_msg_head mgmt_msg_head; 762 763 u16 func_id; 764 u8 tcam_enable; 765 u8 rsvd1; 766 u32 rsvd2; 767 }; 768 769 #define HINIC_MAX_TCAM_RULES_NUM (10240) 770 #define HINIC_TCAM_BLOCK_ENABLE 1 771 #define HINIC_TCAM_BLOCK_DISABLE 0 772 773 struct tag_tcam_result { 774 u32 qid; 775 u32 rsvd; 776 }; 777 778 #define TCAM_FLOW_KEY_SIZE 24 779 780 struct tag_tcam_key_x_y { 781 u8 x[TCAM_FLOW_KEY_SIZE]; 782 u8 y[TCAM_FLOW_KEY_SIZE]; 783 }; 784 785 struct tag_tcam_cfg_rule { 786 u32 index; 787 struct tag_tcam_result data; 788 struct tag_tcam_key_x_y key; 789 }; 790 791 struct tag_fdir_add_rule_cmd { 792 struct hinic_mgmt_msg_head mgmt_msg_head; 793 struct tag_tcam_cfg_rule rule; 794 }; 795 796 struct tag_fdir_del_rule_cmd { 797 struct hinic_mgmt_msg_head mgmt_msg_head; 798 799 u32 index_start; 800 u32 index_num; 801 }; 802 803 struct hinic_cmd_flush_tcam_rules { 804 struct hinic_mgmt_msg_head mgmt_msg_head; 805 806 u16 func_id; 807 u16 rsvd; 808 }; 809 810 struct hinic_cmd_ctrl_tcam_block { 811 struct hinic_mgmt_msg_head mgmt_msg_head; 812 813 u16 func_id; 814 u8 alloc_en; /* 0: free tcam block, 1: alloc tcam block */ 815 /* 816 * 0: alloc 1k size tcam block, 817 * 1: alloc 128 size tcam block, others rsvd 818 */ 819 u8 tcam_type; 820 u16 tcam_block_index; 821 u16 rsvd; 822 }; 823 824 int hinic_set_mac(void *hwdev, u8 *mac_addr, u16 vlan_id, u16 func_id); 825 826 int hinic_del_mac(void *hwdev, u8 *mac_addr, u16 vlan_id, u16 func_id); 827 828 int hinic_update_mac(void *hwdev, u8 *old_mac, u8 *new_mac, u16 vlan_id, 829 u16 func_id); 830 831 int hinic_get_default_mac(void *hwdev, u8 *mac_addr); 832 833 int hinic_set_port_mtu(void *hwdev, u32 new_mtu); 834 835 int hinic_add_remove_vlan(void *hwdev, u16 vlan_id, u16 func_id, bool add); 836 837 int hinic_config_vlan_filter(void *hwdev, u32 vlan_filter_ctrl); 838 839 int hinic_set_rx_vlan_offload(void *hwdev, u8 en); 840 841 int hinic_set_vport_enable(void *hwdev, bool enable); 842 843 int hinic_set_port_enable(void *hwdev, bool enable); 844 845 int hinic_get_link_status(void *hwdev, u8 *link_state); 846 847 int hinic_get_port_info(void *hwdev, struct nic_port_info *port_info); 848 849 int hinic_set_rx_vhd_mode(void *hwdev, u16 vhd_mode, u16 rx_buf_sz); 850 851 int hinic_set_pause_config(void *hwdev, struct nic_pause_config nic_pause); 852 853 int hinic_get_pause_info(void *hwdev, struct nic_pause_config *nic_pause); 854 855 int hinic_reset_port_link_cfg(void *hwdev); 856 857 int hinic_dcb_set_ets(void *hwdev, u8 *up_tc, u8 *pg_bw, u8 *pgid, u8 *up_bw, 858 u8 *prio); 859 860 int hinic_set_anti_attack(void *hwdev, bool enable); 861 862 /* offload feature */ 863 int hinic_set_rx_lro(void *hwdev, u8 ipv4_en, u8 ipv6_en, u8 max_wqe_num); 864 865 int hinic_get_vport_stats(void *hwdev, struct hinic_vport_stats *stats); 866 867 int hinic_get_phy_port_stats(void *hwdev, struct hinic_phy_port_stats *stats); 868 869 /* rss */ 870 int hinic_set_rss_type(void *hwdev, u32 tmpl_idx, 871 struct nic_rss_type rss_type); 872 873 int hinic_get_rss_type(void *hwdev, u32 tmpl_idx, 874 struct nic_rss_type *rss_type); 875 876 int hinic_rss_set_template_tbl(void *hwdev, u32 tmpl_idx, u8 *temp); 877 878 int hinic_rss_get_template_tbl(void *hwdev, u32 tmpl_idx, u8 *temp); 879 880 int hinic_rss_set_hash_engine(void *hwdev, u8 tmpl_idx, u8 type); 881 882 int hinic_rss_get_indir_tbl(void *hwdev, u32 tmpl_idx, u32 *indir_table); 883 884 int hinic_rss_set_indir_tbl(void *hwdev, u32 tmpl_idx, u32 *indir_table); 885 886 int hinic_rss_cfg(void *hwdev, u8 rss_en, u8 tmpl_idx, u8 tc_num, u8 *prio_tc); 887 888 int hinic_rss_template_alloc(void *hwdev, u8 *tmpl_idx); 889 890 int hinic_rss_template_free(void *hwdev, u8 tmpl_idx); 891 892 int hinic_set_rx_mode(void *hwdev, u32 enable); 893 894 int hinic_get_mgmt_version(void *hwdev, char *fw); 895 896 int hinic_set_rx_csum_offload(void *hwdev, u32 en); 897 898 int hinic_set_link_status_follow(void *hwdev, 899 enum hinic_link_follow_status status); 900 901 int hinic_get_link_mode(void *hwdev, u32 *supported, u32 *advertised); 902 903 int hinic_flush_qp_res(void *hwdev); 904 905 int hinic_init_function_table(void *hwdev, u16 rx_buf_sz); 906 907 int hinic_set_fast_recycle_mode(void *hwdev, u8 mode); 908 909 int hinic_get_base_qpn(void *hwdev, u16 *global_qpn); 910 911 int hinic_clear_vport_stats(struct hinic_hwdev *hwdev); 912 913 int hinic_clear_phy_port_stats(struct hinic_hwdev *hwdev); 914 915 int hinic_vf_func_init(struct hinic_hwdev *hwdev); 916 917 void hinic_vf_func_free(struct hinic_hwdev *hwdev); 918 919 int hinic_vf_get_default_cos(struct hinic_hwdev *hwdev, u8 *cos_id); 920 921 int hinic_set_fdir_filter(void *hwdev, u8 filter_type, u8 qid, 922 u8 type_enable, bool enable); 923 924 int hinic_set_normal_filter(void *hwdev, u8 qid, u8 normal_type_enable, 925 u32 key, bool enable, u8 flag); 926 927 int hinic_set_fdir_tcam(void *hwdev, u16 type_mask, 928 struct tag_pa_rule *filter_rule, struct tag_pa_action *filter_action); 929 930 int hinic_clear_fdir_tcam(void *hwdev, u16 type_mask); 931 932 int hinic_add_tcam_rule(void *hwdev, struct tag_tcam_cfg_rule *tcam_rule); 933 934 int hinic_del_tcam_rule(void *hwdev, u32 index); 935 936 int hinic_alloc_tcam_block(void *hwdev, u8 block_type, u16 *index); 937 938 int hinic_free_tcam_block(void *hwdev, u8 block_type, u16 *index); 939 940 int hinic_flush_tcam_rule(void *hwdev); 941 942 int hinic_set_fdir_tcam_rule_filter(void *hwdev, bool enable); 943 944 #endif /* _HINIC_PMD_NICCFG_H_ */ 945