1 /* $OpenBSD: if_iwxvar.h,v 1.42 2024/11/08 09:12:46 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2014 genua mbh <info@genua.de> 5 * Copyright (c) 2014 Fixup Software Ltd. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 22 * which were used as the reference documentation for this implementation. 23 * 24 ****************************************************************************** 25 * 26 * This file is provided under a dual BSD/GPLv2 license. When using or 27 * redistributing this file, you may do so under either license. 28 * 29 * GPL LICENSE SUMMARY 30 * 31 * Copyright(c) 2017 Intel Deutschland GmbH 32 * Copyright(c) 2018 - 2019 Intel Corporation 33 * 34 * This program is free software; you can redistribute it and/or modify 35 * it under the terms of version 2 of the GNU General Public License as 36 * published by the Free Software Foundation. 37 * 38 * This program is distributed in the hope that it will be useful, but 39 * WITHOUT ANY WARRANTY; without even the implied warranty of 40 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 41 * General Public License for more details. 42 * 43 * BSD LICENSE 44 * 45 * Copyright(c) 2017 Intel Deutschland GmbH 46 * Copyright(c) 2018 - 2019 Intel Corporation 47 * All rights reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 53 * * Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * * Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in 57 * the documentation and/or other materials provided with the 58 * distribution. 59 * * Neither the name Intel Corporation nor the names of its 60 * contributors may be used to endorse or promote products derived 61 * from this software without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 64 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 65 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 66 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 67 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 68 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 69 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 70 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 71 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 72 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 73 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 74 * 75 ***************************************************************************** 76 */ 77 78 /*- 79 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 80 * 81 * Permission to use, copy, modify, and distribute this software for any 82 * purpose with or without fee is hereby granted, provided that the above 83 * copyright notice and this permission notice appear in all copies. 84 * 85 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 86 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 87 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 88 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 89 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 90 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 91 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 92 */ 93 94 struct iwx_rx_radiotap_header { 95 struct ieee80211_radiotap_header wr_ihdr; 96 uint64_t wr_tsft; 97 uint8_t wr_flags; 98 uint8_t wr_rate; 99 uint16_t wr_chan_freq; 100 uint16_t wr_chan_flags; 101 int8_t wr_dbm_antsignal; 102 int8_t wr_dbm_antnoise; 103 } __packed; 104 105 #define IWX_RX_RADIOTAP_PRESENT \ 106 ((1 << IEEE80211_RADIOTAP_TSFT) | \ 107 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 108 (1 << IEEE80211_RADIOTAP_RATE) | \ 109 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 110 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ 111 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)) 112 113 struct iwx_tx_radiotap_header { 114 struct ieee80211_radiotap_header wt_ihdr; 115 uint8_t wt_flags; 116 uint8_t wt_rate; 117 uint16_t wt_chan_freq; 118 uint16_t wt_chan_flags; 119 } __packed; 120 121 #define IWX_TX_RADIOTAP_PRESENT \ 122 ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 123 (1 << IEEE80211_RADIOTAP_RATE) | \ 124 (1 << IEEE80211_RADIOTAP_CHANNEL)) 125 126 #define IWX_UCODE_SECT_MAX 60 127 128 /* 129 * fw_status is used to determine if we've already parsed the firmware file 130 * 131 * In addition to the following, status < 0 ==> -error 132 */ 133 #define IWX_FW_STATUS_NONE 0 134 #define IWX_FW_STATUS_INPROGRESS 1 135 #define IWX_FW_STATUS_DONE 2 136 137 enum iwx_ucode_type { 138 IWX_UCODE_TYPE_REGULAR, 139 IWX_UCODE_TYPE_INIT, 140 IWX_UCODE_TYPE_WOW, 141 IWX_UCODE_TYPE_REGULAR_USNIFFER, 142 IWX_UCODE_TYPE_MAX 143 }; 144 145 struct iwx_fw_info { 146 void *fw_rawdata; 147 size_t fw_rawsize; 148 int fw_status; 149 150 struct iwx_fw_sects { 151 struct iwx_fw_onesect { 152 void *fws_data; 153 uint32_t fws_len; 154 uint32_t fws_devoff; 155 } fw_sect[IWX_UCODE_SECT_MAX]; 156 size_t fw_totlen; 157 int fw_count; 158 } fw_sects[IWX_UCODE_TYPE_MAX]; 159 160 /* FW debug data parsed for driver usage */ 161 int dbg_dest_tlv_init; 162 uint8_t *dbg_dest_ver; 163 uint8_t n_dest_reg; 164 struct iwx_fw_dbg_dest_tlv_v1 *dbg_dest_tlv_v1; 165 166 struct iwx_fw_dbg_conf_tlv *dbg_conf_tlv[IWX_FW_DBG_CONF_MAX]; 167 size_t dbg_conf_tlv_len[IWX_FW_DBG_CONF_MAX]; 168 struct iwx_fw_dbg_trigger_tlv *dbg_trigger_tlv[IWX_FW_DBG_TRIGGER_MAX]; 169 size_t dbg_trigger_tlv_len[IWX_FW_DBG_TRIGGER_MAX]; 170 struct iwx_fw_dbg_mem_seg_tlv *dbg_mem_tlv; 171 size_t n_mem_tlv; 172 173 /* Copy of firmware image loader found in file. */ 174 uint8_t *iml; 175 size_t iml_len; 176 }; 177 178 struct iwx_nvm_data { 179 int n_hw_addrs; 180 uint8_t hw_addr[ETHER_ADDR_LEN]; 181 182 int sku_cap_band_24GHz_enable; 183 int sku_cap_band_52GHz_enable; 184 int sku_cap_11n_enable; 185 int sku_cap_11ac_enable; 186 int sku_cap_11ax_enable; 187 int sku_cap_amt_enable; 188 int sku_cap_ipan_enable; 189 int sku_cap_mimo_disable; 190 int lar_enabled; 191 192 uint8_t valid_tx_ant, valid_rx_ant; 193 194 uint16_t nvm_version; 195 }; 196 197 /* max bufs per tfd the driver will use */ 198 #define IWX_MAX_CMD_TBS_PER_TFD 2 199 200 struct iwx_host_cmd { 201 const void *data[IWX_MAX_CMD_TBS_PER_TFD]; 202 struct iwx_rx_packet *resp_pkt; 203 size_t resp_pkt_len; 204 unsigned long _rx_page_addr; 205 uint32_t _rx_page_order; 206 int handler_status; 207 208 uint32_t flags; 209 uint16_t len[IWX_MAX_CMD_TBS_PER_TFD]; 210 uint8_t dataflags[IWX_MAX_CMD_TBS_PER_TFD]; 211 uint32_t id; 212 }; 213 214 /* 215 * DMA glue is from iwn 216 */ 217 218 struct iwx_dma_info { 219 bus_dma_tag_t tag; 220 bus_dmamap_t map; 221 bus_dma_segment_t seg; 222 bus_addr_t paddr; 223 void *vaddr; 224 bus_size_t size; 225 }; 226 227 #define IWX_TX_RING_COUNT IWX_DEFAULT_QUEUE_SIZE 228 #define IWX_TX_RING_LOMARK 192 229 #define IWX_TX_RING_HIMARK 224 230 231 struct iwx_tx_data { 232 bus_dmamap_t map; 233 bus_addr_t cmd_paddr; 234 struct mbuf *m; 235 struct iwx_node *in; 236 int flags; 237 #define IWX_TXDATA_FLAG_CMD_IS_NARROW 0x01 238 }; 239 240 struct iwx_tx_ring { 241 struct iwx_dma_info desc_dma; 242 struct iwx_dma_info cmd_dma; 243 struct iwx_dma_info bc_tbl; 244 struct iwx_tfh_tfd *desc; 245 struct iwx_device_cmd *cmd; 246 struct iwx_tx_data data[IWX_TX_RING_COUNT]; 247 int qid; 248 int queued; 249 int cur; 250 int cur_hw; 251 int tail; 252 int tail_hw; 253 int tid; 254 }; 255 256 #define IWX_RX_MQ_RING_COUNT 512 257 /* Linux driver optionally uses 8k buffer */ 258 #define IWX_RBUF_SIZE 4096 259 260 struct iwx_rx_data { 261 struct mbuf *m; 262 bus_dmamap_t map; 263 }; 264 265 struct iwx_rx_ring { 266 struct iwx_dma_info free_desc_dma; 267 struct iwx_dma_info stat_dma; 268 struct iwx_dma_info used_desc_dma; 269 void *desc; 270 struct iwx_rb_status *stat; 271 struct iwx_rx_data data[IWX_RX_MQ_RING_COUNT]; 272 int cur; 273 }; 274 275 #define IWX_FLAG_USE_ICT 0x01 /* using Interrupt Cause Table */ 276 #define IWX_FLAG_RFKILL 0x02 /* radio kill switch is set */ 277 #define IWX_FLAG_SCANNING 0x04 /* scan in progress */ 278 #define IWX_FLAG_MAC_ACTIVE 0x08 /* MAC context added to firmware */ 279 #define IWX_FLAG_BINDING_ACTIVE 0x10 /* MAC->PHY binding added to firmware */ 280 #define IWX_FLAG_STA_ACTIVE 0x20 /* AP added to firmware station table */ 281 #define IWX_FLAG_TE_ACTIVE 0x40 /* time event is scheduled */ 282 #define IWX_FLAG_HW_ERR 0x80 /* hardware error occurred */ 283 #define IWX_FLAG_SHUTDOWN 0x100 /* shutting down; new tasks forbidden */ 284 #define IWX_FLAG_BGSCAN 0x200 /* background scan in progress */ 285 #define IWX_FLAG_TXFLUSH 0x400 /* Tx queue flushing in progress */ 286 287 struct iwx_ucode_status { 288 uint32_t uc_lmac_error_event_table[2]; 289 uint32_t uc_umac_error_event_table; 290 uint32_t uc_log_event_table; 291 unsigned int error_event_table_tlv_status; 292 293 int uc_ok; 294 int uc_intr; 295 }; 296 297 #define IWX_ERROR_EVENT_TABLE_LMAC1 (1 << 0) 298 #define IWX_ERROR_EVENT_TABLE_LMAC2 (1 << 1) 299 #define IWX_ERROR_EVENT_TABLE_UMAC (1 << 2) 300 301 #define IWX_CMD_RESP_MAX PAGE_SIZE 302 303 /* lower blocks contain EEPROM image and calibration data */ 304 #define IWX_OTP_LOW_IMAGE_SIZE_FAMILY_7000 16384 305 #define IWX_OTP_LOW_IMAGE_SIZE_FAMILY_8000 32768 306 307 #define IWX_TE_SESSION_PROTECTION_MAX_TIME_MS 1000 308 #define IWX_TE_SESSION_PROTECTION_MIN_TIME_MS 400 309 310 enum IWX_CMD_MODE { 311 IWX_CMD_ASYNC = (1 << 0), 312 IWX_CMD_WANT_RESP = (1 << 1), 313 IWX_CMD_SEND_IN_RFKILL = (1 << 2), 314 }; 315 enum iwx_hcmd_dataflag { 316 IWX_HCMD_DFL_NOCOPY = (1 << 0), 317 IWX_HCMD_DFL_DUP = (1 << 1), 318 }; 319 320 #define IWX_NUM_PAPD_CH_GROUPS 9 321 #define IWX_NUM_TXP_CH_GROUPS 9 322 323 struct iwx_phy_ctxt { 324 uint16_t id; 325 uint16_t color; 326 uint32_t ref; 327 struct ieee80211_channel *channel; 328 uint8_t sco; /* 40 MHz secondary channel offset */ 329 uint8_t vht_chan_width; 330 }; 331 332 struct iwx_bf_data { 333 int bf_enabled; /* filtering */ 334 int ba_enabled; /* abort */ 335 int ave_beacon_signal; 336 int last_cqm_event; 337 }; 338 339 /** 340 * struct iwx_self_init_dram - dram data used by self init process 341 * @fw: lmac and umac dram data 342 * @lmac_cnt: number of lmac sections in fw image 343 * @umac_cnt: number of umac sections in fw image 344 * @paging: paging dram data 345 * @paging_cnt: number of paging sections needed by fw image 346 */ 347 struct iwx_self_init_dram { 348 struct iwx_dma_info *fw; 349 int lmac_cnt; 350 int umac_cnt; 351 struct iwx_dma_info *paging; 352 int paging_cnt; 353 }; 354 355 /** 356 * struct iwx_reorder_buffer - per ra/tid/queue reorder buffer 357 * @head_sn: reorder window head sn 358 * @num_stored: number of mpdus stored in the buffer 359 * @buf_size: the reorder buffer size as set by the last addba request 360 * @queue: queue of this reorder buffer 361 * @last_amsdu: track last ASMDU SN for duplication detection 362 * @last_sub_index: track ASMDU sub frame index for duplication detection 363 * @reorder_timer: timer for frames are in the reorder buffer. For AMSDU 364 * it is the time of last received sub-frame 365 * @removed: prevent timer re-arming 366 * @valid: reordering is valid for this queue 367 * @consec_oldsn_drops: consecutive drops due to old SN 368 * @consec_oldsn_ampdu_gp2: A-MPDU GP2 timestamp to track 369 * when to apply old SN consecutive drop workaround 370 * @consec_oldsn_prev_drop: track whether or not an MPDU 371 * that was single/part of the previous A-MPDU was 372 * dropped due to old SN 373 */ 374 struct iwx_reorder_buffer { 375 uint16_t head_sn; 376 uint16_t num_stored; 377 uint16_t buf_size; 378 uint16_t last_amsdu; 379 uint8_t last_sub_index; 380 struct timeout reorder_timer; 381 int removed; 382 int valid; 383 unsigned int consec_oldsn_drops; 384 uint32_t consec_oldsn_ampdu_gp2; 385 unsigned int consec_oldsn_prev_drop; 386 #define IWX_AMPDU_CONSEC_DROPS_DELBA 10 387 }; 388 389 /** 390 * struct iwx_reorder_buf_entry - reorder buffer entry per frame sequence number 391 * @frames: list of mbufs stored (A-MSDU subframes share a sequence number) 392 * @reorder_time: time the packet was stored in the reorder buffer 393 */ 394 struct iwx_reorder_buf_entry { 395 struct mbuf_list frames; 396 struct timeval reorder_time; 397 uint32_t rx_pkt_status; 398 int chanidx; 399 int is_shortpre; 400 uint32_t rate_n_flags; 401 uint32_t device_timestamp; 402 struct ieee80211_rxinfo rxi; 403 }; 404 405 /** 406 * struct iwx_rxba_data - BA session data 407 * @sta_id: station id 408 * @tid: tid of the session 409 * @baid: baid of the session 410 * @timeout: the timeout set in the addba request 411 * @entries_per_queue: # of buffers per queue 412 * @last_rx: last rx timestamp, updated only if timeout passed from last update 413 * @session_timer: timer to check if BA session expired, runs at 2 * timeout 414 * @sc: softc pointer, needed for timer context 415 * @reorder_buf: reorder buffer 416 * @reorder_buf_data: buffered frames, one entry per sequence number 417 */ 418 struct iwx_rxba_data { 419 uint8_t sta_id; 420 uint8_t tid; 421 uint8_t baid; 422 uint16_t timeout; 423 uint16_t entries_per_queue; 424 struct timeval last_rx; 425 struct timeout session_timer; 426 struct iwx_softc *sc; 427 struct iwx_reorder_buffer reorder_buf; 428 struct iwx_reorder_buf_entry entries[IEEE80211_BA_MAX_WINSZ]; 429 }; 430 431 static inline struct iwx_rxba_data * 432 iwx_rxba_data_from_reorder_buf(struct iwx_reorder_buffer *buf) 433 { 434 return (void *)((uint8_t *)buf - 435 offsetof(struct iwx_rxba_data, reorder_buf)); 436 } 437 438 /** 439 * struct iwx_rxq_dup_data - per station per rx queue data 440 * @last_seq: last sequence per tid for duplicate packet detection 441 * @last_sub_frame: last subframe packet 442 */ 443 struct iwx_rxq_dup_data { 444 uint16_t last_seq[IWX_MAX_TID_COUNT + 1]; 445 uint8_t last_sub_frame[IWX_MAX_TID_COUNT + 1]; 446 }; 447 448 struct iwx_setkey_task_arg { 449 int sta_id; 450 struct ieee80211_node *ni; 451 struct ieee80211_key *k; 452 }; 453 454 struct iwx_ba_task_data { 455 uint32_t start_tidmask; 456 uint32_t stop_tidmask; 457 }; 458 459 460 /* 461 * Device configuration parameters which cannot be detected based on 462 * PCI vendor/product ID alone. 463 */ 464 struct iwx_device_cfg { 465 const char *fw_name; 466 const char *pnvm_name; 467 int tx_with_siso_diversity; 468 int uhb_supported; 469 int xtal_latency; 470 int low_latency_xtal; 471 }; 472 473 /* Firmware listed here must be available in fw_update(8). */ 474 #define IWX_CC_A_FW "iwx-cc-a0-77" 475 #define IWX_TY_A_GF_A_FW "iwx-ty-a0-gf-a0-77" 476 #define IWX_TY_A_GF_A_PNVM "iwx-ty-a0-gf-a0.pnvm" 477 #define IWX_QU_B_HR_B_FW "iwx-Qu-b0-hr-b0-77" 478 #define IWX_QU_B_JF_B_FW "iwx-Qu-b0-jf-b0-77" 479 #define IWX_QU_C_HR_B_FW "iwx-Qu-c0-hr-b0-77" 480 #define IWX_QU_C_JF_B_FW "iwx-Qu-c0-jf-b0-77" 481 #define IWX_QUZ_A_HR_B_FW "iwx-QuZ-a0-hr-b0-77" 482 #define IWX_QUZ_A_JF_B_FW "iwx-QuZ-a0-jf-b0-77" 483 #define IWX_SO_A_GF_A_FW "iwx-so-a0-gf-a0-77" 484 #define IWX_SO_A_GF_A_PNVM "iwx-so-a0-gf-a0.pnvm" 485 #define IWX_SO_A_GF4_A_FW "iwx-so-a0-gf4-a0-77" 486 #define IWX_SO_A_GF4_A_PNVM "iwx-so-a0-gf4-a0.pnvm" 487 #define IWX_SO_A_HR_B_FW "iwx-so-a0-hr-b0-77" 488 #define IWX_SO_A_JF_B_FW "iwx-so-a0-jf-b0-77" 489 #define IWX_MA_B_HR_B_FW "iwx-ma-a0-hr-b0-83" 490 #define IWX_MA_B_HR_B_PNVM "iwx-ma-a0-hr-b0.pnvm" 491 #define IWX_MA_B_GF_A_FW "iwx-ma-b0-gf-a0-83" 492 #define IWX_MA_B_GF_A_PNVM "iwx-ma-b0-gf-a0.pnvm" 493 #define IWX_MA_B_GF4_A_FW "iwx-ma-b0-gf4-a0-83" 494 #define IWX_MA_B_GF4_A_PNVM "iwx-ma-b0-gf4-a0.pnvm" 495 #define IWX_MA_A_FM_A_FW "iwx-ma-a0-fm-a0-83" 496 #define IWX_MA_A_FM_A_PNVM "iwx-ma-a0-fm-a0.pnvm" 497 498 const struct iwx_device_cfg iwx_9560_quz_a0_jf_b0_cfg = { 499 .fw_name = IWX_QUZ_A_JF_B_FW, 500 }; 501 502 const struct iwx_device_cfg iwx_9560_qu_c0_jf_b0_cfg = { 503 .fw_name = IWX_QU_C_JF_B_FW, 504 }; 505 506 const struct iwx_device_cfg iwx_qu_b0_hr1_b0 = { 507 .fw_name = IWX_QU_B_HR_B_FW, 508 .tx_with_siso_diversity = true, 509 }; 510 511 const struct iwx_device_cfg iwx_qu_b0_hr_b0 = { 512 .fw_name = IWX_QU_B_HR_B_FW, 513 }; 514 515 const struct iwx_device_cfg iwx_ax201_cfg_qu_hr = { 516 .fw_name = IWX_QU_B_HR_B_FW, 517 }; 518 519 const struct iwx_device_cfg iwx_qu_c0_hr1_b0 = { 520 .fw_name = IWX_QU_C_HR_B_FW, 521 .tx_with_siso_diversity = true, 522 }; 523 524 const struct iwx_device_cfg iwx_qu_c0_hr_b0 = { 525 .fw_name = IWX_QU_C_HR_B_FW, 526 }; 527 528 const struct iwx_device_cfg iwx_ax201_cfg_qu_c0_hr_b0 = { 529 .fw_name = IWX_QU_C_HR_B_FW, 530 }; 531 532 const struct iwx_device_cfg iwx_quz_a0_hr1_b0 = { 533 .fw_name = IWX_QUZ_A_HR_B_FW, 534 }; 535 536 const struct iwx_device_cfg iwx_ax201_cfg_quz_hr = { 537 .fw_name = IWX_QUZ_A_HR_B_FW, 538 }; 539 540 const struct iwx_device_cfg iwx_cfg_so_a0_hr_b0 = { 541 .fw_name = IWX_SO_A_HR_B_FW, 542 }; 543 544 const struct iwx_device_cfg iwx_cfg_quz_a0_hr_b0 = { 545 .fw_name = IWX_QUZ_A_HR_B_FW, 546 }; 547 548 const struct iwx_device_cfg iwx_2ax_cfg_so_gf_a0 = { 549 .fw_name = IWX_SO_A_GF_A_FW, 550 .pnvm_name = IWX_SO_A_GF_A_PNVM, 551 .uhb_supported = 1, 552 }; 553 554 const struct iwx_device_cfg iwx_2ax_cfg_so_gf_a0_long = { 555 .fw_name = IWX_SO_A_GF_A_FW, 556 .pnvm_name = IWX_SO_A_GF_A_PNVM, 557 .uhb_supported = 1, 558 .xtal_latency = 12000, 559 .low_latency_xtal = 1, 560 }; 561 562 const struct iwx_device_cfg iwx_2ax_cfg_so_gf4_a0 = { 563 .fw_name = IWX_SO_A_GF4_A_FW, 564 .pnvm_name = IWX_SO_A_GF4_A_PNVM, 565 .uhb_supported = 1, 566 .xtal_latency = 12000, 567 .low_latency_xtal = 1, 568 }; 569 570 const struct iwx_device_cfg iwx_2ax_cfg_so_gf4_a0_long = { 571 .fw_name = IWX_SO_A_GF4_A_FW, 572 .pnvm_name = IWX_SO_A_GF4_A_PNVM, 573 .uhb_supported = 1, 574 }; 575 576 const struct iwx_device_cfg iwx_2ax_cfg_ty_gf_a0 = { 577 .fw_name = IWX_TY_A_GF_A_FW, 578 .pnvm_name = IWX_TY_A_GF_A_PNVM, 579 }; 580 581 const struct iwx_device_cfg iwx_2ax_cfg_so_jf_b0 = { 582 .fw_name = IWX_SO_A_JF_B_FW, 583 }; 584 585 const struct iwx_device_cfg iwx_cfg_ma_b0_hr_b0 = { 586 .fw_name = IWX_MA_B_HR_B_FW, 587 .pnvm_name = IWX_MA_B_HR_B_PNVM, 588 }; 589 590 const struct iwx_device_cfg iwx_cfg_ma_b0_gf_a0 = { 591 .fw_name = IWX_MA_B_GF_A_FW, 592 .pnvm_name = IWX_MA_B_GF_A_PNVM, 593 }; 594 595 const struct iwx_device_cfg iwx_cfg_ma_b0_gf4_a0 = { 596 .fw_name = IWX_MA_B_GF4_A_FW, 597 .pnvm_name = IWX_MA_B_GF4_A_PNVM, 598 }; 599 600 const struct iwx_device_cfg iwx_cfg_ma_a0_fm_a0 = { 601 .fw_name = IWX_MA_A_FM_A_FW, 602 .pnvm_name = IWX_MA_A_FM_A_PNVM, 603 }; 604 605 #define IWX_CFG_ANY (~0) 606 607 #define IWX_CFG_MAC_TYPE_QU 0x33 608 #define IWX_CFG_MAC_TYPE_QUZ 0x35 609 #define IWX_CFG_MAC_TYPE_QNJ 0x36 610 #define IWX_CFG_MAC_TYPE_SO 0x37 611 #define IWX_CFG_MAC_TYPE_SNJ 0x42 612 #define IWX_CFG_MAC_TYPE_SOF 0x43 613 #define IWX_CFG_MAC_TYPE_MA 0x44 614 #define IWX_CFG_MAC_TYPE_BZ 0x46 615 #define IWX_CFG_MAC_TYPE_GL 0x47 616 617 #define IWX_CFG_RF_TYPE_JF2 0x105 618 #define IWX_CFG_RF_TYPE_JF1 0x108 619 #define IWX_CFG_RF_TYPE_HR2 0x10a 620 #define IWX_CFG_RF_TYPE_HR1 0x10c 621 #define IWX_CFG_RF_TYPE_GF 0x10d 622 #define IWX_CFG_RF_TYPE_MR 0x110 623 #define IWX_CFG_RF_TYPE_MS 0x111 624 #define IWX_CFG_RF_TYPE_FM 0x112 625 626 #define IWX_CFG_RF_ID_JF 0x3 627 #define IWX_CFG_RF_ID_JF1 0x6 628 #define IWX_CFG_RF_ID_JF1_DIV 0xa 629 630 #define IWX_CFG_NO_160 0x1 631 #define IWX_CFG_160 0x0 632 633 #define IWX_CFG_CORES_BT 0x0 634 635 #define IWX_CFG_NO_CDB 0x0 636 #define IWX_CFG_CDB 0x1 637 638 #define IWX_SUBDEVICE_RF_ID(subdevice) ((uint16_t)((subdevice) & 0x00f0) >> 4) 639 #define IWX_SUBDEVICE_NO_160(subdevice) ((uint16_t)((subdevice) & 0x0200) >> 9) 640 #define IWX_SUBDEVICE_CORES(subdevice) ((uint16_t)((subdevice) & 0x1c00) >> 10) 641 642 struct iwx_softc { 643 struct device sc_dev; 644 struct ieee80211com sc_ic; 645 int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int); 646 int sc_newstate_pending; 647 int attached; 648 649 struct task init_task; /* NB: not reference-counted */ 650 struct refcnt task_refs; 651 struct task newstate_task; 652 enum ieee80211_state ns_nstate; 653 int ns_arg; 654 655 /* Task for firmware BlockAck setup/teardown and its arguments. */ 656 struct task ba_task; 657 struct iwx_ba_task_data ba_rx; 658 struct iwx_ba_task_data ba_tx; 659 660 /* Task for setting encryption keys and its arguments. */ 661 struct task setkey_task; 662 /* 663 * At present we need to process at most two keys at once: 664 * Our pairwise key and a group key. 665 * When hostap mode is implemented this array needs to grow or 666 * it might become a bottleneck for associations that occur at 667 * roughly the same time. 668 */ 669 struct iwx_setkey_task_arg setkey_arg[2]; 670 int setkey_cur; 671 int setkey_tail; 672 int setkey_nkeys; 673 674 /* Task for ERP/HT prot/slot-time/EDCA updates. */ 675 struct task mac_ctxt_task; 676 677 /* Task for HT 20/40 MHz channel width updates. */ 678 struct task phy_ctxt_task; 679 680 bus_space_tag_t sc_st; 681 bus_space_handle_t sc_sh; 682 bus_size_t sc_sz; 683 bus_dma_tag_t sc_dmat; 684 pci_product_id_t sc_pid; 685 pci_chipset_tag_t sc_pct; 686 pcitag_t sc_pcitag; 687 const void *sc_ih; 688 int sc_msix; 689 690 /* TX/RX rings. */ 691 struct iwx_tx_ring txq[IWX_NUM_TX_QUEUES]; 692 struct iwx_rx_ring rxq; 693 int qfullmsk; 694 int qenablemsk; 695 int first_data_qid; 696 int aggqid[IEEE80211_NUM_TID]; 697 int max_tfd_queue_size; 698 699 int sc_sf_state; 700 701 /* ICT table. */ 702 struct iwx_dma_info ict_dma; 703 int ict_cur; 704 705 int sc_hw_rev; 706 #define IWX_SILICON_A_STEP 0 707 #define IWX_SILICON_B_STEP 1 708 #define IWX_SILICON_C_STEP 2 709 #define IWX_SILICON_Z_STEP 0xf 710 int sc_hw_id; 711 int sc_hw_rf_id; 712 int sc_device_family; 713 #define IWX_DEVICE_FAMILY_22000 1 714 #define IWX_DEVICE_FAMILY_AX210 2 715 uint32_t sc_sku_id[3]; 716 uint32_t mac_addr_from_csr; 717 718 struct iwx_dma_info ctxt_info_dma; 719 struct iwx_self_init_dram init_dram; 720 struct iwx_dma_info prph_scratch_dma; 721 struct iwx_dma_info prph_info_dma; 722 struct iwx_dma_info iml_dma; 723 struct iwx_dma_info pnvm_dma; 724 struct iwx_dma_info pnvm_seg_dma[IWX_MAX_DRAM_ENTRY]; 725 uint32_t pnvm_size; 726 int pnvm_segs; 727 uint32_t sc_pnvm_ver; 728 729 int sc_fw_chunk_done; 730 int sc_init_complete; 731 #define IWX_INIT_COMPLETE 0x01 732 #define IWX_CALIB_COMPLETE 0x02 733 #define IWX_PNVM_COMPLETE 0x04 734 735 struct iwx_ucode_status sc_uc; 736 char sc_fwver[32]; 737 738 int sc_capaflags; 739 int sc_capa_max_probe_len; 740 int sc_capa_n_scan_channels; 741 uint8_t sc_ucode_api[howmany(IWX_NUM_UCODE_TLV_API, NBBY)]; 742 uint8_t sc_enabled_capa[howmany(IWX_NUM_UCODE_TLV_CAPA, NBBY)]; 743 #define IWX_MAX_FW_CMD_VERSIONS 704 744 struct iwx_fw_cmd_version cmd_versions[IWX_MAX_FW_CMD_VERSIONS]; 745 int n_cmd_versions; 746 int sc_rate_n_flags_version; 747 int sc_use_mld_api; 748 749 int sc_intmask; 750 int sc_flags; 751 752 uint32_t sc_fh_init_mask; 753 uint32_t sc_hw_init_mask; 754 uint32_t sc_fh_mask; 755 uint32_t sc_hw_mask; 756 757 int sc_generation; 758 759 struct rwlock ioctl_rwl; 760 761 int sc_cap_off; /* PCIe caps */ 762 763 const char *sc_fwname; 764 struct iwx_fw_info sc_fw; 765 struct iwx_dma_info fw_mon; 766 int sc_fw_phy_config; 767 struct iwx_tlv_calib_ctrl sc_default_calib[IWX_UCODE_TYPE_MAX]; 768 769 struct iwx_nvm_data sc_nvm; 770 struct iwx_bf_data sc_bf; 771 const char *sc_pnvm_name; 772 773 int sc_tx_timer[IWX_NUM_TX_QUEUES]; 774 int sc_rx_ba_sessions; 775 776 struct task bgscan_done_task; 777 struct ieee80211_node_switch_bss_arg *bgscan_unref_arg; 778 size_t bgscan_unref_arg_size; 779 780 int sc_scan_last_antenna; 781 782 int sc_staid; 783 int sc_nodecolor; 784 785 uint8_t *sc_cmd_resp_pkt[IWX_TX_RING_COUNT]; 786 size_t sc_cmd_resp_len[IWX_TX_RING_COUNT]; 787 int sc_nic_locks; 788 789 struct taskq *sc_nswq; 790 791 struct iwx_rx_phy_info sc_last_phy_info; 792 int sc_ampdu_ref; 793 struct iwx_rxba_data sc_rxba_data[IWX_MAX_BAID]; 794 795 uint32_t sc_time_event_uid; 796 797 /* phy contexts. we only use the first one */ 798 struct iwx_phy_ctxt sc_phyctxt[IWX_NUM_PHY_CTX]; 799 800 struct iwx_notif_statistics sc_stats; 801 int sc_noise; 802 803 int sc_pm_support; 804 int sc_ltr_enabled; 805 806 int sc_integrated; 807 int sc_tx_with_siso_diversity; 808 int sc_max_tfd_queue_size; 809 int sc_ltr_delay; 810 int sc_xtal_latency; 811 int sc_low_latency_xtal; 812 int sc_uhb_supported; 813 int sc_umac_prph_offset; 814 int sc_imr_enabled; 815 816 #if NBPFILTER > 0 817 caddr_t sc_drvbpf; 818 819 union { 820 struct iwx_rx_radiotap_header th; 821 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 822 } sc_rxtapu; 823 #define sc_rxtap sc_rxtapu.th 824 int sc_rxtap_len; 825 826 union { 827 struct iwx_tx_radiotap_header th; 828 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 829 } sc_txtapu; 830 #define sc_txtap sc_txtapu.th 831 int sc_txtap_len; 832 #endif 833 }; 834 835 struct iwx_node { 836 struct ieee80211_node in_ni; 837 struct iwx_phy_ctxt *in_phyctxt; 838 uint8_t in_macaddr[ETHER_ADDR_LEN]; 839 840 uint16_t in_id; 841 uint16_t in_color; 842 843 struct iwx_rxq_dup_data dup_data; 844 845 int in_flags; 846 #define IWX_NODE_FLAG_HAVE_PAIRWISE_KEY 0x01 847 #define IWX_NODE_FLAG_HAVE_GROUP_KEY 0x02 848 }; 849 #define IWX_STATION_ID 0 850 #define IWX_AUX_STA_ID 1 851 #define IWX_MONITOR_STA_ID 2 852 853 #define IWX_ICT_SIZE 4096 854 #define IWX_ICT_COUNT (IWX_ICT_SIZE / sizeof (uint32_t)) 855 #define IWX_ICT_PADDR_SHIFT 12 856